[S] Change in coreboot[main]: mb/google/nissa/var/pujjoga: Generate SPD IDs
by Derek Huang (Code Review) 30 Apr '24
by Derek Huang (Code Review) 30 Apr '24
30 Apr '24
Attention is currently required from: Dinesh Gehlot, Felix Held, Kapil Porwal, Nick Vaccaro, Roger Wang, Shou-Chieh Hsu, Subrata Banik.
Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82135?usp=email )
Change subject: mb/google/nissa/var/pujjoga: Generate SPD IDs
......................................................................
Patch Set 3: Code-Review+2
--
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[XS] Change in libgfxinit[cros]: gma tgl: Pcode CDCLK_PREPARE_FOR_CHANGE is not mandatory
by Dinesh Gehlot (Code Review) 30 Apr '24
by Dinesh Gehlot (Code Review) 30 Apr '24
30 Apr '24
Attention is currently required from: Anil Kumar K, Jérémy Compostella.
Hello Anil Kumar K, Jérémy Compostella,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/libgfxinit/+/82147?usp=email
to review the following change.
Change subject: gma tgl: Pcode CDCLK_PREPARE_FOR_CHANGE is not mandatory
......................................................................
gma tgl: Pcode CDCLK_PREPARE_FOR_CHANGE is not mandatory
Pcode mailbox `CDCLK_PREPARE_FOR_CHANGE' command is not available till
BIOS Reset CPL and may fail when called too early.
This command is actually not mandatory to set the CDCLK sucessfully on
ADL platform. This patch keeps the `CDCLK_PREPARE_FOR_CHANGE' command
but ignores return errors if any.
Change-Id: I0514e404a7b580d1e35af7b39c1bd77183f11058
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com>
---
M common/tigerlake/hw-gfx-gma-power_and_clocks.adb
1 file changed, 5 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/47/82147/1
diff --git a/common/tigerlake/hw-gfx-gma-power_and_clocks.adb b/common/tigerlake/hw-gfx-gma-power_and_clocks.adb
index 68636f7..41331b9 100644
--- a/common/tigerlake/hw-gfx-gma-power_and_clocks.adb
+++ b/common/tigerlake/hw-gfx-gma-power_and_clocks.adb
@@ -328,7 +328,7 @@
Wait_Ready => True,
Success => Success);
- if not Success then
+ if not Success and not Config.CPU_Alderlake then
pragma Debug (Debug.Put_Line
("ERROR: PCODE not ready for frequency change."));
return;
@@ -348,7 +348,8 @@
Registers.Wait_Set_Mask
(Register => Registers.CDCLK_PLL_ENABLE,
Mask => CDCLK_PLL_ENABLE_PLL_LOCK or
- CDCLK_PLL_ENABLE_FREQ_REQ_ACK);
+ CDCLK_PLL_ENABLE_FREQ_REQ_ACK,
+ Success => Success);
Registers.Write
(Register => Registers.CDCLK_PLL_ENABLE,
Value => Word32(PLL_Ratio) or
@@ -413,7 +414,8 @@
Command => (if CDClk <= 312_000_000 then 0
elsif CDClk <= 326_400_000 then 1
elsif CDClk <= 556_800_000 then 2
- else 3));
+ else 3),
+ Wait_Ready => True);
Config.CDClk := CDClk;
end Set_CDClk;
--
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Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com>
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0
[XL] Change in libgfxinit[cros]: gma: Support ADL-P CDClk clock crawl
by Dinesh Gehlot (Code Review) 30 Apr '24
by Dinesh Gehlot (Code Review) 30 Apr '24
30 Apr '24
Attention is currently required from: Tim Wawrzynczak.
Hello Tim Wawrzynczak,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/libgfxinit/+/82146?usp=email
to review the following change.
Change subject: gma: Support ADL-P CDClk clock crawl
......................................................................
gma: Support ADL-P CDClk clock crawl
Setting up CDCLK is a little different for ADL-P, i915 calls it
adlp_cdclk_pll_crawl.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: Id01752a41e4e401a5f759453c12f368395eebdf2
---
M common/hw-gfx-gma-config.ads.template
M common/tigerlake/Makefile.inc
M common/tigerlake/hw-gfx-gma-connectors-tc.adb
M common/tigerlake/hw-gfx-gma-port_detect.adb
A common/tigerlake/hw-gfx-gma-power_and_clocks-tgl.adb
A common/tigerlake/hw-gfx-gma-power_and_clocks-tgl.ads
A common/tigerlake/hw-gfx-gma-power_and_clocks-xelpd.adb
A common/tigerlake/hw-gfx-gma-power_and_clocks-xelpd.ads
M common/tigerlake/hw-gfx-gma-power_and_clocks.adb
M common/tigerlake/hw-gfx-gma-power_and_clocks.ads
10 files changed, 1,293 insertions(+), 485 deletions(-)
git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/46/82146/1
diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template
index b56086f..41fe590 100644
--- a/common/hw-gfx-gma-config.ads.template
+++ b/common/hw-gfx-gma-config.ads.template
@@ -262,6 +262,7 @@
Can_Switch_CDClk : <hswbool> := Broadwell_On;
Has_Fractional_RawClk : <genbool> := Cannon_Point_On;
Has_New_Type_C_PLL_Enable : <tglbool> := Alderlake_On;
+ Has_CDClk_PLL_Crawl : <tglbool> := Alderlake_On;
----------- DDI: -------------
End_EDP_Training_Late : <genbool> := Gen_Haswell;
@@ -302,12 +303,17 @@
Has_IPS_CTL_Mailbox : <hswbool> := CPU_Broadwell;
Has_Per_Pipe_SRD : <hswbool> := Broadwell_On;
+ Has_XELPD_Power_Domains : <tglbool> := Alderlake_On;
----------- GTT: -------------
Has_64bit_GTT : <hswbool> := Broadwell_On;
----------- Type-C: ----------
Has_Type_C_Ports : <genbool> := Tigerlake_On;
+ Need_TC_PHY_Ownership : <tglbool> := Alderlake_On;
+ Need_Loadgen_Select : <tglbool> := Alderlake_On;
+ Need_DP_Alt_Switch : <tglbool> := Alderlake_On;
+ Has_TCSS_DDI_Status : <tglbool> := Alderlake_On;
----------- Rawclk -----------
Need_Rawclk_Numerator : <genbool> := Tigerlake_On;
diff --git a/common/tigerlake/Makefile.inc b/common/tigerlake/Makefile.inc
index b76f2fe..c5a1c79 100644
--- a/common/tigerlake/Makefile.inc
+++ b/common/tigerlake/Makefile.inc
@@ -2,6 +2,10 @@
gfxinit-y += hw-gfx-gma-combo_phy.ads
gfxinit-y += hw-gfx-gma-power_and_clocks.adb
gfxinit-y += hw-gfx-gma-power_and_clocks.ads
+gfxinit-y += hw-gfx-gma-power_and_clocks-tgl.adb
+gfxinit-y += hw-gfx-gma-power_and_clocks-tgl.ads
+gfxinit-y += hw-gfx-gma-power_and_clocks-xelpd.adb
+gfxinit-y += hw-gfx-gma-power_and_clocks-xelpd.ads
gfxinit-y += hw-gfx-gma-connectors.adb
gfxinit-y += hw-gfx-gma-connectors-tc.adb
gfxinit-y += hw-gfx-gma-connectors-tc.ads
diff --git a/common/tigerlake/hw-gfx-gma-connectors-tc.adb b/common/tigerlake/hw-gfx-gma-connectors-tc.adb
index 976c5f2..b1c284e 100644
--- a/common/tigerlake/hw-gfx-gma-connectors-tc.adb
+++ b/common/tigerlake/hw-gfx-gma-connectors-tc.adb
@@ -44,6 +44,25 @@
DDI_TC5 => Registers.DKL_DP_MODE_5,
DDI_TC6 => Registers.DKL_DP_MODE_6);
+ DKL_PCS_DW5 : constant Port_Regs_Array :=
+ Port_Regs_Array'
+ (DDI_TC1 => Registers.DKL_PCS_DW5_1,
+ DDI_TC2 => Registers.DKL_PCS_DW5_2,
+ DDI_TC3 => Registers.DKL_PCS_DW5_3,
+ DDI_TC4 => Registers.DKL_PCS_DW5_4,
+ others => Registers.DKL_PCS_DW5_1);
+
+ TCSS_DDI_STATUS : constant Port_Regs_Array :=
+ Port_Regs_Array'
+ (DDI_TC1 => Registers.TCSS_DDI_STATUS_1,
+ DDI_TC2 => Registers.TCSS_DDI_STATUS_2,
+ DDI_TC3 => Registers.TCSS_DDI_STATUS_3,
+ DDI_TC4 => Registers.TCSS_DDI_STATUS_4,
+ others => Registers.TCSS_DDI_STATUS_1);
+
+ TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT : constant := 1 * 2 ** 0;
+ TCSS_DDI_STATUS_READY : constant := 1 * 2 ** 2;
+
function DP_PIN_ASSIGNMENT_SHIFT (P : USBC_Port) return natural is
(case P is
when DDI_TC1 => 0,
@@ -144,6 +163,7 @@
DDI_BUF_CTL_PORT_WIDTH_2_LANES : constant := 1 * 2 ** 1;
DDI_BUF_CTL_PORT_WIDTH_4_LANES : constant := 3 * 2 ** 1;
DDI_BUF_CTL_IDLE_STATUS : constant := 1 * 2 ** 7;
+ DDI_BUF_CTL_TC_PHY_OWNERSHIP : constant := 1 * 2 ** 6;
type DDI_BUF_CTL_PORT_WIDTH_T is array (HW.GFX.DP_Lane_Count) of Word32;
DDI_BUF_CTL_PORT_WIDTH : constant DDI_BUF_CTL_PORT_WIDTH_T :=
@@ -401,10 +421,17 @@
Success: out Boolean)
is
begin
- Registers.Is_Set_Mask
- (Register => Fia_Regs (Port).PORT_TX_DFLEXDPPMS,
- Mask => DP_PHY_MODE_STATUS_COMPLETE (Port),
- Result => Success);
+ if Config.Need_TC_PHY_Ownership then
+ Registers.Is_Set_Mask
+ (Register => TCSS_DDI_STATUS (Port),
+ Mask => TCSS_DDI_STATUS_READY,
+ Result => Success);
+ else
+ Registers.Is_Set_Mask
+ (Register => Fia_Regs (Port).PORT_TX_DFLEXDPPMS,
+ Mask => DP_PHY_MODE_STATUS_COMPLETE (Port),
+ Result => Success);
+ end if;
end Is_DP_Phy_Mode_Status_Complete;
procedure Connect
@@ -437,17 +464,31 @@
return;
end if;
- Registers.Set_Mask
- (Register => Fia_Regs (Port).PORT_TX_DFLEXDPCSSS,
- Mask => DP_PHY_MODE_STATUS_NOT_SAFE (Port));
+ -- Take ownership and check live status
+ if Config.Need_TC_PHY_Ownership then
+ -- TODO: also check SDEISR for legacy "connection"
+ Registers.Is_Set_Mask
+ (Register => TCSS_DDI_STATUS (Port),
+ Mask => TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT,
+ Result => Success);
- Registers.Is_Set_Mask
- (Register => Fia_Regs (Port).PORT_TX_DFLEXDPSP,
- Mask => TC_LIVE_STATE_TC (Port),
- Result => Success);
+ if Success then
+ Registers.Set_Mask
+ (Register => DDI_BUF_CTL (Port),
+ Mask => DDI_BUF_CTL_TC_PHY_OWNERSHIP);
+ end if;
+ else
+ -- TODO: also check SDEISR for legacy "connection"
+ Registers.Is_Set_Mask
+ (Register => Fia_Regs (Port).PORT_TX_DFLEXDPSP,
+ Mask => TC_LIVE_STATE_TC (Port),
+ Result => Success);
- if not Success then
- pragma Debug (Debug.Put_Line ("Type-C Port is not connected."));
+ if Success then
+ Registers.Set_Mask
+ (Register => Fia_Regs (Port).PORT_TX_DFLEXDPCSSS,
+ Mask => DP_PHY_MODE_STATUS_NOT_SAFE (Port));
+ end if;
end if;
pragma Debug
@@ -461,13 +502,19 @@
procedure Disconnect (Port : USBC_Port) is
begin
- Registers.Unset_Mask
- (Register => Fia_Regs (Port).PORT_TX_DFLEXDPCSSS,
- Mask => Word32 (Fia_Index (Port)));
+ if Config.Need_TC_PHY_Ownership then
+ Registers.Unset_Mask
+ (Register => DDI_BUF_CTL (Port),
+ Mask => DDI_BUF_CTL_TC_PHY_OWNERSHIP);
+ else
+ Registers.Unset_Mask
+ (Register => Fia_Regs (Port).PORT_TX_DFLEXDPCSSS,
+ Mask => Word32 (Fia_Index (Port)));
- Registers.Wait_Unset_mask
- (Register => Fia_Regs (Port).PORT_TX_DFLEXDPPMS,
- Mask => DP_PHY_MODE_STATUS_COMPLETE (Port));
+ Registers.Wait_Unset_mask
+ (Register => Fia_Regs (Port).PORT_TX_DFLEXDPPMS,
+ Mask => DP_PHY_MODE_STATUS_COMPLETE (Port));
+ end if;
end Disconnect;
---------------------------------------------------------------------
@@ -483,6 +530,14 @@
Shift_Left (Buf_Trans.Deemphasis_Control, 8) or
Shift_Left (Buf_Trans.Preshoot_Control, 13);
DKL_TX_DP20BITMODE : constant := 1 * 2 ** 2;
+
+ function DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1 (N : Word32) return Word32
+ is (Shift_Left (N and 16#3#, 3));
+ function DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2 (N : Word32) return Word32
+ is (Shift_Left (N and 16#3#, 5));
+
+ DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK : constant := 16#18#;
+ DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK : constant := 16#60#;
begin
for Lane in 0 .. 1 loop
Set_HIP_For_Port (Port, Lane);
@@ -493,6 +548,31 @@
(Vswing_Regs (Port).DKL_TX_DPCNTL1, DPcnt_Mask, DPcnt_Val);
Registers.Unset_Mask
(Vswing_Regs (Port).DKL_TX_DPCNTL2, DKL_TX_DP20BITMODE);
+
+ if Config.Need_Loadgen_Select then
+ declare
+ Val : Word32;
+ begin
+ -- if Port in USBC1_HDMI .. USBC6_HDMI then
+ -- if Lane = 0 then
+ -- Val := DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1 (0) or
+ -- DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2 (2);
+ -- else
+ -- Val := DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1 (3) or
+ -- DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2 (3);
+ -- end if;
+ -- else
+ Val := DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1 (3) or
+ DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2 (3);
+ -- end if;
+
+ Registers.Unset_And_Set_Mask
+ (Register => Vswing_Regs (Port).DKL_TX_DPCNTL2,
+ Mask_Unset => DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK or
+ DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,
+ Mask_Set => Val);
+ end;
+ end if;
end loop;
end Set_Vswing_And_Deemphasis;
@@ -504,6 +584,7 @@
Link : DP_Link;
Train_Set : DP_Info.Train_Set)
is
+ DKL_PCS_DW5_CORE_SOFTRESET : constant := 1 * 2 ** 11;
function To_Buf_Trans_Index
(Set : DP_Info.Train_Set) return Buffer_Trans_Range
is
@@ -565,13 +646,24 @@
Set_Vswing_And_Deemphasis (Port, Buf_Trans);
+ if Config.Need_DP_Alt_Switch and not Was_Enabled then
+ for Lane in 0 .. 1 loop
+ Set_HIP_For_Port (Port, Lane);
+ Registers.Unset_Mask
+ (Register => DKL_PCS_DW5 (Port),
+ Mask => DKL_PCS_DW5_CORE_SOFTRESET);
+ end loop;
+ end if;
+
Registers.Unset_And_Set_Mask
(Register => DDI_BUF_CTL (Port),
Mask_Unset => DDI_BUF_CTL_TRANS_SELECT_MASK or
DDI_BUF_CTL_PORT_REVERSAL or
DDI_BUF_CTL_PORT_WIDTH_MASK,
Mask_Set => DDI_BUF_CTL_BUFFER_ENABLE or
- DDI_BUF_CTL_PORT_WIDTH (Link.Lane_Count));
+ DDI_BUF_CTL_PORT_WIDTH (Link.Lane_Count) or
+ (if Config.Need_TC_PHY_Ownership
+ then DDI_BUF_CTL_TC_PHY_OWNERSHIP else 0));
Registers.Posting_Read (DDI_BUF_CTL (Port));
if not Was_Enabled then
diff --git a/common/tigerlake/hw-gfx-gma-port_detect.adb b/common/tigerlake/hw-gfx-gma-port_detect.adb
index 681172b..d9b8f60 100644
--- a/common/tigerlake/hw-gfx-gma-port_detect.adb
+++ b/common/tigerlake/hw-gfx-gma-port_detect.adb
@@ -16,6 +16,7 @@
with HW.GFX.GMA.Registers;
with HW.GFX.GMA.Config_Helpers;
with HW.GFX.GMA.Connectors.TC;
+with HW.GFX.GMA.Power_And_Clocks;
with HW.Debug;
with GNAT.Source_Info;
@@ -26,6 +27,7 @@
function SDEISR_MASK (Port : Active_Port_Type) return Word32
is (case Port is
+ when eDP => 16#1_0000#,
when DP1 | HDMI1 => 16#1_0000#,
when DP2 | HDMI2 => 16#2_0000#,
when DP3 | HDMI3 => 16#4_0000#,
@@ -64,22 +66,10 @@
procedure Initialize
is
INIT_DISPLAY_DETECTED : constant := 1 * 2 ** 0;
- Internal_Detected : Boolean;
Success : Boolean;
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
- -- only for DDI_A / eDP
- if Config.Has_Presence_Straps and not Config.Ignore_Presence_Straps then
- Registers.Is_Set_Mask
- (Register => Registers.DDI_BUF_CTL_A,
- Mask => INIT_DISPLAY_DETECTED,
- Result => Internal_Detected);
- else
- Internal_Detected := True;
- end if;
- Config.Valid_Port (eDP) := Internal_Detected;
-
Registers.Unset_And_Set_Mask
(Register => Registers.SHPD_FILTER_CNT,
Mask_Unset => 16#1_ffff#,
@@ -116,15 +106,25 @@
TC_HOTPLUG_CTL_HPD_ENABLE (USBC6_DP)); -- also USBC6_HDMI
-- Validity can only be detected via hotplug
+ Config.Valid_Port (eDP) := True;
for Port in DP1 .. HDMI3 loop
Config.Valid_Port (Port) := True;
end loop;
- -- For Type-C ports, we can check if the IOM PHY status is 'Complete'.
+ -- For Type-C ports, we can check if the IOM PHY status is 'Complete',
+ -- then perform the connection flow for all connected ports.
+ Power_And_Clocks.Power_Up_Aux ;
for Port in USBC1_DP .. USBC6_HDMI loop
- Connectors.TC.Is_DP_Phy_Mode_Status_Complete
- (Port => Config_Helpers.To_GPU_Port (Pipe_Index'First, Port),
- Success => Config.Valid_Port (Port));
+ declare
+ G : GPU_Port;
+ Success : Boolean;
+ begin
+ G := Config_Helpers.To_GPU_Port (Pipe_Index'First, Port);
+ if G in USBC_Port then
+ Connectors.TC.Connect (G, Success);
+ Config.Valid_Port (Port) := Success;
+ end if;
+ end;
end loop;
-- TCCOLD should be blocked first before accessing FIA registers
@@ -134,12 +134,14 @@
-- In order to avoid keeping track of the state and constantly
-- blocking and unblocking, we just block it once at the beginning and
-- leave it that way.
- Connectors.TC.TC_Cold_Request (Connectors.TC.Block, Success);
- if not Success then
- Debug.Put_Line ("Failed to bock TCCOLD, Type-C will not work!");
- for Port in USBC1_DP .. USBC6_HDMI loop
- Config.Valid_Port (Port) := False;
- end loop;
+ if not Config.Has_XELPD_Power_Domains then
+ Connectors.TC.TC_Cold_Request (Connectors.TC.Block, Success);
+ if not Success then
+ Debug.Put_Line ("Failed to bock TCCOLD, Type-C will not work!");
+ for Port in USBC1_DP .. USBC6_HDMI loop
+ Config.Valid_Port (Port) := False;
+ end loop;
+ end if;
end if;
end Initialize;
diff --git a/common/tigerlake/hw-gfx-gma-power_and_clocks-tgl.adb b/common/tigerlake/hw-gfx-gma-power_and_clocks-tgl.adb
new file mode 100644
index 0000000..b9417af
--- /dev/null
+++ b/common/tigerlake/hw-gfx-gma-power_and_clocks-tgl.adb
@@ -0,0 +1,425 @@
+--
+-- Copyright (C) 2022 Google, LLC
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with GNAT.Source_Info;
+with HW.Debug;
+with HW.GFX.GMA.Config;
+with HW.GFX.GMA.Registers;
+with HW.GFX.GMA.Connectors.TC;
+
+use type HW.Word64;
+
+package body HW.GFX.GMA.Power_And_Clocks.TGL is
+
+ type Power_Domain_Types is (Power_Well, Power_DDI, Power_AUX);
+ subtype PW_Domain is Power_Domain range PW1 .. PW5;
+ subtype DDI_Domain is Power_Domain range DDI_A .. DDI_USBC6;
+ subtype AUX_Domain is Power_Domain range AUX_A .. AUX_USBC6;
+ subtype AUX_USBC_Domain is Power_Domain range AUX_USBC1 .. AUX_USBC6;
+
+ function HIP_INDEX_REG (A : AUX_USBC_Domain) return Registers.Registers_Index
+ is (if A <= AUX_USBC4
+ then Registers.HIP_INDEX_REG0
+ else Registers.HIP_INDEX_REG1);
+
+ function HIP_INDEX_VAL (A : AUX_USBC_Domain; Val : Word32) return Word32 is
+ (case A is
+ when AUX_USBC1 | AUX_USBC3 | AUX_USBC5 => Val * 2 ** 0,
+ when AUX_USBC2 | AUX_USBC4 | AUX_USBC6 => Val * 2 ** 8);
+
+ type DKL_Regs is array (AUX_USBC_Domain) of Registers.Registers_Index;
+ DKL_CMN_UC_DW_27 : constant DKL_Regs := DKL_Regs'
+ (AUX_USBC1 => Registers.DKL_CMN_UC_DW_27_1,
+ AUX_USBC2 => Registers.DKL_CMN_UC_DW_27_2,
+ AUX_USBC3 => Registers.DKL_CMN_UC_DW_27_3,
+ AUX_USBC4 => Registers.DKL_CMN_UC_DW_27_4,
+ AUX_USBC5 => Registers.DKL_CMN_UC_DW_27_5,
+ AUX_USBC6 => Registers.DKL_CMN_UC_DW_27_6);
+
+ ----------------------------------------------------------------------------
+
+ function Power_Domain_Type (PD : Power_Domain) return Power_Domain_Types is
+ (if PD in PW_Domain then Power_Well
+ elsif PD in DDI_Domain then Power_DDI
+ else Power_AUX);
+
+ type Power_Well_Regs is array (Power_Domain_Types) of Registers.Registers_Index;
+ PWR_CTL_BIOS : constant Power_Well_Regs :=
+ (Power_Well => Registers.PWR_WELL_CTL_BIOS,
+ Power_DDI => Registers.PWR_DDI_CTL_BIOS,
+ Power_AUX => Registers.PWR_AUX_CTL_BIOS);
+ PWR_CTL_DRIVER : constant Power_Well_Regs :=
+ (Power_Well => Registers.PWR_WELL_CTL_DRIVER,
+ Power_DDI => Registers.PWR_DDI_CTL_DRIVER,
+ Power_AUX => Registers.PWR_AUX_CTL_DRIVER);
+
+ package Rep is
+ function PW_Index (PW : PW_Domain) return natural
+ with Post => PW_Index'Result < PW_Domain'Range_Length;
+ function DDI_Index (DDI : DDI_Domain) return natural
+ with Post => DDI_Index'Result < DDI_Domain'Range_Length;
+ function AUX_Index (AUX : AUX_Domain) return natural
+ with Post => Aux_Index'Result < AUX_Domain'Range_Length;
+ end Rep;
+
+ package body Rep is
+ function PW_Index (PW : PW_Domain) return natural
+ with
+ SPARK_Mode => Off
+ is
+ begin
+ return PW'Enum_Rep - PW1'Enum_Rep;
+ end PW_Index;
+
+ function DDI_Index (DDI : DDI_Domain) return natural
+ with
+ SPARK_Mode => Off
+ is
+ begin
+ return DDI'Enum_Rep - DDI_A'Enum_Rep;
+ end DDI_Index;
+
+ function AUX_Index (AUX : AUX_Domain) return natural
+ with
+ SPARK_Mode => Off
+ is
+ begin
+ return AUX'Enum_Rep - AUX_A'Enum_Rep;
+ end AUX_Index;
+ end Rep;
+
+ function PW_Request_Mask (PW : PW_Domain) return Word32 is
+ (2 * 2 ** (2 * Rep.PW_Index (PW)));
+ function PW_State_Mask (PW : PW_Domain) return Word32 is
+ (1 * 2 ** (2 * Rep.PW_Index (PW)));
+
+ function DDI_Request_Mask (DDI : DDI_Domain) return Word32 is
+ (2 * 2 ** (2 * Rep.DDI_Index (DDI)));
+ function DDI_State_Mask (DDI : DDI_Domain) return Word32 is
+ (1 * 2 ** (2 * Rep.DDI_Index (DDI)));
+
+ function AUX_Request_Mask (AUX : AUX_Domain) return Word32 is
+ (2 * 2 ** (2 * Rep.AUX_Index (AUX)));
+ function AUX_State_Mask (AUX : AUX_Domain) return Word32 is
+ (1 * 2 ** (2 * Rep.AUX_Index (AUX)));
+
+ ----------------------------------------------------------------------------
+
+ FUSE_STATUS_PG0_DIST_STATUS : constant := 1 * 2 ** 27;
+ type Power_Well_Values is array (PW_Domain) of Word32;
+ FUSE_STATUS_PGx_DIST_STATUS : constant Power_Well_Values :=
+ (PW1 => 1 * 2 ** 26,
+ PW2 => 1 * 2 ** 25,
+ PW3 => 1 * 2 ** 24,
+ PW4 => 1 * 2 ** 23,
+ PW5 => 1 * 2 ** 22);
+
+ ----------------------------------------------------------------------------
+
+ function Power_Request_Mask (PD : Power_Domain) return Word32 is
+ begin
+ if PD in PW_Domain then
+ return PW_Request_Mask (PD);
+ elsif PD in DDI_Domain then
+ return DDI_Request_Mask (PD);
+ else
+ return AUX_Request_Mask (PD);
+ end if;
+ end Power_Request_Mask;
+
+ function Power_State_Mask (PD : Power_Domain) return Word32 is
+ begin
+ if PD in PW_Domain then
+ return PW_State_Mask (PD);
+ elsif PD in DDI_Domain then
+ return DDI_State_Mask (PD);
+ else
+ return AUX_State_Mask (PD);
+ end if;
+ end Power_State_Mask;
+
+ ----------------------------------------------------------------------------
+
+ type AUX_CTL_Array is array (AUX_USBC_Domain) of Registers.Registers_Index;
+ AUX_CTL_Regs : constant AUX_CTL_Array :=
+ AUX_CTL_Array'
+ (AUX_USBC1 => Registers.DDI_AUX_CTL_USBC1,
+ AUX_USBC2 => Registers.DDI_AUX_CTL_USBC2,
+ AUX_USBC3 => Registers.DDI_AUX_CTL_USBC3,
+ AUX_USBC4 => Registers.DDI_AUX_CTL_USBC4,
+ AUX_USBC5 => Registers.DDI_AUX_CTL_USBC5,
+ AUX_USBC6 => Registers.DDI_AUX_CTL_USBC6);
+
+ function Aux_To_Port (PD : AUX_USBC_Domain) return USBC_Port
+ is (case PD is
+ when AUX_USBC1 => DDI_TC1,
+ when AUX_USBC2 => DDI_TC2,
+ when AUX_USBC3 => DDI_TC3,
+ when AUX_USBC4 => DDI_TC4,
+ when AUX_USBC5 => DDI_TC5,
+ when AUX_USBC6 => DDI_TC6);
+
+ procedure Pre_On (PD : Power_Domain)
+ is
+ DP_AUX_CH_CTL_TBT_IO : constant := 1 * 2 ** 11;
+ begin
+ if PD in AUX_USBC_Domain then
+ -- Disable TBT IO mode for AUX
+ Registers.Unset_Mask
+ (Register => AUX_CTL_Regs (PD),
+ Mask => DP_AUX_CH_CTL_TBT_IO);
+ elsif PD = PW1 then
+ Registers.Wait_Set_Mask
+ (Register => Registers.FUSE_STATUS,
+ Mask => FUSE_STATUS_PG0_DIST_STATUS);
+ end if;
+ end Pre_On;
+
+ procedure Pre_Off (PD : Power_Domain) is
+ begin
+ if PD in AUX_USBC_Domain then
+ Connectors.TC.Disconnect (Aux_To_Port (PD));
+ end if;
+ end Pre_Off;
+
+ procedure Post_On (PD : Power_Domain)
+ is
+ DKL_CMN_UC_DW_27_UC_HEALTH : constant := 1 * 2 ** 15;
+ begin
+ if PD in PW_Domain then
+ Registers.Wait_Set_Mask (Registers.FUSE_STATUS,
+ FUSE_STATUS_PGx_DIST_STATUS (PD));
+ elsif PD in AUX_USBC_Domain then
+ Registers.Write (HIP_INDEX_REG (PD), HIP_INDEX_VAL (PD, 2));
+ Registers.Wait_Set_Mask
+ (Register => DKL_CMN_UC_DW_27 (PD),
+ Mask => DKL_CMN_UC_DW_27_UC_HEALTH);
+ end if;
+ end Post_On;
+
+ procedure PD_On (PD : Power_Domain)
+ is
+ Ctl1, Ctl2 : Word32;
+ PD_Type : constant Power_Domain_Types := Power_Domain_Type (PD);
+ Success : Boolean;
+ DP_AUX_CH_CTL_TBT_IO : constant := 1 * 2 ** 11;
+ begin
+ Pre_On (PD);
+
+ Registers.Read (PWR_CTL_BIOS (PD_Type), Ctl1);
+ Registers.Read (PWR_CTL_DRIVER (PD_Type), Ctl2);
+
+ if ((Ctl1 or Ctl2) and Power_Request_Mask (PD)) = 0 then
+ Registers.Wait_Unset_Mask
+ (Register => PWR_CTL_DRIVER (PD_Type),
+ Mask => Power_State_Mask (PD));
+ end if;
+
+ if (Ctl2 and Power_Request_Mask (PD)) = 0 then
+ Registers.Set_Mask (PWR_CTL_DRIVER (PD_Type), Power_Request_Mask (PD));
+ Registers.Wait_Set_Mask
+ (Register => PWR_CTL_DRIVER (PD_Type),
+ Mask => Power_State_Mask (PD),
+ Success => Success);
+
+ if not Success then
+ Debug.Put_Line ("Failed to enable power domain!");
+ return;
+ end if;
+ end if;
+
+ Post_On (PD);
+ end PD_On;
+
+ procedure PD_Off (PD : Power_Domain)
+ is
+ Ctl1, Ctl2 : Word32;
+ PD_Type : constant Power_Domain_Types := Power_Domain_Type (PD);
+ begin
+ pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+ Registers.Read (PWR_CTL_BIOS (PD_Type), Ctl1);
+ Registers.Read (PWR_CTL_DRIVER (PD_Type), Ctl2);
+
+ -- PW1 is "always-on"
+ if PD = PW1 then
+ return;
+ end if;
+
+ if ((Ctl1 or Ctl2) and Power_Request_Mask (PD)) /= 0 then
+ Registers.Wait_Set_Mask
+ (Register => PWR_CTL_DRIVER (PD_Type),
+ Mask => Power_State_Mask (PD));
+ end if;
+
+ Pre_Off (PD);
+
+ if (Ctl2 and Power_Request_Mask (PD)) /= 0 then
+ Registers.Unset_Mask (PWR_CTL_DRIVER (PD_Type), Power_Request_Mask (PD));
+ Registers.Unset_Mask (PWR_CTL_BIOS (PD_Type), Power_Request_Mask (PD));
+ end if;
+ end PD_Off;
+
+ type Port_Array is array (natural range <>) of Active_Port_Type;
+ DDI_TC : constant Port_Array :=
+ Port_Array'
+ (USBC1_DP, USBC2_DP, USBC3_DP, USBC4_DP, USBC5_DP, USBC6_DP,
+ USBC1_HDMI, USBC2_HDMI, USBC3_HDMI, USBC4_HDMI, USBC5_HDMI,
+ USBC6_HDMI);
+
+ function Need_PD (PD : Power_Domain; Configs : Pipe_Configs) return Boolean
+ is
+ function Any_Port_Is (Port : Active_Port_Type) return Boolean is
+ (Configs (Primary).Port = Port or Configs (Secondary).Port = Port or
+ Configs (Tertiary).Port = Port);
+
+ function Any_Port_In (Ports : Port_Array) return Boolean is
+ begin
+ for P of Ports loop
+ if (Configs (Primary).Port = P) or
+ (Configs (Secondary).Port = P) or
+ (Configs (Tertiary).Port = P)
+ then
+ return True;
+ end if;
+ end loop;
+ return False;
+ end Any_Port_In;
+
+ function Num_Active_Pipes return Natural is
+ Count : Natural := 0;
+ begin
+ for I in Pipe_Index loop
+ if Configs (I).Port /= Disabled then
+ Count := Count + 1;
+ end if;
+ end loop;
+ return Count;
+ end Num_Active_Pipes;
+ begin
+ case PD is
+ when PW1 | PW2 =>
+ if Num_Active_Pipes >= 1 or Any_Port_In (DDI_TC) then
+ return True;
+ end if;
+ when PW3 =>
+ if Num_Active_Pipes >= 2 or Any_Port_In (DDI_TC) then
+ return True;
+ end if;
+ when PW4 =>
+ if Num_Active_Pipes >= 3 then
+ return True;
+ end if;
+ when PW5 => return False;
+ when DDI_A | AUX_A =>
+ if Any_Port_Is (DP1) or Any_Port_Is (HDMI1) or Any_Port_Is (eDP) then
+ return True;
+ end if;
+ when DDI_B | AUX_B =>
+ if Any_Port_Is (DP2) or Any_Port_Is (HDMI2) then
+ return True;
+ end if;
+ when DDI_C | AUX_C =>
+ if Any_Port_Is (DP3) or Any_Port_Is (HDMI3) then
+ return True;
+ end if;
+ when DDI_USBC1 | AUX_USBC1 =>
+ return Any_Port_Is (USBC1_DP) or Any_Port_Is (USBC1_HDMI);
+ when DDI_USBC2 | AUX_USBC2 =>
+ return Any_Port_Is (USBC2_DP) or Any_Port_Is (USBC2_HDMI);
+ when DDI_USBC3 | AUX_USBC3 =>
+ return Any_Port_Is (USBC3_DP) or Any_Port_Is (USBC3_HDMI);
+ when DDI_USBC4 | AUX_USBC4 =>
+ return Any_Port_Is (USBC4_DP) or Any_Port_Is (USBC4_HDMI);
+ when DDI_USBC5 | AUX_USBC5 =>
+ return Any_Port_Is (USBC5_DP) or Any_Port_Is (USBC5_HDMI);
+ when DDI_USBC6 | AUX_USBC6 =>
+ return Any_Port_Is (USBC6_DP) or Any_Port_Is (USBC6_HDMI);
+ end case;
+
+ return False;
+ end Need_PD;
+
+ procedure Aux_Off is
+ begin
+ for AUX in reverse AUX_USBC1 .. AUX_USBC6 loop
+ PD_Off (AUX);
+ end loop;
+ end Aux_off;
+
+ procedure Init_Power is
+ begin
+ PD_On (PW1);
+ end Init_Power;
+
+ procedure Power_Set_To (Configs : Pipe_Configs) is
+ begin
+ for PD in reverse Power_Domain loop
+ if not Need_PD (PD, Configs) then
+ PD_Off (PD);
+ end if;
+ end loop;
+
+ for PD in Power_Domain loop
+ if Need_PD (PD, Configs) then
+ PD_On (PD);
+ end if;
+ end loop;
+ end Power_Set_To;
+
+ procedure Power_Up (Old_Configs, New_Configs : Pipe_Configs)
+ is
+ Success : Boolean;
+ begin
+ pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+ Connectors.TC.TC_Cold_Request (Connectors.TC.Block, Success);
+ if not Success then
+ Debug.Put_Line ("Failed to unblock TCCOLD");
+ end if;
+
+ for PD in Power_Domain loop
+ if not Need_PD (PD, Old_Configs) and Need_PD (PD, New_Configs) then
+ PD_On (PD);
+ end if;
+ end loop;
+ end Power_Up;
+
+ procedure Power_Down (Old_Configs, Tmp_Configs, New_Configs : Pipe_Configs)
+ is
+ begin
+ for PD in reverse Power_Domain loop
+ if (Need_PD (PD, Old_Configs) or Need_PD (PD, Tmp_Configs)) and
+ not Need_PD (PD, New_Configs)
+ then
+ PD_Off (PD);
+ end if;
+ end loop;
+ end Power_Down;
+
+ procedure All_Off is
+ begin
+ for AUX in reverse AUX_A .. AUX_USBC6 loop
+ PD_Off (AUX);
+ end loop;
+
+ for DDI in reverse DDI_A .. DDI_USBC6 loop
+ PD_Off (DDI);
+ end loop;
+
+ for PW in reverse PW1 .. PW5 loop
+ PD_Off (PW);
+ end loop;
+ end All_Off;
+
+end HW.GFX.GMA.Power_And_Clocks.TGL;
diff --git a/common/tigerlake/hw-gfx-gma-power_and_clocks-tgl.ads b/common/tigerlake/hw-gfx-gma-power_and_clocks-tgl.ads
new file mode 100644
index 0000000..cfbfe19
--- /dev/null
+++ b/common/tigerlake/hw-gfx-gma-power_and_clocks-tgl.ads
@@ -0,0 +1,31 @@
+-- (C) 2022 Google, LLC
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+private package HW.GFX.GMA.Power_And_Clocks.TGL is
+
+ type Power_Domain is
+ (PW1, PW2, PW3, PW4, PW5,
+ AUX_A, AUX_B, AUX_C,
+ AUX_USBC1, AUX_USBC2, AUX_USBC3, AUX_USBC4, AUX_USBC5, AUX_USBC6,
+ DDI_A, DDI_B, DDI_C,
+ DDI_USBC1, DDI_USBC2, DDI_USBC3, DDI_USBC4, DDI_USBC5, DDI_USBC6);
+
+ procedure Power_Set_To (Configs : Pipe_Configs);
+ procedure Power_Up (Old_Configs, New_Configs : Pipe_Configs);
+ procedure Power_Down (Old_Configs, Tmp_Configs, New_Configs : Pipe_Configs);
+ procedure All_Off;
+ function Need_PD (PD : Power_Domain; Configs : Pipe_Configs) return Boolean;
+ procedure Init_Power;
+ procedure Aux_Off;
+
+end HW.GFX.GMA.Power_And_Clocks.TGL;
diff --git a/common/tigerlake/hw-gfx-gma-power_and_clocks-xelpd.adb b/common/tigerlake/hw-gfx-gma-power_and_clocks-xelpd.adb
new file mode 100644
index 0000000..b2e9769
--- /dev/null
+++ b/common/tigerlake/hw-gfx-gma-power_and_clocks-xelpd.adb
@@ -0,0 +1,372 @@
+-- (C) 2022 Google, LLC
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with GNAT.Source_Info;
+with HW.Debug;
+with HW.GFX.GMA.Config;
+with HW.GFX.GMA.Registers;
+with HW.GFX.GMA.Connectors.TC;
+
+use type HW.Word64;
+
+package body HW.GFX.GMA.Power_And_Clocks.XELPD is
+
+ -- Comment lifted from i915:
+ -- XE_LPD Power Domains
+ --
+ -- Previous platforms required that PG(n-1) be enabled before PG(n). That
+ -- dependency chain turns into a dependency tree on XE_LPD:
+ --
+ -- PG0
+ -- |
+ -- --PG1--
+ -- / \
+ -- PGA --PG2--
+ -- / | \
+ -- PGB PGC PGD
+ --
+ -- Power wells must be enabled from top to bottom and disabled from bottom
+ -- to top. This allows pipes to be power gated independently.
+
+ type Power_Domain_Types is (Power_Well, Power_DDI, Power_AUX);
+ subtype PW_Domain is Power_Domain range PW1 .. PWD;
+ subtype DDI_Domain is Power_Domain range DDI_A .. DDI_USBC4;
+ subtype AUX_Domain is Power_Domain range AUX_A .. AUX_USBC4;
+ subtype AUX_USBC_Domain is Power_Domain range AUX_USBC1 .. AUX_USBC4;
+
+ function Power_Domain_Type (PD : Power_Domain) return Power_Domain_Types is
+ (if PD in PW_Domain then Power_Well
+ elsif PD in DDI_Domain then Power_DDI
+ else Power_AUX);
+
+ HIP_INDEX_REG : constant Registers.Registers_Index := Registers.HIP_INDEX_REG0;
+ function HIP_INDEX_VAL (A : AUX_USBC_Domain; Val : Word32) return Word32 is
+ (case A is
+ when AUX_USBC1 | AUX_USBC3 => Val,
+ when AUX_USBC2 | AUX_USBC4 => Shift_Left (Val, 8));
+
+ type DKL_Regs is array (AUX_USBC_Domain) of Registers.Registers_Index;
+ DKL_CMN_UC_DW_27 : constant DKL_Regs := DKL_Regs'
+ (AUX_USBC1 => Registers.DKL_CMN_UC_DW_27_1,
+ AUX_USBC2 => Registers.DKL_CMN_UC_DW_27_2,
+ AUX_USBC3 => Registers.DKL_CMN_UC_DW_27_3,
+ AUX_USBC4 => Registers.DKL_CMN_UC_DW_27_4);
+
+ type Power_Well_Regs is array (Power_Domain_Types) of Registers.Registers_Index;
+ PWR_CTL_BIOS : constant Power_Well_Regs :=
+ (Power_Well => Registers.PWR_WELL_CTL_BIOS,
+ Power_DDI => Registers.PWR_DDI_CTL_BIOS,
+ Power_AUX => Registers.PWR_AUX_CTL_BIOS);
+ PWR_CTL_DRIVER : constant Power_Well_Regs :=
+ (Power_Well => Registers.PWR_WELL_CTL_DRIVER,
+ Power_DDI => Registers.PWR_DDI_CTL_DRIVER,
+ Power_AUX => Registers.PWR_AUX_CTL_DRIVER);
+
+ FUSE_STATUS_PG0_DIST_STATUS : constant := 1 * 2 ** 27;
+ type Power_Well_Values is array (PW_Domain) of Word32;
+ FUSE_STATUS_PGx_DIST_STATUS : constant Power_Well_Values :=
+ (PW1 => 1 * 2 ** 26,
+ PW2 => 1 * 2 ** 25,
+ PWA => 1 * 2 ** 21,
+ PWB => 1 * 2 ** 20,
+ PWC => 1 * 2 ** 19,
+ PWD => 1 * 2 ** 18);
+
+ function Power_State_Mask (PD : Power_Domain) return Word32 is
+ begin
+ return
+ 2 ** (2 * (case PD is
+ when PW1 => 0,
+ when PW2 => 1,
+ when PWA => 5,
+ when PWB => 6,
+ when PWC => 7,
+ when PWD => 8,
+ when AUX_A => 0,
+ when AUX_B => 1,
+ when AUX_USBC1 => 5,
+ when AUX_USBC2 => 6,
+ when AUX_USBC3 => 7,
+ when AUX_USBC4 => 8,
+ when DDI_A => 0,
+ when DDI_B => 1,
+ when DDI_USBC1 => 5,
+ when DDI_USBC2 => 6,
+ when DDI_USBC3 => 7,
+ when DDI_USBC4 => 8));
+ end Power_State_Mask;
+
+ function Power_Request_Mask (PD : Power_Domain) return Word32 is
+ begin
+ return Shift_Left (Power_State_Mask (PD), 1);
+ end Power_Request_Mask;
+
+ type AUX_CTL_Array is array (AUX_USBC_Domain) of Registers.Registers_Index;
+ AUX_CTL_Regs : constant AUX_CTL_Array :=
+ AUX_CTL_Array'
+ (AUX_USBC1 => Registers.DDI_AUX_CTL_USBC1,
+ AUX_USBC2 => Registers.DDI_AUX_CTL_USBC2,
+ AUX_USBC3 => Registers.DDI_AUX_CTL_USBC3,
+ AUX_USBC4 => Registers.DDI_AUX_CTL_USBC4);
+
+ procedure Pre_On (PD : Power_Domain)
+ is
+ DP_AUX_CH_CTL_TBT_IO : constant := 1 * 2 ** 11;
+ begin
+ if PD in AUX_USBC_Domain then
+ Registers.Unset_Mask
+ (Register => AUX_CTL_Regs (PD),
+ Mask => DP_AUX_CH_CTL_TBT_IO);
+ elsif PD = PW1 then
+ Registers.Set_Mask
+ (Register => Registers.GEN8_CHICKEN_DCPR_1,
+ Mask => 1 * 2 ** 15); -- DISABLE_FLR_SRC
+ Registers.Wait_Set_Mask
+ (Register => Registers.FUSE_STATUS,
+ Mask => FUSE_STATUS_PG0_DIST_STATUS);
+ end if;
+ end Pre_On;
+
+ procedure Post_On (PD : Power_Domain)
+ is
+ DKL_CMN_UC_DW_27_UC_HEALTH : constant := 1 * 2 ** 15;
+ begin
+ if PD in PW_Domain then
+ Registers.Wait_Set_Mask (Registers.FUSE_STATUS,
+ FUSE_STATUS_PGx_DIST_STATUS (PD));
+ elsif PD in AUX_USBC_Domain then
+ Registers.Write (HIP_INDEX_REG, HIP_INDEX_VAL (PD, 2));
+ Registers.Wait_Set_Mask
+ (Register => DKL_CMN_UC_DW_27 (PD),
+ Mask => DKL_CMN_UC_DW_27_UC_HEALTH);
+ end if;
+ end Post_On;
+
+ function Aux_To_Port (PD : AUX_USBC_Domain) return USBC_Port
+ is (case PD is
+ when AUX_USBC1 => DDI_TC1,
+ when AUX_USBC2 => DDI_TC2,
+ when AUX_USBC3 => DDI_TC3,
+ when AUX_USBC4 => DDI_TC4);
+
+ procedure Pre_Off (PD : Power_Domain) is
+ begin
+ if PD in AUX_USBC_Domain then
+ Connectors.TC.Disconnect (Aux_To_Port (PD));
+ end if;
+ end Pre_Off;
+
+ procedure PD_On (PD : Power_Domain) is
+ PD_Type : constant Power_Domain_Types := Power_Domain_Type (PD);
+ Ctl1, Ctl2 : Word32;
+ Success : Boolean;
+ begin
+ Pre_On (PD);
+
+ Registers.Read (PWR_CTL_BIOS (PD_Type), Ctl1);
+ Registers.Read (PWR_CTL_DRIVER (PD_Type), Ctl2);
+
+ if ((Ctl1 or Ctl2) and Power_Request_Mask (PD)) = 0 then
+ Registers.Wait_Unset_Mask
+ (Register => PWR_CTL_DRIVER (PD_Type),
+ Mask => Power_State_Mask (PD));
+ end if;
+
+ if (Ctl2 and Power_Request_Mask (PD)) = 0 then
+ Registers.Set_Mask (PWR_CTL_DRIVER (PD_Type), Power_Request_Mask (PD));
+ Registers.Wait_Set_Mask
+ (Register => PWR_CTL_DRIVER (PD_Type),
+ Mask => Power_State_Mask (PD),
+ Success => Success);
+
+ if not Success then
+ if PD in AUX_USBC_Domain then
+ pragma Debug (Debug.Put_Line ("AUX timeout expected."));
+ else
+ Debug.Put_Line ("Failed to enable power domain!");
+ return;
+ end if;
+ end if;
+ end if;
+
+ Post_On (PD);
+ end PD_On;
+
+ procedure PD_Off (PD : Power_Domain)
+ is
+ PD_Type : constant Power_Domain_Types := Power_Domain_Type (PD);
+ Ctl1, Ctl2 : Word32;
+ begin
+ pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+ Registers.Read (PWR_CTL_BIOS (PD_Type), Ctl1);
+ Registers.Read (PWR_CTL_DRIVER (PD_Type), Ctl2);
+
+ -- PW1 is "always-on"
+ if PD = PW1 then
+ return;
+ end if;
+
+ if ((Ctl1 or Ctl2) and Power_Request_Mask (PD)) /= 0 then
+ Registers.Wait_Set_Mask
+ (Register => PWR_CTL_DRIVER (PD_Type),
+ Mask => Power_State_Mask (PD));
+ end if;
+
+ Pre_Off (PD);
+
+ if (Ctl2 and Power_Request_Mask (PD)) /= 0 then
+ Registers.Unset_Mask (PWR_CTL_DRIVER (PD_Type), Power_Request_Mask (PD));
+ Registers.Unset_Mask (PWR_CTL_BIOS (PD_Type), Power_Request_Mask (PD));
+ end if;
+ end PD_Off;
+
+ function Need_PD (PD : Power_Domain; Configs : Pipe_Configs) return Boolean
+ is
+ function Any_Port_Is (Port : Active_Port_Type) return Boolean is
+ (Configs (Primary).Port = Port or Configs (Secondary).Port = Port or
+ Configs (Tertiary).Port = Port);
+
+ type Port_Array is array (natural range <>) of Active_Port_Type;
+ function Any_Port_In (Ports : Port_Array) return Boolean is
+ begin
+ for P of Ports loop
+ if (Configs (Primary).Port = P) or
+ (Configs (Secondary).Port = P) or
+ (Configs (Tertiary).Port = P)
+ then
+ return True;
+ end if;
+ end loop;
+ return False;
+ end Any_Port_In;
+
+ DDI_UBSC : constant Port_Array :=
+ Port_Array'
+ (USBC1_DP, USBC2_DP, USBC3_DP, USBC4_DP,
+ USBC1_HDMI, USBC2_HDMI, USBC3_HDMI, USBC4_HDMI);
+
+ function Num_Active_Pipes return Natural is
+ Count : Natural := 0;
+ begin
+ for I in Pipe_Index loop
+ if Configs (I).Port /= Disabled then
+ Count := Count + 1;
+ end if;
+ end loop;
+ return Count;
+ end Num_Active_Pipes;
+ begin
+ case PD is
+ when PW1 =>
+ return True;
+ when PW2 =>
+ return Any_Port_In (DDI_UBSC);
+ when PWA =>
+ return Num_Active_Pipes >= 1;
+ when PWB =>
+ return Num_Active_Pipes >= 2;
+ when PWC =>
+ return Num_Active_Pipes >= 3;
+ when PWD =>
+ return Num_Active_Pipes >= 4;
+ when DDI_A | AUX_A =>
+ return Any_Port_Is (DP1) or else Any_Port_Is (HDMI1) or else
+ Any_Port_Is (eDP);
+ when DDI_B | AUX_B =>
+ return Any_Port_Is (DP2) or else Any_Port_Is (HDMI2);
+ when DDI_USBC1 | AUX_USBC1 =>
+ return Any_Port_Is (USBC1_DP) or Any_Port_Is (USBC1_HDMI);
+ when DDI_USBC2 | AUX_USBC2 =>
+ return Any_Port_Is (USBC2_DP) or Any_Port_Is (USBC2_HDMI);
+ when DDI_USBC3 | AUX_USBC3 =>
+ return Any_Port_Is (USBC3_DP) or Any_Port_Is (USBC3_HDMI);
+ when DDI_USBC4 | AUX_USBC4 =>
+ return Any_Port_Is (USBC4_DP) or Any_Port_Is (USBC4_HDMI);
+ end case;
+ end Need_PD;
+
+ procedure Aux_Off is
+ begin
+ for AUX in reverse AUX_USBC1 .. AUX_USBC4 loop
+ PD_Off (AUX);
+ end loop;
+ PD_Off (AUX_B);
+ PD_Off (AUX_A);
+ end Aux_off;
+
+ procedure Init_Power is
+ begin
+ PD_On (PW1);
+ end Init_Power;
+
+ procedure Power_Set_To (Configs : Pipe_Configs) is
+ begin
+ for PD in reverse Power_Domain loop
+ if not Need_PD (PD, Configs) then
+ PD_Off (PD);
+ end if;
+ end loop;
+
+ for PD in Power_Domain loop
+ if Need_PD (PD, Configs) then
+ PD_On (PD);
+ end if;
+ end loop;
+ end Power_Set_To;
+
+ procedure Power_Up (Old_Configs, New_Configs : Pipe_Configs) is
+ begin
+ pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+ for PD in Power_Domain loop
+ if not Need_PD (PD, Old_Configs) and Need_PD (PD, New_Configs) then
+ PD_On (PD);
+ end if;
+ end loop;
+ end Power_Up;
+
+ procedure Power_Down (Old_Configs, Tmp_Configs, New_Configs : Pipe_Configs)
+ is
+ begin
+ for PD in reverse Power_Domain loop
+ if (Need_PD (PD, Old_Configs) or Need_PD (PD, Tmp_Configs)) and
+ not Need_PD (PD, New_Configs)
+ then
+ PD_Off (PD);
+ end if;
+ end loop;
+ end Power_Down;
+
+ procedure All_Off is
+ begin
+ for AUX in reverse AUX_A .. AUX_USBC4 loop
+ PD_Off (AUX);
+ end loop;
+
+ for DDI in reverse DDI_A .. DDI_USBC4 loop
+ PD_Off (DDI);
+ end loop;
+
+ for PW in reverse PW1 .. PWD loop
+ PD_Off (PW);
+ end loop;
+ end All_Off;
+
+ procedure Power_Up_Aux is
+ begin
+ for Aux in AUX_Domain loop
+ PD_On (Aux);
+ end loop;
+ end Power_Up_Aux;
+
+end HW.GFX.GMA.Power_And_Clocks.XELPD;
diff --git a/common/tigerlake/hw-gfx-gma-power_and_clocks-xelpd.ads b/common/tigerlake/hw-gfx-gma-power_and_clocks-xelpd.ads
new file mode 100644
index 0000000..9bbd397
--- /dev/null
+++ b/common/tigerlake/hw-gfx-gma-power_and_clocks-xelpd.ads
@@ -0,0 +1,30 @@
+-- (C) 2022 Google, LLC
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+private package HW.GFX.GMA.Power_And_Clocks.XELPD is
+
+ type Power_Domain is
+ (PW1, PWA, PW2, PWB, PWC, PWD,
+ AUX_A, AUX_B, AUX_USBC1, AUX_USBC2, AUX_USBC3, AUX_USBC4,
+ DDI_A, DDI_B, DDI_USBC1, DDI_USBC2, DDI_USBC3, DDI_USBC4);
+
+ procedure Power_Set_To (Configs : Pipe_Configs);
+ procedure Power_Up (Old_Configs, New_Configs : Pipe_Configs);
+ procedure Power_Down (Old_Configs, Tmp_Configs, New_Configs : Pipe_Configs);
+ procedure All_Off;
+ function Need_PD (PD : Power_Domain; Configs : Pipe_Configs) return Boolean;
+ procedure Init_Power;
+ procedure Aux_Off;
+ procedure Power_Up_Aux;
+
+end HW.GFX.GMA.Power_And_Clocks.XELPD;
diff --git a/common/tigerlake/hw-gfx-gma-power_and_clocks.adb b/common/tigerlake/hw-gfx-gma-power_and_clocks.adb
index 099376a..68636f7 100644
--- a/common/tigerlake/hw-gfx-gma-power_and_clocks.adb
+++ b/common/tigerlake/hw-gfx-gma-power_and_clocks.adb
@@ -19,25 +19,15 @@
with HW.GFX.GMA.PCode;
with HW.GFX.GMA.Registers;
with HW.GFX.GMA.Transcoder;
-with HW.GFX.GMA.Connectors;
with HW.GFX.GMA.Connectors.TC;
+with HW.GFX.GMA.Power_And_Clocks.TGL;
+with HW.GFX.GMA.Power_And_Clocks.XELPD;
use type HW.Word64;
package body HW.GFX.GMA.Power_And_Clocks is
- type Power_Domain is
- (PW1, PW2, PW3, PW4, PW5,
- AUX_A, AUX_B, AUX_C,
- AUX_USBC1, AUX_USBC2, AUX_USBC3, AUX_USBC4, AUX_USBC5, AUX_USBC6,
- DDI_A, DDI_B, DDI_C,
- DDI_USBC1, DDI_USBC2, DDI_USBC3, DDI_USBC4, DDI_USBC5, DDI_USBC6);
- type Power_Domain_Types is (Power_Well, Power_DDI, Power_AUX);
- subtype PW_Domain is Power_Domain range PW1 .. PW5;
- subtype DDI_Domain is Power_Domain range DDI_A .. DDI_USBC6;
- subtype AUX_Domain is Power_Domain range AUX_A .. AUX_USBC6;
- subtype AUX_USBC_Domain is Power_Domain range AUX_USBC1 .. AUX_USBC6;
-
+ DARBF_GATING_DIS : constant := 1 * 2 ** 27;
PCH_DPMGUNIT_CLOCK_GATE_DISABLE : constant := 1 * 2 ** 15;
NDE_RSTWRN_OPT_RST_PCH_Handshake_En : constant := 1 * 2 ** 4;
@@ -46,8 +36,25 @@
DBUF_CTL_DBUF_POWER_REQUEST : constant := 1 * 2 ** 31;
DBUF_CTL_TRACKER_STATE_SERVICE_MASK : constant := 16#f8_0000#;
DBUF_CTL_TRACKER_STATE_SERVICE_SHIFT : constant := 19;
+ DBUF_CTL_MIN_TRACKER_STATE_SERVICE_SHIFT : constant := 16;
+ DBUF_CTL_MIN_TRACKER_STATE_SERVICE_MASK : constant := 16#7_0000#;
DBUF_CTL_DBUF_POWER_STATE : constant := 1 * 2 ** 30;
+ type DBUF_Regs_Array is array (natural range 0 .. 3) of Registers.Registers_Index;
+ DBUF_Regs : constant DBUF_Regs_Array :=
+ DBUF_Regs_Array'
+ (Registers.DBUF_CTL_S0,
+ Registers.DBUF_CTL_S1,
+ Registers.DBUF_CTL_S2,
+ Registers.DBUF_CTL_S3);
+
+ MBUS_JOIN : constant := 1 * 2 ** 31;
+ MBUS_HASHING_MODE_MASK : constant := 1 * 2 ** 30;
+ MBUS_HASHING_MODE_2x2 : constant := 0 * 2 ** 30;
+ MBUS_HASHING_MODE_1x4 : constant := 1 * 2 ** 30;
+ MBUS_JOIN_PIPE_SELECT_MASK : constant := 16#1c00_0000#;
+ MBUS_JOIN_PIPE_SELECT_NONE : constant := 16#1c00_0000#;
+
----------------------------------------------------------------------------
MBUS_ABOX_CTL_BW_CREDITS_MASK : constant := 16#3# * 2 ** 20;
@@ -78,88 +85,10 @@
----------------------------------------------------------------------------
- DCPR_MASK_MAXLATENCY_MEMUP_CLR : constant := 1 * 2 ** 27;
- DCPR_MASK_LPMODE : constant := 1 * 2 ** 26;
- DCPR_SEND_RESP_IMM : constant := 1 * 2 ** 25;
- DCPR_CLEAR_MEMSTAT_DIS : constant := 1 * 2 ** 24;
-
- ----------------------------------------------------------------------------
-
- function HIP_INDEX_REG (A : AUX_USBC_Domain) return Registers.Registers_Index
- is (if A <= AUX_USBC4
- then Registers.HIP_INDEX_REG0
- else Registers.HIP_INDEX_REG1);
-
- function HIP_INDEX_VAL (A : AUX_USBC_Domain; Val : Word32) return Word32 is
- (case A is
- when AUX_USBC1 | AUX_USBC3 | AUX_USBC5 => Val * 2 ** 0,
- when AUX_USBC2 | AUX_USBC4 | AUX_USBC6 => Val * 2 ** 8);
-
- type DKL_Regs is array (AUX_USBC_Domain) of Registers.Registers_Index;
- DKL_CMN_UC_DW_27 : constant DKL_Regs := DKL_Regs'
- (AUX_USBC1 => Registers.DKL_CMN_UC_DW_27_1,
- AUX_USBC2 => Registers.DKL_CMN_UC_DW_27_2,
- AUX_USBC3 => Registers.DKL_CMN_UC_DW_27_3,
- AUX_USBC4 => Registers.DKL_CMN_UC_DW_27_4,
- AUX_USBC5 => Registers.DKL_CMN_UC_DW_27_5,
- AUX_USBC6 => Registers.DKL_CMN_UC_DW_27_6);
-
- ----------------------------------------------------------------------------
-
- function Power_Domain_Type (PD : Power_Domain) return Power_Domain_Types is
- (if PD in PW_Domain then Power_Well
- elsif PD in DDI_Domain then Power_DDI
- else Power_AUX);
-
- type Power_Well_Regs is array (Power_Domain_Types) of Registers.Registers_Index;
- PWR_CTL_BIOS : constant Power_Well_Regs :=
- (Power_Well => Registers.PWR_WELL_CTL_BIOS,
- Power_DDI => Registers.PWR_DDI_CTL_BIOS,
- Power_AUX => Registers.PWR_AUX_CTL_BIOS);
- PWR_CTL_DRIVER : constant Power_Well_Regs :=
- (Power_Well => Registers.PWR_WELL_CTL_DRIVER,
- Power_DDI => Registers.PWR_DDI_CTL_DRIVER,
- Power_AUX => Registers.PWR_AUX_CTL_DRIVER);
-
- function PW_Index (PW : PW_Domain) return Natural
- is
- (Power_Domain'Pos (PW) - Power_Domain'Pos (PW1));
-
- function DDI_Index (DDI : DDI_Domain) return Natural
- is
- (Power_Domain'Pos (DDI) - Power_Domain'Pos (DDI_A));
-
- function AUX_Index (AUX : AUX_Domain) return Natural
- is
- (Power_Domain'Pos (AUX) - Power_Domain'Pos (AUX_A));
-
- function PW_Request_Mask (PW : PW_Domain) return Word32 is
- (2 * 2 ** (2 * PW_Index (PW)));
- function PW_State_Mask (PW : PW_Domain) return Word32 is
- (1 * 2 ** (2 * PW_Index (PW)));
-
- function DDI_Request_Mask (DDI : DDI_Domain) return Word32 is
- (2 * 2 ** (2 * DDI_Index (DDI)));
- function DDI_State_Mask (DDI : DDI_Domain) return Word32 is
- (1 * 2 ** (2 * DDI_Index (DDI)));
-
- function AUX_Request_Mask (AUX : AUX_Domain) return Word32 is
- (2 * 2 ** (2 * AUX_Index (AUX)));
- function AUX_State_Mask (AUX : AUX_Domain) return Word32 is
- (1 * 2 ** (2 * AUX_Index (AUX)));
-
- ----------------------------------------------------------------------------
-
- FUSE_STATUS_PG0_DIST_STATUS : constant := 1 * 2 ** 27;
- type Power_Well_Values is array (PW_Domain) of Word32;
- FUSE_STATUS_PGx_DIST_STATUS : constant Power_Well_Values :=
- (PW1 => 1 * 2 ** 26,
- PW2 => 1 * 2 ** 25,
- PW3 => 1 * 2 ** 24,
- PW4 => 1 * 2 ** 23,
- PW5 => 1 * 2 ** 22);
-
- ----------------------------------------------------------------------------
+ DCPR_MASK_MAXLATENCY_MEMUP_CLR : constant := 1 * 2 ** 27;
+ DCPR_MASK_LPMODE : constant := 1 * 2 ** 26;
+ DCPR_SEND_RESP_IMM : constant := 1 * 2 ** 25;
+ DCPR_CLEAR_MEMSTAT_DIS : constant := 1 * 2 ** 24;
TGL_PCODE_MEM_SUBSYSTEM_INFO : constant := 16#d#;
TGL_PCODE_MEM_SS_READ_GLOBAL_INFO : constant := 0 * 2 ** 8;
@@ -167,222 +96,21 @@
TGL_CDCLK_PREPARE_FOR_CHANGE : constant := 3;
TGL_CDCLK_READY_FOR_CHANGE : constant := 1;
- ----------------------------------------------------------------------------
-
CDCLK_PLL_ENABLE_PLL_RATIO_MASK : constant := 16#ff#;
CDCLK_PLL_ENABLE_PLL_ENABLE : constant := 1 * 2 ** 31;
CDCLK_PLL_ENABLE_PLL_LOCK : constant := 1 * 2 ** 30;
CDCLK_CD2X_DIV_SEL_MASK : constant := 3 * 2 ** 22;
CDCLK_CD2X_DIV_SEL_1 : constant := 0 * 2 ** 22;
+ CDCLK_CD2X_DIV_SEL_1_5 : constant := 1 * 2 ** 22;
CDCLK_CD2X_DIV_SEL_2 : constant := 2 * 2 ** 22;
+ CDCLK_CD2X_DIV_SEL_4 : constant := 3 * 2 ** 22;
CDCLK_CD2X_PIPE_NONE : constant := 7 * 2 ** 19;
CDCLK_CTL_CD_FREQ_DECIMAL_MASK : constant := 16#7ff#;
+ CDCLK_PLL_ENABLE_FREQ_REQ_ACK : constant := 1 * 2 ** 22;
+ CDCLK_PLL_ENABLE_FREQ_REQ : constant := 1 * 2 ** 23;
----------------------------------------------------------------------------
- function Power_Request_Mask (PD : Power_Domain) return Word32 is
- begin
- if PD in PW_Domain then
- return PW_Request_Mask (PD);
- elsif PD in DDI_Domain then
- return DDI_Request_Mask (PD);
- else
- return AUX_Request_Mask (PD);
- end if;
- end Power_Request_Mask;
-
- function Power_State_Mask (PD : Power_Domain) return Word32 is
- begin
- if PD in PW_Domain then
- return PW_State_Mask (PD);
- elsif PD in DDI_Domain then
- return DDI_State_Mask (PD);
- else
- return AUX_State_Mask (PD);
- end if;
- end Power_State_Mask;
-
- type AUX_CTL_Array is array (AUX_USBC_Domain) of Registers.Registers_Index;
- AUX_CTL_Regs : constant AUX_CTL_Array :=
- AUX_CTL_Array'
- (AUX_USBC1 => Registers.DDI_AUX_CTL_USBC1,
- AUX_USBC2 => Registers.DDI_AUX_CTL_USBC2,
- AUX_USBC3 => Registers.DDI_AUX_CTL_USBC3,
- AUX_USBC4 => Registers.DDI_AUX_CTL_USBC4,
- AUX_USBC5 => Registers.DDI_AUX_CTL_USBC5,
- AUX_USBC6 => Registers.DDI_AUX_CTL_USBC6);
-
- function Aux_To_Port (PD : AUX_USBC_Domain) return USBC_Port
- is (case PD is
- when AUX_USBC1 => DDI_TC1,
- when AUX_USBC2 => DDI_TC2,
- when AUX_USBC3 => DDI_TC3,
- when AUX_USBC4 => DDI_TC4,
- when AUX_USBC5 => DDI_TC5,
- when AUX_USBC6 => DDI_TC6);
-
- procedure Pre_On (PD : Power_Domain)
- is
- DP_AUX_CH_CTL_TBT_IO : constant := 1 * 2 ** 11;
- Success : Boolean;
- begin
- if PD in AUX_USBC_Domain then
- -- Disable TBT IO mode for AUX
- Registers.Unset_Mask
- (Register => AUX_CTL_Regs (PD),
- Mask => DP_AUX_CH_CTL_TBT_IO);
-
- Connectors.TC.Connect (Aux_To_Port (PD), Success);
- if not Success then
- Debug.Put_Line ("Connection flow failed!");
- end if;
- end if;
- end Pre_On;
-
- procedure Pre_Off (PD : Power_Domain) is
- begin
- if PD in AUX_USBC_Domain then
- Connectors.TC.Disconnect (Aux_To_Port (PD));
- end if;
- end Pre_Off;
-
- procedure Post_On (PD : Power_Domain)
- is
- DKL_CMN_UC_DW_27_UC_HEALTH : constant := 1 * 2 ** 15;
- begin
- if PD in PW_Domain then
- Registers.Wait_Set_Mask (Registers.FUSE_STATUS,
- FUSE_STATUS_PGx_DIST_STATUS (PD));
- elsif PD in AUX_USBC_Domain then
- Registers.Write (HIP_INDEX_REG (PD), HIP_INDEX_VAL (PD, 2));
- Registers.Wait_Set_Mask
- (Register => DKL_CMN_UC_DW_27 (PD),
- Mask => DKL_CMN_UC_DW_27_UC_HEALTH);
- end if;
- end Post_On;
-
- procedure PD_On (PD : Power_Domain)
- is
- Ctl1, Ctl2 : Word32;
- PD_Type : constant Power_Domain_Types := Power_Domain_Type (PD);
- Success : Boolean;
- begin
- Pre_On (PD);
-
- Registers.Read (PWR_CTL_BIOS (PD_Type), Ctl1);
- Registers.Read (PWR_CTL_DRIVER (PD_Type), Ctl2);
-
- if ((Ctl1 or Ctl2) and Power_Request_Mask (PD)) = 0 then
- Registers.Wait_Unset_Mask
- (Register => PWR_CTL_DRIVER (PD_Type),
- Mask => Power_State_Mask (PD));
- end if;
-
- if (Ctl2 and Power_Request_Mask (PD)) = 0 then
- Registers.Set_Mask (PWR_CTL_DRIVER (PD_Type), Power_Request_Mask (PD));
- Registers.Wait_Set_Mask
- (Register => PWR_CTL_DRIVER (PD_Type),
- Mask => Power_State_Mask (PD),
- Success => Success);
-
- if not Success then
- Debug.Put_Line ("Failed to enable power domain!");
- return;
- end if;
- end if;
-
- Post_On (PD);
- end PD_On;
-
- procedure PD_Off (PD : Power_Domain)
- is
- Ctl1, Ctl2 : Word32;
- PD_Type : constant Power_Domain_Types := Power_Domain_Type (PD);
- begin
- pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
- Registers.Read (PWR_CTL_BIOS (PD_Type), Ctl1);
- Registers.Read (PWR_CTL_DRIVER (PD_Type), Ctl2);
-
- if ((Ctl1 or Ctl2) and Power_Request_Mask (PD)) /= 0 then
- Registers.Wait_Set_Mask
- (Register => PWR_CTL_DRIVER (PD_Type),
- Mask => Power_State_Mask (PD));
- end if;
-
- if (Ctl2 and Power_Request_Mask (PD)) /= 0 then
- Registers.Unset_Mask (PWR_CTL_DRIVER (PD_Type), Power_Request_Mask (PD));
- Registers.Unset_Mask (PWR_CTL_BIOS (PD_Type), Power_Request_Mask (PD));
- end if;
- end PD_Off;
-
- type Port_Array is array (natural range <>) of Active_Port_Type;
- Conventional_Ports : constant Port_Array :=
- (DP1, DP2, DP3, HDMI1, HDMI2, HDMI3);
- TC_Ports : constant Port_Array :=
- (USBC1_DP, USBC2_DP, USBC3_DP, USBC4_DP, USBC5_DP, USBC6_DP,
- USBC1_HDMI, USBC1_HDMI, USBC1_HDMI, USBC1_HDMI, USBC1_HDMI,
- USBC1_HDMI);
-
- function Need_PD (PD : Power_Domain; Configs : Pipe_Configs) return Boolean
- is
- function Any_Port_Is (Port : Active_Port_Type) return Boolean is
- (Configs (Primary).Port = Port or Configs (Secondary).Port = Port or
- Configs (Tertiary).Port = Port);
-
- function Any_Port_In (Ports : Port_Array) return Boolean is
- begin
- for P of Ports loop
- if (Configs (Primary).Port = P) or
- (Configs (Secondary).Port = P) or
- (Configs (Tertiary).Port = P)
- then
- return True;
- end if;
- end loop;
- return False;
- end Any_Port_In;
-
- function Num_Active_Pipes return Natural is
- Count : Natural := 0;
- begin
- for I in Pipe_Index loop
- if Configs (I).Port /= Disabled then
- Count := Count + 1;
- end if;
- end loop;
- return Count;
- end Num_Active_Pipes;
- begin
- case PD is
- when PW1 | PW2 =>
- return Configs (Primary).Port /= Disabled or Any_Port_In (Conventional_Ports);
- when PW3 =>
- return Configs (Secondary).Port /= Disabled or Any_Port_In (TC_Ports);
- when PW4 =>
- return Configs (Tertiary).Port /= Disabled;
- when PW5 =>
- return False;
- when DDI_A | AUX_A =>
- return Any_Port_Is (DP1) or Any_Port_Is (HDMI1) or Any_Port_Is (eDP);
- when DDI_B | AUX_B =>
- return Any_Port_Is (DP2) or Any_Port_Is (HDMI2);
- when DDI_C | AUX_C =>
- return Any_Port_Is (DP3) or Any_Port_Is (HDMI3);
- when DDI_USBC1 | AUX_USBC1 =>
- return Any_Port_Is (USBC1_DP) or Any_Port_Is (USBC1_HDMI);
- when DDI_USBC2 | AUX_USBC2 =>
- return Any_Port_Is (USBC2_DP) or Any_Port_Is (USBC2_HDMI);
- when DDI_USBC3 | AUX_USBC3 =>
- return Any_Port_Is (USBC3_DP) or Any_Port_Is (USBC3_HDMI);
- when DDI_USBC4 | AUX_USBC4 =>
- return Any_Port_Is (USBC4_DP) or Any_Port_Is (USBC4_HDMI);
- when DDI_USBC5 | AUX_USBC5 =>
- return Any_Port_Is (USBC5_DP) or Any_Port_Is (USBC5_HDMI);
- when DDI_USBC6 | AUX_USBC6 =>
- return Any_Port_Is (USBC6_DP) or Any_Port_Is (USBC6_HDMI);
- end case;
- end Need_PD;
-
procedure Get_RefClk (Refclk : out Refclk_Range)
is
DSSM : Word32;
@@ -434,22 +162,45 @@
Refclk_Freq : Frequency_Type;
begin
Get_Refclk (Refclk_Freq);
- Normalized :=
- (case Refclk_Freq is
- when 19_200_000 | 38_400_000 =>
- (if CDClk <= 172_800_000 then 172_800_000
- elsif CDClk <= 192_000_000 then 192_000_000
- elsif CDClk <= 307_200_000 then 307_200_000
- elsif CDClk <= 326_400_000 then 326_400_000
- elsif CDClk <= 556_800_000 then 556_800_000
- else 652_800_000),
- when others =>
- (if CDClk <= 180_000_000 then 180_000_000
- elsif CDClk <= 192_000_000 then 192_000_000
- elsif CDClk <= 312_000_000 then 312_000_000
- elsif CDClk <= 324_000_000 then 324_000_000
- elsif CDClk <= 552_000_000 then 552_000_000
- else 648_000_000));
+ if Config.Has_CDClk_PLL_Crawl then
+ Normalized :=
+ (case Refclk_Freq is
+ when 19_200_000 =>
+ (if CDClk <= 172_800_000 then 172_800_000
+ elsif CDClk <= 192_000_000 then 192_000_000
+ elsif CDClk <= 307_200_000 then 307_200_000
+ elsif CDClk <= 556_800_000 then 556_800_000
+ else 652_800_000),
+ when 24_000_000 =>
+ (if CDClk <= 176_000_000 then 176_000_000
+ elsif CDClk <= 192_000_000 then 192_000_000
+ elsif CDClk <= 312_000_000 then 307_200_000
+ elsif CDClk <= 552_000_000 then 552_000_000
+ else 648_000_000),
+ when others => -- 38_400_000
+ (if CDClk <= 179_200_000 then 179_200_000
+ elsif CDClk <= 192_000_000 then 192_000_000
+ elsif CDClk <= 307_200_000 then 307_200_000
+ elsif CDClk <= 556_800_000 then 556_800_000
+ else 652_800_000));
+ else
+ Normalized :=
+ (case Refclk_Freq is
+ when 19_200_000 | 38_400_000 =>
+ (if CDClk <= 172_800_000 then 172_800_000
+ elsif CDClk <= 192_000_000 then 192_000_000
+ elsif CDClk <= 307_200_000 then 307_200_000
+ elsif CDClk <= 326_400_000 then 326_400_000
+ elsif CDClk <= 556_800_000 then 556_800_000
+ else 652_800_000),
+ when others =>
+ (if CDClk <= 180_000_000 then 180_000_000
+ elsif CDClk <= 192_000_000 then 192_000_000
+ elsif CDClk <= 312_000_000 then 312_000_000
+ elsif CDClk <= 324_000_000 then 324_000_000
+ elsif CDClk <= 552_000_000 then 552_000_000
+ else 648_000_000));
+ end if;
end Normalize_CDClk;
procedure Get_Cur_CDClk (CDClk : out Config.CDClk_Range)
@@ -466,28 +217,76 @@
procedure Set_CDClk (CDClk_In : Frequency_Type)
is
subtype PLL_Ratio_Range is natural range 0 .. 68;
- function Ratio_For_19_2_MHz (CDCLk : Frequency_Type) return PLL_Ratio_Range is
+ function Ratio_For_19_2_MHz (CDClk : Frequency_Type) return PLL_Ratio_Range is
begin
- case CDClk is
- when 172_800_000 => return 18;
- when 192_000_000 => return 20;
- when 307_200_000 => return 32;
- when 326_400_000 | 652_800_000 => return 68;
- when 556_800_000 => return 58;
- when others => return 0;
- end case;
+ if Config.Has_CDClk_PLL_Crawl then
+ case CDClk is
+ when 172_800_000 => return 27;
+ when 192_000_000 => return 20;
+ when 307_200_000 => return 32;
+ when 556_800_000 => return 58;
+ when 652_800_000 => return 68;
+ when others => return 0;
+ end case;
+ else
+ case CDClk is
+ when 172_800_000 => return 18;
+ when 192_000_000 => return 20;
+ when 307_200_000 => return 32;
+ when 326_400_000
+ | 652_800_000 => return 68;
+ when 556_800_000 => return 58;
+ when others => return 0;
+ end case;
+ end if;
end Ratio_For_19_2_MHz;
- function Ratio_For_24_MHz (CDCLk : Frequency_Type) return PLL_Ratio_Range is
+ function Ratio_For_38_4_MHz (CDClk : Frequency_Type) return PLL_Ratio_Range is
begin
- case CDClk is
- when 180_800_000 => return 15;
- when 192_000_000 => return 16;
- when 312_000_000 => return 26;
- when 324_000_000 | 648_000_000 => return 54;
- when 552_000_000 => return 46;
- when others => return 0;
- end case;
+ if Config.Has_CDClk_PLL_Crawl then
+ case CDClk is
+ when 179_200_000 => return 14;
+ when 192_000_000 => return 10;
+ when 307_200_000 => return 16;
+ when 556_800_000 => return 29;
+ when 652_800_000 => return 34;
+ when others => return 0;
+ end case;
+ else
+ case CDClk is
+ when 172_800_000 => return 9;
+ when 192_000_000 => return 10;
+ when 307_200_000 => return 16;
+ when 326_400_000
+ | 652_800_000 => return 34;
+ when 556_800_000 => return 29;
+ when others => return 0;
+ end case;
+ end if;
+ end Ratio_For_38_4_MHz;
+
+ function Ratio_For_24_MHz (CDClk : Frequency_Type) return PLL_Ratio_Range is
+ begin
+ if Config.Has_CDClk_PLL_Crawl then
+ case CDClk is
+ when 176_000_000 => return 22;
+ when 192_000_000 => return 16;
+ when 312_000_000 => return 26;
+ when 552_000_000 => return 46;
+ when 648_000_000 => return 54;
+ when others => return 0;
+ end case;
+ else
+ case CDClk is
+ when 180_800_000 => return 15;
+ when 192_000_000 => return 16;
+ when 312_000_000 => return 26;
+ when 324_000_000
+ | 648_000_000 => return 54;
+ when 552_000_000 => return 46;
+ when others => return 0;
+ end case;
+ end if;
end Ratio_For_24_MHz;
function CDCLK_CTL_CD_FREQ_DECIMAL (Freq : Frequency_Type) return Word32 with
@@ -511,7 +310,7 @@
Get_Refclk (Refclk_Freq);
case Refclk_Freq is
when 19_200_000 => PLL_Ratio := Ratio_For_19_2_MHz (CDClk);
- when 38_400_000 => PLL_Ratio := Ratio_For_19_2_MHz (CDClk) / 2;
+ when 38_400_000 => PLL_Ratio := Ratio_For_38_4_MHz (CDClk);
when 24_000_000 => PLL_Ratio := Ratio_For_24_MHz (CDClk);
when others => PLL_Ratio := 0;
end case;
@@ -535,23 +334,44 @@
return;
end if;
- Registers.Unset_Mask
- (Register => Registers.CDCLK_PLL_ENABLE,
- Mask => CDCLK_PLL_ENABLE_PLL_ENABLE);
- Registers.Wait_Unset_Mask
- (Register => Registers.CDCLK_PLL_ENABLE,
- Mask => CDCLK_PLL_ENABLE_PLL_LOCK);
+ if Config.Has_CDClk_PLL_Crawl then
+ Registers.Write
+ (Register => Registers.CDCLK_PLL_ENABLE,
+ Value => Word32(PLL_Ratio) or
+ CDCLK_PLL_ENABLE_PLL_ENABLE);
+ Registers.Write
+ (Register => Registers.CDCLK_PLL_ENABLE,
+ Value => Word32(PLL_Ratio) or
+ CDCLK_PLL_ENABLE_PLL_ENABLE or
+ CDCLK_PLL_ENABLE_FREQ_REQ);
- Registers.Write
- (Register => Registers.CDCLK_PLL_ENABLE,
- Value => Word32(PLL_Ratio));
- Registers.Write
- (Register => Registers.CDCLK_PLL_ENABLE,
- Value => Word32(PLL_Ratio) or CDCLK_PLL_ENABLE_PLL_ENABLE);
- Registers.Wait_Set_Mask
- (Register => Registers.CDCLK_PLL_ENABLE,
- Mask => CDCLK_PLL_ENABLE_PLL_LOCK,
- Success => Success);
+ Registers.Wait_Set_Mask
+ (Register => Registers.CDCLK_PLL_ENABLE,
+ Mask => CDCLK_PLL_ENABLE_PLL_LOCK or
+ CDCLK_PLL_ENABLE_FREQ_REQ_ACK);
+ Registers.Write
+ (Register => Registers.CDCLK_PLL_ENABLE,
+ Value => Word32(PLL_Ratio) or
+ CDCLK_PLL_ENABLE_PLL_ENABLE);
+ else
+ Registers.Unset_Mask
+ (Register => Registers.CDCLK_PLL_ENABLE,
+ Mask => CDCLK_PLL_ENABLE_PLL_ENABLE);
+ Registers.Wait_Unset_Mask
+ (Register => Registers.CDCLK_PLL_ENABLE,
+ Mask => CDCLK_PLL_ENABLE_PLL_LOCK);
+
+ Registers.Write
+ (Register => Registers.CDCLK_PLL_ENABLE,
+ Value => Word32(PLL_Ratio));
+ Registers.Write
+ (Register => Registers.CDCLK_PLL_ENABLE,
+ Value => Word32(PLL_Ratio) or CDCLK_PLL_ENABLE_PLL_ENABLE);
+ Registers.Wait_Set_Mask
+ (Register => Registers.CDCLK_PLL_ENABLE,
+ Mask => CDCLK_PLL_ENABLE_PLL_LOCK,
+ Success => Success);
+ end if;
if not Success then
Debug.Put_Line ("CDClk PLL failed to lock!");
@@ -562,7 +382,9 @@
CD2X :=
(case (Div_Round_Closest (VCO, CDClk / 1_000)) is
when 2 => CDCLK_CD2X_DIV_SEL_1,
+ when 3 => CDCLK_CD2X_DIV_SEL_1_5,
when 4 => CDCLK_CD2X_DIV_SEL_2,
+ when 8 => CDCLK_CD2X_DIV_SEL_4,
when others => CDCLK_CD2X_DIV_SEL_1);
Registers.Write
@@ -607,18 +429,11 @@
BW_BUDDY_MASK : Word32;
end record;
type Bw_Buddy_Info_Array is array (Natural range 0 .. 3) of Bw_Buddy_Info;
- Buddy_Info_Wa : constant Bw_Buddy_Info_Array :=
- -- wa_1409767108_buddy_page_masks
- ((1, DDR4, 1),
- (1, LPDDR4, 1),
- (2, DDR4, 3),
- (2, LPDDR4, 3));
Buddy_Info : constant Bw_Buddy_Info_Array :=
- -- tgl_buddy_page_masks
((1, DDR4, 16#f#),
(2, LPDDR4, 16#1c#),
(2, DDR4, 16#1f#),
- (4, LPDDR4, 16#1c#));
+ (4, LPDDR4, 16#38#));
Result : Word64;
Module_Type: DRAM_Module_Type;
Channels : Natural;
@@ -658,7 +473,6 @@
(Register => Registers.BW_BUDDY2_PAGE_MASK,
Mask => Buddy_Info (I).BW_BUDDY_MASK);
- -- Wa_22010178259:tgl,rkl
Registers.Unset_And_Set_Mask
(Register => Registers.BW_BUDDY1_CTL,
Mask_Unset => BW_BUDDY_TLB_REQ_TIMER_MASK,
@@ -698,11 +512,31 @@
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
- Get_Default_CDClk(Default_CDClk_Freq);
- -- USBC AUX is not supposed to be enabled until the connect flow
- for AUX in reverse AUX_USBC1 .. AUX_USBC6 loop
- PD_Off (AUX);
- end loop;
+ if Config.Has_CDClk_PLL_Crawl then
+ XELPD.Aux_Off;
+ else
+ TGL.Aux_Off;
+ end if;
+
+ -- Wa_14011294188:ehl,jsl,tgl,rkl,adl-s,adl-p
+ Registers.Set_Mask
+ (Register => Registers.PCH_DSPCLK_GATE_D,
+ Mask => PCH_DPMGUNIT_CLOCK_GATE_DISABLE);
+
+ if Config.Has_CDClk_PLL_Crawl then
+ -- Wa_22011091694:adlp
+ Registers.Set_Mask
+ (Register => Registers.GEN9_CLKGATE_DIS_5,
+ Mask => 1 * 2 ** 17); --DPCE_GATING_DIS);
+
+ -- i915 calls this the "Bspec/49189 Initialize Sequence"
+ Registers.Unset_Mask
+ (Register => Registers.GEN8_CHICKEN_DCPR_1,
+ Mask => 1 * 2 ** 7); --DDI_CLOCK_REG_ACCESS);
+ else
+ -- Display WA #1185 WaDisableDARBFClkGating
+ Registers.Set_Mask (Registers.GEN9_CLKGATE_DIS_0, DARBF_GATING_DIS);
+ end if;
Registers.Set_Mask
(Register => Registers.NDE_RSTWRN_OPT,
@@ -710,14 +544,16 @@
Combo_Phy.Initialize;
- Registers.Wait_Set_Mask
- (Register => Registers.FUSE_STATUS,
- Mask => FUSE_STATUS_PG0_DIST_STATUS);
- PD_On (PW1);
+ if Config.Has_CDClk_PLL_Crawl then
+ XELPD.Init_Power;
+ else
+ TGL.Init_Power;
+ end if;
Get_Cur_CDClk (CDClk);
Config.CDClk := CDClk;
Get_Max_CDClk (Config.Max_CDClk);
+ Get_Default_CDClk (Default_CDClk_Freq);
if Config.CDClk /= Default_CDClk_Freq then
Set_CDClk (Default_CDClk_Freq);
end if;
@@ -725,42 +561,65 @@
Get_RawClk (Rawclk);
Config.Raw_Clock := RawClk;
- for PW in PW2 .. PW4 loop
- PD_On (PW);
- end loop;
+ if Config.Has_CDClk_PLL_Crawl then
+ Registers.Unset_And_Set_Mask
+ (Register => Registers.MBUS_CTL,
+ Mask_Unset => MBUS_HASHING_MODE_MASK or
+ MBUS_JOIN or
+ MBUS_JOIN_PIPE_SELECT_MASK,
+ Mask_Set => MBUS_HASHING_MODE_1x4 or
+ MBUS_JOIN or
+ MBUS_JOIN_PIPE_SELECT_NONE);
- PD_On (DDI_A);
- PD_On (AUX_A);
+ Registers.Unset_And_Set_Mask
+ (Register => Registers.DBUF_CTL_S0,
+ Mask_Unset => DBUF_CTL_MIN_TRACKER_STATE_SERVICE_MASK,
+ Mask_Set =>
+ Shift_Left (3, DBUF_CTL_MIN_TRACKER_STATE_SERVICE_SHIFT));
+ else
+ Registers.Unset_And_Set_Mask
+ (Register => Registers.DBUF_CTL_S0,
+ Mask_Unset => DBUF_CTL_TRACKER_STATE_SERVICE_MASK,
+ Mask_Set => Shift_Left (8, DBUF_CTL_TRACKER_STATE_SERVICE_SHIFT));
+ end if;
- -- Enable first DBUF slice
+ -- Enable required DBUF slices
Registers.Set_Mask (Registers.DBUF_CTL_S0, DBUF_CTL_DBUF_POWER_REQUEST);
Registers.Posting_Read (Registers.DBUF_CTL_S0);
Registers.Wait_Set_Mask (Registers.DBUF_CTL_S0, DBUF_CTL_DBUF_POWER_STATE);
- for I in MBUS_ABOX_CTL'Range loop
- Registers.Unset_And_Set_Mask
- (Register => MBUS_ABOX_CTL (I),
- Mask_Unset => MBUS_ABOX_MASK,
- Mask_Set => MBUS_ABOX_CREDITS);
- end loop;
+ if Config.Has_CDClk_PLL_Crawl then
+ for I in 1 .. 3 loop
+ Registers.Set_Mask (DBUF_Regs (I), DBUF_CTL_DBUF_POWER_REQUEST);
+ Registers.Posting_Read (DBUF_Regs (I));
+ Registers.Wait_Set_Mask (DBUF_Regs (I), DBUF_CTL_DBUF_POWER_STATE);
+ end loop;
+ end if;
- -- Set DBUF Tracker State Service to 8
- Registers.Unset_And_Set_Mask
- (Register => Registers.DBUF_CTL_S0,
- Mask_Unset => DBUF_CTL_TRACKER_STATE_SERVICE_MASK,
- Mask_Set => 8 * 2 ** DBUF_CTL_TRACKER_STATE_SERVICE_SHIFT);
- Registers.Unset_And_Set_Mask
- (Register => Registers.DBUF_CTL_S2,
- Mask_Unset => DBUF_CTL_TRACKER_STATE_SERVICE_MASK,
- Mask_Set => 8 * 2 ** DBUF_CTL_TRACKER_STATE_SERVICE_SHIFT);
+ if not Config.Has_CDClk_PLL_Crawl then
+ for I in MBUS_ABOX_CTL'Range loop
+ Registers.Unset_And_Set_Mask
+ (Register => MBUS_ABOX_CTL (I),
+ Mask_Unset => MBUS_ABOX_MASK,
+ Mask_Set => MBUS_ABOX_CREDITS);
+ end loop;
+ end if;
Configure_Bandwidth_Buddy;
-- Display WA #14011508470 tgl,dg1,rkl,adl-s,adl-p
Registers.Set_Mask
(Register => Registers.GEN11_CHICKEN_DCPR_2,
- Mask => DCPR_MASK_MAXLATENCY_MEMUP_CLR or DCPR_MASK_LPMODE or
- DCPR_SEND_RESP_IMM or DCPR_CLEAR_MEMSTAT_DIS);
+ Mask => DCPR_MASK_MAXLATENCY_MEMUP_CLR or
+ DCPR_MASK_LPMODE or
+ DCPR_SEND_RESP_IMM or
+ DCPR_CLEAR_MEMSTAT_DIS);
+
+ if Config.Has_CDClk_PLL_Crawl then
+ Registers.Write
+ (Register => Registers.DISPLAY_ERR_FATAL_MASK,
+ Value => 16#ffff_ffff#);
+ end if;
end Initialize;
procedure Limit_Dotclocks
@@ -776,9 +635,11 @@
procedure Update_CDClk (Configs : in out Pipe_Configs)
is
- New_CDClk : constant Frequency_Type :=
- Config_Helpers.Highest_Dotclock (Configs);
+ New_CDClk : Frequency_Type;
begin
+ Normalize_CDClk
+ (Div_Round_Up (Config_Helpers.Highest_Dotclock (Configs), 2),
+ New_CDClk);
Set_CDClk (New_CDClk);
Config_Helpers.Limit_Dotclocks (Configs, Config.CDClk);
end Update_CDClk;
@@ -800,53 +661,33 @@
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
- for PD in reverse Power_Domain loop
- if not Need_PD (PD, Configs) then
- PD_Off (PD);
- end if;
- end loop;
-
- for PD in Power_Domain loop
- if Need_PD (PD, Configs) then
- PD_On (PD);
- end if;
- end loop;
+ if Config.Has_XELPD_Power_Domains then
+ XELPD.Power_Set_To (Configs);
+ else
+ TGL.Power_Set_To (Configs);
+ end if;
end Power_Set_To;
- procedure Power_Up (Old_Configs, New_Configs : Pipe_Configs)
- is
- Success : Boolean;
+ procedure Power_Up (Old_Configs, New_Configs : Pipe_Configs) is
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
- Connectors.TC.TC_Cold_Request (Connectors.TC.Block, Success);
- if not Success then
- Debug.Put_Line ("Failed to unblock TCCOLD");
+ if Config.Has_XELPD_Power_Domains then
+ XELPD.Power_Up (Old_Configs, New_Configs);
+ else
+ TGL.Power_Up (Old_Configs, New_Configs);
end if;
-
- for PD in Power_Domain loop
- if not Need_PD (PD, Old_Configs) and Need_PD (PD, New_Configs) then
- PD_On (PD);
- end if;
- end loop;
end Power_Up;
procedure Power_Down (Old_Configs, Tmp_Configs, New_Configs : Pipe_Configs)
is
- Success : Boolean;
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
- for PD in reverse Power_Domain loop
- if (Need_PD (PD, Old_Configs) or Need_PD (PD, Tmp_Configs)) and
- not Need_PD (PD, New_Configs)
- then
- PD_Off (PD);
- end if;
- end loop;
- Connectors.TC.TC_Cold_Request (Connectors.TC.Unblock, Success);
- if not Success then
- Debug.Put_Line ("Failed to unblock TCCOLD");
+ if Config.Has_XELPD_Power_Domains then
+ XELPD.Power_Down (Old_Configs, Tmp_Configs, New_Configs);
+ else
+ TGL.Power_Down (Old_Configs, Tmp_Configs, New_Configs);
end if;
end Power_Down;
@@ -860,28 +701,31 @@
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
- Registers.Unset_Mask
- (Registers.DBUF_CTL_S0, DBUF_CTL_DBUF_POWER_REQUEST);
- Registers.Wait_Unset_Mask
- (Registers.DBUF_CTL_S0, DBUF_CTL_DBUF_POWER_STATE);
+ for I in reverse DBUF_Regs'Range loop
+ Registers.Unset_Mask
+ (DBUF_Regs (I), DBUF_CTL_DBUF_POWER_REQUEST);
+ Registers.Wait_Unset_Mask
+ (DBUF_Regs (I), DBUF_CTL_DBUF_POWER_STATE);
+ end loop;
-- Disable CD clock, bypass frequency is Refclk / 2
Get_Refclk (Refclk);
Set_CDClk (Refclk / 2);
- for AUX in reverse AUX_A .. AUX_USBC6 loop
- PD_Off (AUX);
- end loop;
-
- for DDI in reverse DDI_A .. DDI_USBC6 loop
- PD_Off (DDI);
- end loop;
-
- for PW in reverse PW1 .. PW5 loop
- PD_Off (PW);
- end loop;
+ if Config.Has_XELPD_Power_Domains then
+ XELPD.All_Off;
+ else
+ TGL.All_Off;
+ end if;
Combo_Phy.All_Off;
end Post_All_Off;
+ procedure Power_Up_Aux is
+ begin
+ if Config.Has_XELPD_Power_Domains then
+ XELPD.Power_Up_Aux;
+ end if;
+ end Power_Up_Aux;
+
end HW.GFX.GMA.Power_And_Clocks;
diff --git a/common/tigerlake/hw-gfx-gma-power_and_clocks.ads b/common/tigerlake/hw-gfx-gma-power_and_clocks.ads
index b3302fb..1ea09ae 100644
--- a/common/tigerlake/hw-gfx-gma-power_and_clocks.ads
+++ b/common/tigerlake/hw-gfx-gma-power_and_clocks.ads
@@ -40,6 +40,8 @@
procedure Power_Up (Old_Configs, New_Configs : Pipe_Configs);
procedure Power_Down (Old_Configs, Tmp_Configs, New_Configs : Pipe_Configs);
+ procedure Power_Up_Aux;
+
procedure Get_Refclk (Refclk : out Refclk_Range);
end HW.GFX.GMA.Power_And_Clocks;
--
To view, visit https://review.coreboot.org/c/libgfxinit/+/82146?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: libgfxinit
Gerrit-Branch: cros
Gerrit-Change-Id: Id01752a41e4e401a5f759453c12f368395eebdf2
Gerrit-Change-Number: 82146
Gerrit-PatchSet: 1
Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com>
Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com>
Gerrit-MessageType: newchange
1
0
[M] Change in libgfxinit[cros]: gma tgl: Add port detection
by Dinesh Gehlot (Code Review) 30 Apr '24
by Dinesh Gehlot (Code Review) 30 Apr '24
30 Apr '24
Attention is currently required from: Tim Wawrzynczak.
Hello Tim Wawrzynczak,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/libgfxinit/+/82145?usp=email
to review the following change.
Change subject: gma tgl: Add port detection
......................................................................
gma tgl: Add port detection
Mostly just detecting the _ISR registers, but during initialization,
this module also blocks TCCOLD so that Modular FIA registers can be
accessed. Instead of keeping track of the state of TCCOLD all of the
time (and enabling and re-enabling), this patch just blocks TCCOLD
once during initializaton and leaves it that way.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: I674e7c2dcd7738e3d76266ff36675dbd52fa5ae2
---
M common/tigerlake/hw-gfx-gma-port_detect.adb
1 file changed, 144 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/45/82145/1
diff --git a/common/tigerlake/hw-gfx-gma-port_detect.adb b/common/tigerlake/hw-gfx-gma-port_detect.adb
index a0bad14..681172b 100644
--- a/common/tigerlake/hw-gfx-gma-port_detect.adb
+++ b/common/tigerlake/hw-gfx-gma-port_detect.adb
@@ -15,19 +15,134 @@
with HW.GFX.GMA.Config;
with HW.GFX.GMA.Registers;
with HW.GFX.GMA.Config_Helpers;
+with HW.GFX.GMA.Connectors.TC;
with HW.Debug;
with GNAT.Source_Info;
package body HW.GFX.GMA.Port_Detect
is
- procedure Initialize is
+ type Digital_Port_Value is array (Digital_Port) of Word32;
+
+ function SDEISR_MASK (Port : Active_Port_Type) return Word32
+ is (case Port is
+ when DP1 | HDMI1 => 16#1_0000#,
+ when DP2 | HDMI2 => 16#2_0000#,
+ when DP3 | HDMI3 => 16#4_0000#,
+ when others => 0);
+
+ function DE_HPD_ISR_MASK (Port : Active_Port_Type) return Word32
+ is (case Port is
+ when USBC1_DP | USBC1_HDMI => 16#01_0000#,
+ when USBC2_DP | USBC2_HDMI => 16#02_0000#,
+ when USBC3_DP | USBC3_HDMI => 16#04_0000#,
+ when USBC4_DP | USBC4_HDMI => 16#08_0000#,
+ when USBC5_DP | USBC5_HDMI => 16#10_0000#,
+ when USBC6_DP | USBC6_HDMI => 16#20_0000#,
+ when others => 0);
+
+ function SHOTPLUG_CTL_DDI_HPD_ENABLE (Port : Combo_Port_Type) return Word32
+ is (case Port is
+ when DP1 | HDMI1 => 16#008#,
+ when DP2 | HDMI2 => 16#080#,
+ when DP3 | HDMI3 => 16#800#);
+
+ function SHOTPLUG_CTL_TC_DDI_HPD_ENABLE (Port : USBC_Port_Type)
+ return Word32
+ is (case Port is
+ when USBC1_DP | USBC1_HDMI => 16#00_0008#,
+ when USBC2_DP | USBC2_HDMI => 16#00_0080#,
+ when USBC3_DP | USBC3_HDMI => 16#00_0800#,
+ when USBC4_DP | USBC4_HDMI => 16#00_8000#,
+ when USBC5_DP | USBC5_HDMI => 16#08_0000#,
+ when USBC6_DP | USBC6_HDMI => 16#80_0000#);
+
+ function TC_HOTPLUG_CTL_HPD_ENABLE (Port : USBC_Port_Type)
+ return Word32
+ is (SHOTPLUG_CTL_TC_DDI_HPD_ENABLE (Port));
+
+ procedure Initialize
+ is
+ INIT_DISPLAY_DETECTED : constant := 1 * 2 ** 0;
+ Internal_Detected : Boolean;
+ Success : Boolean;
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+ -- only for DDI_A / eDP
+ if Config.Has_Presence_Straps and not Config.Ignore_Presence_Straps then
+ Registers.Is_Set_Mask
+ (Register => Registers.DDI_BUF_CTL_A,
+ Mask => INIT_DISPLAY_DETECTED,
+ Result => Internal_Detected);
+ else
+ Internal_Detected := True;
+ end if;
+ Config.Valid_Port (eDP) := Internal_Detected;
+
+ Registers.Unset_And_Set_Mask
+ (Register => Registers.SHPD_FILTER_CNT,
+ Mask_Unset => 16#1_ffff#,
+ Mask_Set => 16#1d9#);
+
+ -- Hotplug for combo ports
+ Registers.Set_Mask
+ (Register => Registers.SHOTPLUG_CTL,
+ Mask =>
+ SHOTPLUG_CTL_DDI_HPD_ENABLE (DP1) or -- also HDMI1
+ SHOTPLUG_CTL_DDI_HPD_ENABLE (DP2) or -- also HDMI2
+ SHOTPLUG_CTL_DDI_HPD_ENABLE (DP3)); -- also HDMI3
+
+ -- Hotplug for Type-C ports in legacy mode
+ Registers.Set_Mask
+ (Register => Registers.SHOTPLUG_CTL_TC,
+ Mask =>
+ SHOTPLUG_CTL_TC_DDI_HPD_ENABLE (USBC1_DP) or -- also USBC1_HDMI
+ SHOTPLUG_CTL_TC_DDI_HPD_ENABLE (USBC2_DP) or -- also USBC2_HDMI
+ SHOTPLUG_CTL_TC_DDI_HPD_ENABLE (USBC3_DP) or -- also USBC3_HDMI
+ SHOTPLUG_CTL_TC_DDI_HPD_ENABLE (USBC4_DP) or -- also USBC4_HDMI
+ SHOTPLUG_CTL_TC_DDI_HPD_ENABLE (USBC5_DP) or -- also USBC5_HDMI
+ SHOTPLUG_CTL_TC_DDI_HPD_ENABLE (USBC6_DP)); -- also USBC6_HDMI
+
+ -- Hotplug for Type-C ports in DP-Alt mode
+ Registers.Set_Mask
+ (Register => Registers.TC_HOTPLUG_CTL,
+ Mask =>
+ TC_HOTPLUG_CTL_HPD_ENABLE (USBC1_DP) or -- also USBC1_HDMI
+ TC_HOTPLUG_CTL_HPD_ENABLE (USBC2_DP) or -- also USBC2_HDMI
+ TC_HOTPLUG_CTL_HPD_ENABLE (USBC3_DP) or -- also USBC3_HDMI
+ TC_HOTPLUG_CTL_HPD_ENABLE (USBC4_DP) or -- also USBC4_HDMI
+ TC_HOTPLUG_CTL_HPD_ENABLE (USBC5_DP) or -- also USBC5_HDMI
+ TC_HOTPLUG_CTL_HPD_ENABLE (USBC6_DP)); -- also USBC6_HDMI
+
+ -- Validity can only be detected via hotplug
+ for Port in DP1 .. HDMI3 loop
+ Config.Valid_Port (Port) := True;
+ end loop;
+
+ -- For Type-C ports, we can check if the IOM PHY status is 'Complete'.
+ for Port in USBC1_DP .. USBC6_HDMI loop
+ Connectors.TC.Is_DP_Phy_Mode_Status_Complete
+ (Port => Config_Helpers.To_GPU_Port (Pipe_Index'First, Port),
+ Success => Config.Valid_Port (Port));
+ end loop;
+
+ -- TCCOLD should be blocked first before accessing FIA registers
+ -- during e.g. connect flows. It can be unblocked only after
+ -- done accessing FIA registers and there is no longer a
+ -- connection i.e., after all ports are disconnected.
+ -- In order to avoid keeping track of the state and constantly
+ -- blocking and unblocking, we just block it once at the beginning and
+ -- leave it that way.
+ Connectors.TC.TC_Cold_Request (Connectors.TC.Block, Success);
+ if not Success then
+ Debug.Put_Line ("Failed to bock TCCOLD, Type-C will not work!");
+ for Port in USBC1_DP .. USBC6_HDMI loop
+ Config.Valid_Port (Port) := False;
+ end loop;
+ end if;
end Initialize;
- pragma Warnings (Off, "unused variable ""Port""",
- Reason => "Not yet implemented.");
procedure Hotplug_Detect
(Port : in Active_Port_Type;
Detected : out Boolean)
@@ -35,13 +150,37 @@
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
Detected := False;
+
+ if Port = eDP then
+ Detected := Config.Valid_Port (eDP);
+ return;
+ end if;
+
+ -- DP-Alt HPD is in the north display hotplug registers
+ if Port in USBC_Port_Type then
+ Registers.Is_Set_Mask
+ (Register => Registers.GEN11_DE_HPD_ISR,
+ Mask => DE_HPD_ISR_MASK (Port),
+ Result => Detected);
+ end if;
+
+ -- Legacy HDMI/DP hotplug is detected through the south display registers
+ if Port in Combo_Port_Type then
+ Registers.Is_Set_Mask
+ (Register => Registers.SDEISR,
+ Mask => SDEISR_MASK (Port),
+ Result => Detected);
+ end if;
end Hotplug_Detect;
- pragma Warnings (On, "unused variable ""Port""");
procedure Clear_Hotplug_Detect (Port : Active_Port_Type)
is
+ Ignored_HPD : Boolean;
begin
- pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+ pragma Warnings (GNATprove, Off, "unused assignment to ""Ignored_HPD""",
+ Reason => "We want to clear pending events only");
+ Port_Detect.Hotplug_Detect (Port, Ignored_HPD);
+ pragma Warnings (GNATprove, On, "unused assignment to ""Ignored_HPD""");
end Clear_Hotplug_Detect;
end HW.GFX.GMA.Port_Detect;
--
To view, visit https://review.coreboot.org/c/libgfxinit/+/82145?usp=email
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Gerrit-Project: libgfxinit
Gerrit-Branch: cros
Gerrit-Change-Id: I674e7c2dcd7738e3d76266ff36675dbd52fa5ae2
Gerrit-Change-Number: 82145
Gerrit-PatchSet: 1
Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com>
Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com>
Gerrit-MessageType: newchange
1
0
[XL] Change in libgfxinit[cros]: gma tgl: Add connector programming
by Dinesh Gehlot (Code Review) 30 Apr '24
by Dinesh Gehlot (Code Review) 30 Apr '24
30 Apr '24
Attention is currently required from: Nico Huber, Tim Wawrzynczak.
Hello Nico Huber, Tim Wawrzynczak,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/libgfxinit/+/82144?usp=email
to review the following change.
Change subject: gma tgl: Add connector programming
......................................................................
gma tgl: Add connector programming
This patch adds support for enabling displays on both combo PHY ports
and Type-C ports over DP-Alt mode.
Verified eDP, HDMI (not Type-C), and DP Alt mode on google/delbin.
Change-Id: I908e8bef8451d21eecde9ce6defddc2b3df7f738
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
M common/hw-gfx-gma-config.ads.template
M common/hw-gfx-gma.adb
M common/hw-gfx-gma.ads
M common/tigerlake/Makefile.inc
A common/tigerlake/hw-gfx-gma-connectors-combo_phy.adb
A common/tigerlake/hw-gfx-gma-connectors-combo_phy.ads
A common/tigerlake/hw-gfx-gma-connectors-tc.adb
A common/tigerlake/hw-gfx-gma-connectors-tc.ads
M common/tigerlake/hw-gfx-gma-connectors.adb
M common/tigerlake/hw-gfx-gma-power_and_clocks.adb
10 files changed, 1,625 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/44/82144/1
diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template
index e168144..b56086f 100644
--- a/common/hw-gfx-gma-config.ads.template
+++ b/common/hw-gfx-gma-config.ads.template
@@ -312,6 +312,9 @@
----------- Rawclk -----------
Need_Rawclk_Numerator : <genbool> := Tigerlake_On;
+ ----------- Combo Phy --------
+ Has_TGL_Buffer_Translations : <tglbool> := CPU_Tigerlake;
+
----------------------------------------------------------------------------
Max_Pipe : <ilkvar> Pipe_Index :=
diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb
index 6331020..2f58da3 100644
--- a/common/hw-gfx-gma.adb
+++ b/common/hw-gfx-gma.adb
@@ -652,12 +652,15 @@
(GNATprove, Off, """Registers.Register_State"" * is not modified*",
Reason => "Power_Up_VGA is only effective in certain configurations.");
pragma Warnings
+ (GNATprove, Off, """PCode.Mailbox_Ready"" * is not modified*",
+ Reason => "Pcode is only used in certain configurations.");
+ pragma Warnings
(GNATprove, Off, "no check message justified*", Reason => "see below");
procedure Power_Up_VGA
with
Refined_Global =>
(Input => (Cur_Configs, Config.Variable, Time.State),
- In_Out => (Registers.Register_State),
+ In_Out => (Registers.Register_State, PCode.Mailbox_Ready),
Proof_In => (Initialized))
is
Fake_Config : constant Pipe_Configs :=
@@ -677,6 +680,8 @@
pragma Annotate
(GNATprove, Intentional, "unused global",
"Power_Up_VGA is only effective in certain configurations.");
+ pragma Warnings
+ (GNATprove, On, """PCode.Mailbox_Ready"" * is not modified*");
pragma Warnings (GNATprove, On, "no check message justified*");
pragma Warnings
(GNATprove, On, """Registers.Register_State"" * is not modified*");
diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads
index 8ef2247..2752cfa 100644
--- a/common/hw-gfx-gma.ads
+++ b/common/hw-gfx-gma.ads
@@ -145,8 +145,8 @@
procedure Power_Up_VGA
with
Global =>
- (Input => (State, Time.State),
- In_Out => (Device_State),
+ (Input => (Time.State),
+ In_Out => (Device_State, State),
Proof_In => (Init_State)),
Pre => Is_Initialized;
diff --git a/common/tigerlake/Makefile.inc b/common/tigerlake/Makefile.inc
index 86ed920..b76f2fe 100644
--- a/common/tigerlake/Makefile.inc
+++ b/common/tigerlake/Makefile.inc
@@ -3,6 +3,10 @@
gfxinit-y += hw-gfx-gma-power_and_clocks.adb
gfxinit-y += hw-gfx-gma-power_and_clocks.ads
gfxinit-y += hw-gfx-gma-connectors.adb
+gfxinit-y += hw-gfx-gma-connectors-tc.adb
+gfxinit-y += hw-gfx-gma-connectors-tc.ads
+gfxinit-y += hw-gfx-gma-connectors-combo_phy.adb
+gfxinit-y += hw-gfx-gma-connectors-combo_phy.ads
gfxinit-y += hw-gfx-gma-port_detect.adb
gfxinit-y += hw-gfx-gma-plls.adb
gfxinit-y += hw-gfx-gma-plls.ads
diff --git a/common/tigerlake/hw-gfx-gma-connectors-combo_phy.adb b/common/tigerlake/hw-gfx-gma-connectors-combo_phy.adb
new file mode 100644
index 0000000..4f28a22
--- /dev/null
+++ b/common/tigerlake/hw-gfx-gma-connectors-combo_phy.adb
@@ -0,0 +1,586 @@
+--
+-- Copyright (C) 2022 Google, LLC
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.DP_Training;
+with HW.GFX.GMA.Config;
+with HW.GFX.GMA.DP_Aux_Ch;
+with HW.GFX.GMA.Registers;
+
+with HW.Debug;
+with GNAT.Source_Info;
+
+package body HW.GFX.GMA.Connectors.Combo_Phy is
+
+ DDI_BUF_CTL_BUFFER_ENABLE : constant := 1 * 2 ** 31;
+ DDI_BUF_CTL_TRANS_SELECT_MASK : constant := 16#f# * 2 ** 24;
+ DDI_BUF_CTL_PORT_REVERSAL : constant := 1 * 2 ** 16;
+ DDI_BUF_CTL_PORT_WIDTH_MASK : constant := 7 * 2 ** 1;
+ DDI_BUF_CTL_PORT_WIDTH_1_LANE : constant := 0 * 2 ** 1;
+ DDI_BUF_CTL_PORT_WIDTH_2_LANES : constant := 1 * 2 ** 1;
+ DDI_BUF_CTL_PORT_WIDTH_4_LANES : constant := 3 * 2 ** 1;
+ DDI_BUF_CTL_IDLE_STATUS : constant := 1 * 2 ** 7;
+
+ type Combo_Port_Regs is array (Combo_Port) of Registers.Registers_Index;
+ DDI_BUF_CTL : constant Combo_Port_Regs :=
+ Combo_Port_Regs'
+ (DIGI_A => Registers.DDI_BUF_CTL_A,
+ DIGI_B => Registers.DDI_BUF_CTL_B,
+ DIGI_C => Registers.DDI_BUF_CTL_C);
+
+ type DDI_BUF_CTL_PORT_WIDTH_T is array (HW.GFX.DP_Lane_Count) of Word32;
+ DDI_BUF_CTL_PORT_WIDTH : constant DDI_BUF_CTL_PORT_WIDTH_T :=
+ DDI_BUF_CTL_PORT_WIDTH_T'
+ (HW.GFX.DP_Lane_Count_1 => DDI_BUF_CTL_PORT_WIDTH_1_LANE,
+ HW.GFX.DP_Lane_Count_2 => DDI_BUF_CTL_PORT_WIDTH_2_LANES,
+ HW.GFX.DP_Lane_Count_4 => DDI_BUF_CTL_PORT_WIDTH_4_LANES);
+
+ type Port_Regs_Record is record
+ PORT_TX_DW5_LN0 : Registers.Registers_Index;
+ PORT_TX_DW5_GRP : Registers.Registers_Index;
+ PORT_TX_DW7_LN0 : Registers.Registers_Index;
+ PORT_TX_DW7_GRP : Registers.Registers_Index;
+ PORT_TX_DW2_LN0 : Registers.Registers_Index;
+ PORT_TX_DW2_GRP : Registers.Registers_Index;
+ PORT_TX_DW4_LN0 : Registers.Registers_Index;
+ PORT_TX_DW4_LN1 : Registers.Registers_Index;
+ PORT_TX_DW4_LN2 : Registers.Registers_Index;
+ PORT_TX_DW4_LN3 : Registers.Registers_Index;
+ PORT_TX_DW4_GRP : Registers.Registers_Index;
+ PORT_PCS_DW1_LN0 : Registers.Registers_Index;
+ PORT_PCS_DW1_GRP : Registers.Registers_Index;
+ PORT_CL_DW5 : Registers.Registers_Index;
+ PORT_CL_DW10 : Registers.Registers_Index;
+ DDI_BUF_CTL : Registers.Registers_Index;
+ end record;
+
+ type Port_Regs_Array is array (Combo_Port) of Port_Regs_Record;
+ Port_Regs : constant Port_Regs_Array :=
+ Port_Regs_Array'
+ (DIGI_A =>
+ (Registers.PORT_TX_DW5_LN0_A, Registers.PORT_TX_DW5_GRP_A,
+ Registers.PORT_TX_DW7_LN0_A, Registers.PORT_TX_DW7_GRP_A,
+ Registers.PORT_TX_DW2_LN0_A, Registers.PORT_TX_DW2_GRP_A,
+ Registers.PORT_TX_DW4_LN0_A, Registers.PORT_TX_DW4_LN1_A,
+ Registers.PORT_TX_DW4_LN2_A, Registers.PORT_TX_DW4_LN3_A,
+ Registers.PORT_TX_DW4_GRP_A,
+ Registers.PORT_PCS_DW1_LN0_A, Registers.PORT_PCS_DW1_GRP_A,
+ Registers.PORT_CL_DW5_A,
+ Registers.PORT_CL_DW10_A,
+ Registers.DDI_BUF_CTL_A),
+ DIGI_B =>
+ (Registers.PORT_TX_DW5_LN0_B, Registers.PORT_TX_DW5_GRP_B,
+ Registers.PORT_TX_DW7_LN0_B, Registers.PORT_TX_DW7_GRP_B,
+ Registers.PORT_TX_DW2_LN0_B, Registers.PORT_TX_DW2_GRP_B,
+ Registers.PORT_TX_DW4_LN0_B, Registers.PORT_TX_DW4_LN1_B,
+ Registers.PORT_TX_DW4_LN2_B, Registers.PORT_TX_DW4_LN3_B,
+ Registers.PORT_TX_DW4_GRP_B,
+ Registers.PORT_PCS_DW1_LN0_B, Registers.PORT_PCS_DW1_GRP_B,
+ Registers.PORT_CL_DW5_B,
+ Registers.PORT_CL_DW10_B,
+ Registers.DDI_BUF_CTL_B),
+ DIGI_C =>
+ (Registers.PORT_TX_DW5_LN0_C, Registers.PORT_TX_DW5_GRP_C,
+ Registers.PORT_TX_DW7_LN0_C, Registers.PORT_TX_DW7_GRP_C,
+ Registers.PORT_TX_DW2_LN0_C, Registers.PORT_TX_DW2_GRP_C,
+ Registers.PORT_TX_DW4_LN0_C, Registers.PORT_TX_DW4_LN1_C,
+ Registers.PORT_TX_DW4_LN2_C, Registers.PORT_TX_DW4_LN3_C,
+ Registers.PORT_TX_DW4_GRP_C,
+ Registers.PORT_PCS_DW1_LN0_C, Registers.PORT_PCS_DW1_GRP_C,
+ Registers.PORT_CL_DW5_C,
+ Registers.PORT_CL_DW10_C,
+ Registers.DDI_BUF_CTL_C));
+
+ type Lanes is (LN0, LN1, LN2, LN3);
+ type Lanes_Range is new Natural range 1 .. 4;
+ function PORT_TX_DW4 (Lane : Lanes; Port : Combo_Port)
+ return Registers.Registers_Index
+ is (case Lane is
+ when LN0 => Port_Regs (Port).PORT_TX_DW4_LN0,
+ when LN1 => Port_Regs (Port).PORT_TX_DW4_LN1,
+ when LN2 => Port_Regs (Port).PORT_TX_DW4_LN2,
+ when LN3 => Port_Regs (Port).PORT_TX_DW4_LN3);
+
+ PORT_PCS_DW1_LN0_COMMON_KEEPER : constant := 1 * 2 ** 26;
+
+ type Post_Cursor is new Natural range 0 .. 63;
+ function PORT_TX_DW4_POST_CURSOR1 (P : Post_Cursor) return Word32 is
+ (Shift_Left (Word32 (P), 12));
+
+ type Cursor_Coeff is new Natural range 0 .. 63;
+ function PORT_TX_DW4_CURSOR_COEFF (C : Cursor_Coeff) return Word32 is
+ (Word32 (C));
+
+ type N_Scalar is new Natural range 0 .. 127;
+ function PORT_TX_DW7_N_SCALAR (N : N_Scalar) return Word32 is
+ (Shift_Left (Word32 (N), 24));
+
+ type Swing_Select is new Natural range 0 .. 15;
+ function PORT_TX_SWING_SEL_UPPER (S : Swing_Select) return Word32 is
+ (Shift_Left (Shift_Right (Word32(S), 3), 15));
+ function PORT_TX_SWING_SEL_LOWER (S : Swing_Select) return Word32 is
+ (Shift_Left (Word32(S), 11));
+
+ type Buffer_Trans is record
+ DW2_SWING_SEL : Swing_Select;
+ DW7_N_SCALAR : N_Scalar;
+ DW4_CURSOR_COEFF : Cursor_Coeff;
+ DW4_POST_CURSOR1 : Post_Cursor;
+ end record;
+
+ type Buffer_Trans_HDMI_Range is new Natural range 0 .. 6;
+ type Buffer_Trans_HDMI_Array is array (Buffer_Trans_HDMI_Range) of Buffer_Trans;
+ Buffer_Trans_HDMI : constant Buffer_Trans_HDMI_Array :=
+ Buffer_Trans_HDMI_Array'(
+ (16#A#, 16#60#, 16#3F#, 16#00#),
+ (16#B#, 16#73#, 16#36#, 16#09#),
+ (16#6#, 16#7F#, 16#31#, 16#0E#),
+ (16#B#, 16#73#, 16#3F#, 16#00#),
+ (16#6#, 16#7F#, 16#37#, 16#08#),
+ (16#6#, 16#7F#, 16#3F#, 16#00#),
+ (16#6#, 16#7F#, 16#35#, 16#0A#));
+
+ type Buffer_Trans_DP_Range is new Natural range 0 .. 9;
+ type Buffer_Trans_DP_Array is array (Buffer_Trans_DP_Range) of Buffer_Trans;
+
+ TGL_Buffer_Trans_DP_HBR : constant Buffer_Trans_DP_Array :=
+ Buffer_Trans_DP_Array'(
+ (16#a#, 16#32#, 16#3f#, 16#00#),
+ (16#a#, 16#4f#, 16#37#, 16#08#),
+ (16#c#, 16#71#, 16#2f#, 16#10#),
+ (16#6#, 16#7d#, 16#2b#, 16#14#),
+ (16#a#, 16#4c#, 16#3f#, 16#00#),
+ (16#c#, 16#73#, 16#34#, 16#0b#),
+ (16#6#, 16#7f#, 16#2f#, 16#10#),
+ (16#c#, 16#6c#, 16#3c#, 16#03#),
+ (16#6#, 16#7f#, 16#35#, 16#0a#),
+ (16#6#, 16#7f#, 16#3f#, 16#00#));
+
+ TGL_Buffer_Trans_DP_HBR2 : constant Buffer_Trans_DP_Array :=
+ Buffer_Trans_DP_Array'(
+ (16#a#, 16#35#, 16#3f#, 16#00#),
+ (16#a#, 16#4f#, 16#37#, 16#08#),
+ (16#c#, 16#63#, 16#2f#, 16#10#),
+ (16#6#, 16#7f#, 16#2b#, 16#14#),
+ (16#a#, 16#47#, 16#3f#, 16#00#),
+ (16#c#, 16#63#, 16#34#, 16#0b#),
+ (16#6#, 16#7f#, 16#2f#, 16#10#),
+ (16#c#, 16#61#, 16#3c#, 16#03#),
+ (16#6#, 16#7b#, 16#35#, 16#0a#),
+ (16#6#, 16#7f#, 16#3f#, 16#00#));
+
+ TGL_Buffer_Trans_DP_HBR2_U_Y : constant Buffer_Trans_DP_Array :=
+ Buffer_Trans_DP_Array'(
+ (16#a#, 16#35#, 16#3f#, 16#00#),
+ (16#a#, 16#4f#, 16#36#, 16#09#),
+ (16#c#, 16#60#, 16#32#, 16#0d#),
+ (16#c#, 16#7f#, 16#2d#, 16#12#),
+ (16#c#, 16#47#, 16#3f#, 16#00#),
+ (16#c#, 16#6f#, 16#36#, 16#09#),
+ (16#6#, 16#7d#, 16#32#, 16#0d#),
+ (16#6#, 16#60#, 16#3c#, 16#03#),
+ (16#6#, 16#7f#, 16#34#, 16#0b#),
+ (16#6#, 16#7f#, 16#3f#, 16#00#));
+
+ TGL_Buffer_Trans_DP_HBR2_EDP_HBR3 : constant Buffer_Trans_DP_Array :=
+ Buffer_Trans_DP_Array'(
+ (16#a#, 16#35#, 16#3f#, 16#00#),
+ (16#a#, 16#4f#, 16#37#, 16#08#),
+ (16#c#, 16#71#, 16#2f#, 16#10#),
+ (16#6#, 16#7f#, 16#2b#, 16#14#),
+ (16#a#, 16#4c#, 16#3f#, 16#00#),
+ (16#c#, 16#73#, 16#34#, 16#0b#),
+ (16#6#, 16#7f#, 16#2f#, 16#10#),
+ (16#c#, 16#6c#, 16#3c#, 16#03#),
+ (16#6#, 16#7f#, 16#35#, 16#0a#),
+ (16#6#, 16#7f#, 16#3f#, 16#00#));
+
+ TGL_Buffer_Trans_EDP_HBR2 : constant Buffer_Trans_DP_Array :=
+ Buffer_Trans_DP_Array'(
+ (16#0#, 16#7F#, 16#3F#, 16#00#),
+ (16#8#, 16#7F#, 16#38#, 16#07#),
+ (16#1#, 16#7F#, 16#33#, 16#0C#),
+ (16#9#, 16#7F#, 16#31#, 16#0E#),
+ (16#8#, 16#7F#, 16#3F#, 16#00#),
+ (16#1#, 16#7F#, 16#38#, 16#07#),
+ (16#9#, 16#7F#, 16#35#, 16#0A#),
+ (16#1#, 16#7F#, 16#3F#, 16#00#),
+ (16#9#, 16#7F#, 16#38#, 16#07#),
+ (16#9#, 16#7F#, 16#3F#, 16#00#));
+
+ ADL_Buffer_Trans_EDP_HBR3 : constant Buffer_Trans_DP_Array :=
+ Buffer_Trans_DP_Array'(
+ (16#a#, 16#35#, 16#3f#, 16#00#),
+ (16#a#, 16#4f#, 16#37#, 16#08#),
+ (16#c#, 16#71#, 16#30#, 16#0f#),
+ (16#6#, 16#7f#, 16#2b#, 16#14#),
+ (16#a#, 16#4c#, 16#3f#, 16#00#),
+ (16#c#, 16#73#, 16#34#, 16#0b#),
+ (16#6#, 16#7f#, 16#30#, 16#0f#),
+ (16#c#, 16#63#, 16#3f#, 16#00#),
+ (16#6#, 16#7f#, 16#38#, 16#07#),
+ (16#6#, 16#7f#, 16#3f#, 16#00#));
+
+ ADL_Buffer_Trans_EDP_HBR2 : constant Buffer_Trans_DP_Array :=
+ Buffer_Trans_DP_Array'(
+ (16#4#, 16#50#, 16#38#, 16#07#),
+ (16#4#, 16#58#, 16#35#, 16#0a#),
+ (16#4#, 16#60#, 16#34#, 16#0b#),
+ (16#4#, 16#6a#, 16#32#, 16#0d#),
+ (16#4#, 16#5e#, 16#38#, 16#07#),
+ (16#4#, 16#61#, 16#36#, 16#09#),
+ (16#4#, 16#6b#, 16#34#, 16#0b#),
+ (16#4#, 16#69#, 16#39#, 16#06#),
+ (16#4#, 16#73#, 16#37#, 16#08#),
+ (16#4#, 16#7a#, 16#38#, 16#07#));
+
+ ADL_Buffer_Trans_DP_HBR3 : constant Buffer_Trans_DP_Array :=
+ Buffer_Trans_DP_Array'(
+ (16#a#, 16#35#, 16#3f#, 16#00#),
+ (16#a#, 16#4f#, 16#37#, 16#08#),
+ (16#c#, 16#71#, 16#30#, 16#0f#),
+ (16#6#, 16#7f#, 16#2b#, 16#14#),
+ (16#a#, 16#4c#, 16#3f#, 16#00#),
+ (16#c#, 16#73#, 16#34#, 16#0b#),
+ (16#6#, 16#7f#, 16#30#, 16#0f#),
+ (16#c#, 16#63#, 16#3f#, 16#00#),
+ (16#6#, 16#7f#, 16#38#, 16#07#),
+ (16#6#, 16#7f#, 16#3f#, 16#00#));
+
+ ADL_Buffer_Trans_DP_HBR : constant Buffer_Trans_DP_Array :=
+ Buffer_Trans_DP_Array'(
+ (16#a#, 16#35#, 16#3f#, 16#00#),
+ (16#a#, 16#4f#, 16#37#, 16#08#),
+ (16#c#, 16#71#, 16#31#, 16#0e#),
+ (16#6#, 16#7f#, 16#2c#, 16#13#),
+ (16#a#, 16#4c#, 16#3f#, 16#00#),
+ (16#c#, 16#73#, 16#34#, 16#0b#),
+ (16#6#, 16#7f#, 16#2f#, 16#10#),
+ (16#c#, 16#7c#, 16#3c#, 16#03#),
+ (16#6#, 16#7f#, 16#35#, 16#0a#),
+ (16#6#, 16#7f#, 16#3f#, 16#00#));
+
+ PORT_CL_DW10_PWR_DOWN_LN_MASK : constant := 16#f# * 2 ** 4;
+ PORT_CL_DW10_PWR_UP_ALL : constant := 0 * 2 ** 4;
+ PORT_CL_DW10_PWR_DOWN_LN_3_2 : constant := 16#c# * 2 ** 4;
+ PORT_CL_DW10_PWR_DOWN_LN_3_2_1 : constant := 16#e# * 2 ** 4;
+ PORT_CL_DW10_PWR_DOWN_LN_1_0 : constant := 16#3# * 2 ** 4;
+ PORT_CL_DW10_PWR_DOWN_LN_2_1_0 : constant := 16#7# * 2 ** 4;
+
+ EDP4K2K_MODE_OVRD_EN : constant := 1 * 2 ** 2;
+ EDP4K2K_MODE_OVRD_OPTIMIZED : constant := 1 * 2 ** 3;
+
+ ---------------------------------------------------------------------
+
+ procedure Set_Vswing_And_Deemphasis
+ (Port : Combo_Port;
+ Buf_Trans : Buffer_Trans;
+ Display : Display_Type;
+ Lane_Count : Lanes_Range)
+ is
+ type Training_Values is (Training_Enable, Training_Disable);
+
+ PORT_TX_DW5_TX_TRAINING_EN : constant := 1 * 2 ** 31;
+ PORT_TX_DW5_SCALING_MODE_SEL_MASK : constant := 7 * 2 ** 18;
+ PORT_TX_DW5_RTERM_SELECT_MASK : constant := 7 * 2 ** 3;
+ PORT_TX_DW5_TAP2_DISABLE : constant := 1 * 2 ** 30;
+ PORT_TX_DW5_TAP3_DISABLE : constant := 1 * 2 ** 29;
+ PORT_TX_DW5_CURSOR_PROGRAM : constant := 1 * 2 ** 26;
+ PORT_TX_DW5_COEFF_POLARITY : constant := 1 * 2 ** 25;
+
+ PORT_TX_DW2_RCOMP_SCALAR_MASK : constant := 16#ff# * 2 ** 0;
+ PORT_TX_DW2_SWING_SEL_LOWER_MASK : constant := 7 * 2 ** 11;
+ PORT_TX_DW2_SWING_SEL_UPPER : constant := 1 * 2 ** 15;
+
+ PORT_TX_DW4_LOADGEN_SELECT : constant := 1 * 2 ** 31;
+ PORT_TX_DW4_POST_CURSOR2_MASK : constant := 16#3f# * 2 ** 6;
+ PORT_TX_DW4_POST_CURSOR1_MASK : constant := 16#3f# * 2 ** 12;
+ PORT_TX_DW4_CURSOR_COEFF_MASK : constant := 16#3f# * 2 ** 0;
+
+ PORT_TX_DW7_N_SCALAR_MASK : constant := 16#7f# * 2 ** 24;
+
+ type Scaling_Mode is new Natural range 0 .. 7;
+ function PORT_TX_DW5_SCALING_MODE_SEL (S : Scaling_Mode) return Word32 is
+ (Shift_Left (Word32 (S), 18));
+
+ type Rterm_Select is new Natural range 0 .. 7;
+ function PORT_TX_DW5_RTERM_SELECT (R : Rterm_Select) return Word32 is
+ (Shift_Left (Word32 (R), 3));
+
+ type Rcomp_Scalar is new Natural range 0 .. 255;
+ function PORT_TX_DW2_RCOMP_SCALAR (R : Rcomp_Scalar) return Word32 is
+ (Word32 (R));
+
+ procedure Set_Tx_Training (Port : Combo_Port; Training : Training_Values) is
+ DW5 : Word32;
+ begin
+ Registers.Read (Port_Regs (Port).PORT_TX_DW5_LN0, DW5);
+ Registers.Write
+ (Register => Port_Regs (Port).PORT_TX_DW5_GRP,
+ Value => (if Training = Training_Enable
+ then DW5 or PORT_TX_DW5_TX_TRAINING_EN
+ else DW5 and not PORT_TX_DW5_TX_TRAINING_EN));
+ end Set_Tx_Training;
+
+ Tmp : Word32;
+ PORT_CL_DW5_SUS_CLOCK_CONFIG : constant := 3 * 2 ** 0;
+ begin
+ -- Enable common keeper for DP/eDP only
+ Registers.Read (Port_Regs (Port).PORT_PCS_DW1_LN0, Tmp);
+ Registers.Write
+ (Port_Regs (Port).PORT_PCS_DW1_GRP,
+ (if Display = DP
+ then Tmp or PORT_PCS_DW1_LN0_COMMON_KEEPER
+ else Tmp and not PORT_PCS_DW1_LN0_COMMON_KEEPER));
+
+ -- Program loadgen select (group access is not allowed since each lane may
+ -- have a unique value.
+ -- <= 6GHz, 4 lanes (0, 1, 1, 1)
+ -- <= 6GHz, 1,2 lanes (0, 1, 1, 0)
+ -- > 6GHz, any lanes (0, 0, 0, 0)
+ for Lane in Lanes loop
+ if (Lane_Count = 4 and Lane /= LN0) or
+ (Lane_Count < 4 and (Lane = LN1 or Lane = LN2))
+ then
+ Registers.Set_Mask (PORT_TX_DW4 (Lane, Port),
+ PORT_TX_DW4_LOADGEN_SELECT);
+ else
+ Registers.Unset_Mask (PORT_TX_DW4 (Lane, Port),
+ PORT_TX_DW4_LOADGEN_SELECT);
+ end if;
+ end loop;
+
+ Registers.Set_Mask
+ (Register => Port_Regs (Port).PORT_CL_DW5,
+ Mask => PORT_CL_DW5_SUS_CLOCK_CONFIG);
+
+ -- In order to change swing values, training must be disabled
+ Set_Tx_Training (Port, Training_Disable);
+
+ if Display = DP then
+ Registers.Unset_Mask
+ (Register => Port_Regs (Port).PORT_CL_DW10,
+ Mask => EDP4K2K_MODE_OVRD_EN or EDP4K2K_MODE_OVRD_OPTIMIZED);
+ end if;
+
+ Registers.Read (Port_Regs (Port).PORT_TX_DW5_LN0, Tmp);
+ Tmp := Tmp and not
+ (PORT_TX_DW5_SCALING_MODE_SEL_MASK or
+ PORT_TX_DW5_RTERM_SELECT_MASK or
+ PORT_TX_DW5_TAP2_DISABLE or
+ PORT_TX_DW5_TAP3_DISABLE or
+ PORT_TX_DW5_CURSOR_PROGRAM or
+ PORT_TX_DW5_COEFF_POLARITY);
+ Tmp := Tmp or
+ PORT_TX_DW5_SCALING_MODE_SEL (2) or
+ PORT_TX_DW5_RTERM_SELECT (6) or
+ PORT_TX_DW5_TAP3_DISABLE;
+ Registers.Write (Port_Regs (Port).PORT_TX_DW5_GRP, Tmp);
+
+ Registers.Read (Port_Regs (Port).PORT_TX_DW2_LN0, Tmp);
+ Tmp := Tmp and not
+ (PORT_TX_DW2_RCOMP_SCALAR_MASK or
+ PORT_TX_DW2_SWING_SEL_LOWER_MASK or
+ PORT_TX_DW2_SWING_SEL_UPPER);
+ Tmp := Tmp or PORT_TX_SWING_SEL_UPPER (Buf_Trans.DW2_SWING_SEL);
+ Tmp := Tmp or PORT_TX_SWING_SEL_LOWER (Buf_Trans.DW2_SWING_SEL);
+ Tmp := Tmp or PORT_TX_DW2_RCOMP_SCALAR (16#98#);
+ Registers.Write (Port_Regs (Port).PORT_TX_DW2_GRP, Tmp);
+
+ -- Cannot write to GRP, because it would overwrite individual loadgen bits
+ for Lane in Lanes loop
+ Registers.Read (PORT_TX_DW4 (Lane, Port), Tmp);
+ Tmp := Tmp and not
+ (PORT_TX_DW4_POST_CURSOR2_MASK or
+ PORT_TX_DW4_POST_CURSOR1_MASK or
+ PORT_TX_DW4_CURSOR_COEFF_MASK);
+ Tmp := Tmp or PORT_TX_DW4_POST_CURSOR1 (Buf_Trans.DW4_POST_CURSOR1);
+ Tmp := Tmp or PORT_TX_DW4_CURSOR_COEFF (Buf_Trans.DW4_CURSOR_COEFF);
+ Registers.Write (PORT_TX_DW4 (Lane, Port), Tmp);
+ end loop;
+
+ Registers.Read (Port_Regs (Port).PORT_TX_DW7_LN0, Tmp);
+ Tmp := Tmp and not PORT_TX_DW7_N_SCALAR_MASK;
+ Tmp := Tmp or PORT_TX_DW7_N_SCALAR (Buf_Trans.DW7_N_SCALAR);
+ Registers.Write (Port_Regs (Port).PORT_TX_DW7_GRP, Tmp);
+
+ -- To trigger an update of swing values, set training enable
+ Set_Tx_Training (Port, Training_Enable);
+ end Set_Vswing_And_Deemphasis;
+
+ ---------------------------------------------------------------------
+
+ procedure Power_Up_Lanes
+ (Port : Combo_Port;
+ Lane_Count : Lanes_Range)
+ is
+ Lane_Mask : constant Word32 :=
+ (case Lane_Count is
+ -- if Lane_Reversal then PWR_DOWN_LN_2_1_0
+ -- else PORT_CL_DW10_PWR_DOWN_LN_3_2_1
+ when 1 => PORT_CL_DW10_PWR_DOWN_LN_3_2_1,
+ -- if Lane_Reversal then PWR_DOWN_1_0
+ -- else PORT_CL_DW10_PWR_DOWN_LN_3_2
+ when 2 => PORT_CL_DW10_PWR_DOWN_LN_3_2,
+ when others => PORT_CL_DW10_PWR_UP_ALL);
+ begin
+ Registers.Unset_And_Set_Mask
+ (Register => Port_Regs (Port).PORT_CL_DW10,
+ Mask_Unset => PORT_CL_DW10_PWR_DOWN_LN_MASK,
+ Mask_Set => Lane_Mask);
+ end Power_Up_Lanes;
+
+ ---------------------------------------------------------------------
+
+ procedure Set_Signal_Levels
+ (Port : Combo_Port;
+ eDP : Boolean;
+ Link : DP_Link;
+ Train_Set : DP_Info.Train_Set)
+ is
+ function Get_Buf_Trans_Table
+ (eDP : Boolean) return Buffer_Trans_DP_Array is
+ begin
+ if Config.Has_TGL_Buffer_Translations then
+ if eDP then
+ if Link.Bandwidth > DP_Bandwidth_5_4 then
+ return TGL_Buffer_Trans_DP_HBR2_EDP_HBR3;
+ else
+ return TGL_Buffer_Trans_DP_HBR;
+ end if;
+ else
+ if Link.Bandwidth > DP_Bandwidth_2_7 then
+ if Config.Is_LP then
+ return TGL_Buffer_Trans_DP_HBR2_U_Y;
+ else
+ return TGL_Buffer_Trans_DP_HBR2;
+ end if;
+ else
+ return TGL_Buffer_Trans_DP_HBR;
+ end if;
+ end if;
+ else
+ if eDP then
+ if Link.Bandwidth > DP_Bandwidth_5_4 then
+ return ADL_Buffer_Trans_EDP_HBR3;
+ else
+ return ADL_Buffer_Trans_DP_HBR; -- EDP_HBR2 ?
+ end if;
+ else
+ if Link.Bandwidth > DP_Bandwidth_2_7 then
+ return ADL_Buffer_Trans_DP_HBR3;
+ else
+ return ADL_Buffer_Trans_DP_HBR;
+ end if;
+ end if;
+ end if;
+ end Get_Buf_Trans_Table;
+
+ function To_Buf_Trans_Index
+ (Set : DP_Info.Train_Set) return Buffer_Trans_DP_Range
+ is
+ begin
+ case Set.Voltage_Swing is
+ when DP_Info.VS_Level_0 =>
+ case Set.Pre_Emph is
+ when DP_Info.Emph_Level_0 => return 0;
+ when DP_Info.Emph_Level_1 => return 1;
+ when DP_Info.Emph_Level_2 => return 2;
+ when DP_Info.Emph_Level_3 => return 3;
+ end case;
+ when DP_Info.VS_Level_1 =>
+ case Set.Pre_Emph is
+ when DP_Info.Emph_Level_0 => return 4;
+ when DP_Info.Emph_Level_1 => return 5;
+ when DP_Info.Emph_Level_2 => return 6;
+ when others => return 0;
+ end case;
+ when DP_Info.VS_Level_2 =>
+ case Set.Pre_Emph is
+ when DP_Info.Emph_Level_0 => return 7;
+ when DP_Info.Emph_Level_1 => return 8;
+ when others => return 0;
+ end case;
+ when DP_Info.VS_Level_3 =>
+ case Set.Pre_Emph is
+ when DP_Info.Emph_Level_0 => return 9;
+ when others => return 0;
+ end case;
+ end case;
+ end To_Buf_Trans_Index;
+
+ Was_Enabled : Boolean;
+ Buf_Trans : Buffer_Trans;
+ Entry_Index : constant Buffer_Trans_DP_Range :=
+ To_Buf_Trans_Index (Train_Set);
+ begin
+ pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+ Registers.Is_Set_Mask
+ (Register => Port_Regs (Port).DDI_BUF_CTL,
+ Mask => DDI_BUF_CTL_BUFFER_ENABLE,
+ Result => Was_Enabled);
+
+ Buf_Trans := Get_Buf_Trans_Table (eDP) (Entry_Index);
+
+ Set_Vswing_And_Deemphasis
+ (Port,
+ Buf_Trans,
+ DP,
+ Lanes_Range (Lane_Count_As_Integer (Link.Lane_Count)));
+
+ if not Was_Enabled then
+ Power_Up_Lanes (Port, Lanes_Range (Lane_Count_As_Integer (Link.Lane_Count)));
+ end if;
+
+ Registers.Unset_And_Set_Mask
+ (Register => Port_Regs (Port).DDI_BUF_CTL,
+ Mask_Unset => DDI_BUF_CTL_TRANS_SELECT_MASK or
+ DDI_BUF_CTL_PORT_REVERSAL or
+ DDI_BUF_CTL_PORT_WIDTH_MASK,
+ Mask_Set => DDI_BUF_CTL_BUFFER_ENABLE or
+ DDI_BUF_CTL_PORT_WIDTH (Link.Lane_Count));
+ Registers.Posting_Read (Port_Regs (Port).DDI_BUF_CTL);
+
+ if not Was_Enabled then
+ Registers.Wait_Unset_Mask (Port_Regs (Port).DDI_BUF_CTL, DDI_BUF_CTL_IDLE_STATUS);
+ end if;
+ end Set_Signal_Levels;
+
+ ---------------------------------------------------------------------
+
+ procedure Enable_HDMI (Port : Combo_Port)
+ is
+ HDMI_Lane_Count : constant := 4;
+ begin
+ Set_Vswing_And_Deemphasis
+ (Port,
+ Buffer_Trans_HDMI (Buffer_Trans_HDMI'First),
+ HDMI,
+ HDMI_Lane_Count);
+
+ Power_Up_Lanes (Port, HDMI_Lane_Count);
+
+ Registers.Unset_And_Set_Mask
+ (Register => DDI_BUF_CTL (Port),
+ Mask_Unset => DDI_BUF_CTL_TRANS_SELECT_MASK or
+ DDI_BUF_CTL_PORT_REVERSAL or
+ DDI_BUF_CTL_PORT_WIDTH_MASK,
+ Mask_Set => DDI_BUF_CTL_BUFFER_ENABLE);
+
+ Registers.Wait_Unset_Mask
+ (Register => DDI_BUF_CTL (Port),
+ Mask => DDI_BUF_CTL_IDLE_STATUS);
+ end Enable_HDMI;
+
+end HW.GFX.GMA.Connectors.Combo_Phy;
diff --git a/common/tigerlake/hw-gfx-gma-connectors-combo_phy.ads b/common/tigerlake/hw-gfx-gma-connectors-combo_phy.ads
new file mode 100644
index 0000000..b5347a2
--- /dev/null
+++ b/common/tigerlake/hw-gfx-gma-connectors-combo_phy.ads
@@ -0,0 +1,27 @@
+--
+-- Copyright (C) 2022 Google, LLC
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA.DP_Info;
+
+private package HW.GFX.GMA.Connectors.Combo_Phy is
+
+ procedure Set_Signal_Levels
+ (Port : Combo_Port;
+ eDP : Boolean;
+ Link : DP_Link;
+ Train_Set : DP_Info.Train_Set);
+
+ procedure Enable_HDMI (Port : Combo_Port);
+
+end HW.GFX.GMA.Connectors.Combo_Phy;
diff --git a/common/tigerlake/hw-gfx-gma-connectors-tc.adb b/common/tigerlake/hw-gfx-gma-connectors-tc.adb
new file mode 100644
index 0000000..976c5f2
--- /dev/null
+++ b/common/tigerlake/hw-gfx-gma-connectors-tc.adb
@@ -0,0 +1,592 @@
+--
+-- Copyright (C) 2022 Google, LLC
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA.Config;
+with HW.GFX.GMA.Registers;
+with HW.GFX.DP_Info;
+with HW.GFX.GMA.PCode;
+
+with HW.Debug;
+with GNAT.Source_Info;
+
+use type HW.Word64;
+
+package body HW.GFX.GMA.Connectors.TC is
+
+ function HIP_INDEX_REG (P : USBC_Port) return Registers.Registers_Index
+ is (if P <= DDI_TC4
+ then Registers.HIP_INDEX_REG0
+ else Registers.HIP_INDEX_REG1);
+
+ function HIP_INDEX_VAL (P : USBC_Port; Val : Word32) return Word32 is
+ (case P is
+ when DDI_TC1 | DDI_TC3 | DDI_TC5 => Val * 2 ** 0,
+ when DDI_TC2 | DDI_TC4 | DDI_TC6 => Val * 2 ** 8);
+
+ type Port_Regs_Array is array (USBC_Port) of Registers.Registers_Index;
+ DKL_DP_MODE : constant Port_Regs_Array :=
+ Port_Regs_Array'
+ (DDI_TC1 => Registers.DKL_DP_MODE_1,
+ DDI_TC2 => Registers.DKL_DP_MODE_2,
+ DDI_TC3 => Registers.DKL_DP_MODE_3,
+ DDI_TC4 => Registers.DKL_DP_MODE_4,
+ DDI_TC5 => Registers.DKL_DP_MODE_5,
+ DDI_TC6 => Registers.DKL_DP_MODE_6);
+
+ function DP_PIN_ASSIGNMENT_SHIFT (P : USBC_Port) return natural is
+ (case P is
+ when DDI_TC1 => 0,
+ when DDI_TC2 => 4,
+ when DDI_TC3 => 8,
+ when DDI_TC4 => 12,
+ when DDI_TC5 => 16,
+ when DDI_TC6 => 20);
+
+ DP_PIN_ASSIGNMENT_MASK : constant := 16#f#;
+
+ TGL_PCODE_TCCOLD : constant := 16#26#;
+ TCCOLD_BLOCK_REQ : constant := 16#00#;
+ TCCOLD_UNBLOCK_REQ : constant := 16#01#;
+ TCCOLD_BLOCK_RESULT_FAIL : constant := 16#01#;
+
+ type Fia_Regs_Record is record
+ PORT_TX_DFLEXDPMLE1 : Registers.Registers_Index;
+ PORT_TX_DFLEXDPSP : Registers.Registers_Index;
+ PORT_TX_DFLEXDPPMS : Registers.Registers_Index;
+ PORT_TX_DFLEXDPCSSS : Registers.Registers_Index;
+ PORT_TX_DFLEXPA1 : Registers.Registers_Index;
+ end record;
+
+ type Fia_Regs_Array is array (USBC_Port) of Fia_Regs_Record;
+ Fia_Regs : constant Fia_Regs_Array :=
+ Fia_Regs_Array'
+ (DDI_TC1 =>
+ (Registers.PORT_TX_DFLEXDPMLE1_FIA1,
+ Registers.PORT_TX_DFLEXDPSP_FIA1,
+ Registers.PORT_TX_DFLEXDPPMS_FIA1,
+ Registers.PORT_TX_DFLEXDPCSSS_FIA1,
+ Registers.PORT_TX_DFLEXPA1_FIA1),
+ DDI_TC2 =>
+ (Registers.PORT_TX_DFLEXDPMLE1_FIA1,
+ Registers.PORT_TX_DFLEXDPSP_FIA1,
+ Registers.PORT_TX_DFLEXDPPMS_FIA1,
+ Registers.PORT_TX_DFLEXDPCSSS_FIA1,
+ Registers.PORT_TX_DFLEXPA1_FIA1),
+ DDI_TC3 =>
+ (Registers.PORT_TX_DFLEXDPMLE1_FIA2,
+ Registers.PORT_TX_DFLEXDPSP_FIA2,
+ Registers.PORT_TX_DFLEXDPPMS_FIA2,
+ Registers.PORT_TX_DFLEXDPCSSS_FIA2,
+ Registers.PORT_TX_DFLEXPA1_FIA2),
+ DDI_TC4 =>
+ (Registers.PORT_TX_DFLEXDPMLE1_FIA2,
+ Registers.PORT_TX_DFLEXDPSP_FIA2,
+ Registers.PORT_TX_DFLEXDPPMS_FIA2,
+ Registers.PORT_TX_DFLEXDPCSSS_FIA2,
+ Registers.PORT_TX_DFLEXPA1_FIA2),
+ DDI_TC5 =>
+ (Registers.PORT_TX_DFLEXDPMLE1_FIA3,
+ Registers.PORT_TX_DFLEXDPSP_FIA3,
+ Registers.PORT_TX_DFLEXDPPMS_FIA3,
+ Registers.PORT_TX_DFLEXDPCSSS_FIA3,
+ Registers.PORT_TX_DFLEXPA1_FIA3),
+ DDI_TC6 =>
+ (Registers.PORT_TX_DFLEXDPMLE1_FIA3,
+ Registers.PORT_TX_DFLEXDPSP_FIA3,
+ Registers.PORT_TX_DFLEXDPPMS_FIA3,
+ Registers.PORT_TX_DFLEXDPCSSS_FIA3,
+ Registers.PORT_TX_DFLEXPA1_FIA3));
+
+ function Fia_Index (Port : USBC_Port) return natural
+ is (case Port is
+ when DDI_TC1 | DDI_TC3 | DDI_TC5 => 0,
+ when DDI_TC2 | DDI_TC4 | DDI_TC6 => 1);
+
+ function DFLEXDPMLE1_DPMLETC_MASK (Port : USBC_Port) return Word32 is
+ (Shift_Left (15, 4 * Fia_Index (Port)));
+ function DFLEXDPMLE1_DPMLETC_ML0 (Port : USBC_Port) return Word32 is
+ (Shift_Left (1, 4 * Fia_Index (Port)));
+ function DFLEXDPMLE1_DPMLETC_ML1_0 (Port : USBC_Port) return Word32 is
+ (Shift_Left (3, 4 * Fia_Index (Port)));
+ function DFLEXDPMLE1_DPMLETC_ML3 (Port : USBC_Port) return Word32 is
+ (Shift_Left (8, 4 * Fia_Index (Port)));
+ function DFLEXDPMLE1_DPMLETC_ML3_2 (Port : USBC_Port) return Word32 is
+ (Shift_Left (12, 4 * Fia_Index (Port)));
+ function DFLEXDPMLE1_DPMLETC_ML3_0 (Port : USBC_Port) return Word32 is
+ (Shift_Left (15, 4 * Fia_Index (Port)));
+ function DP_PHY_MODE_STATUS_COMPLETE (Port : USBC_Port) return Word32 is
+ (Shift_Left (1, Fia_Index (Port)));
+ function DP_PHY_MODE_STATUS_NOT_SAFE (Port : USBC_Port) return Word32 is
+ (Shift_Left (1, Fia_Index (Port)));
+ function TC_LIVE_STATE_TC (Port : USBC_Port) return Word32 is
+ (Shift_Left (1, Fia_Index (Port) * 8 + 5));
+ function DP_LANE_ASSIGNMENT_MASK (Port : USBC_Port) return Word32 is
+ (Shift_Left (16#f#, Fia_Index (Port) * 8));
+ function DP_LANE_ASSIGNMENT_SHIFT (Port : USBC_Port) return natural is
+ (Fia_Index (Port) * 8);
+
+ DDI_BUF_CTL_BUFFER_ENABLE : constant := 1 * 2 ** 31;
+ DDI_BUF_CTL_TRANS_SELECT_MASK : constant := 16#f# * 2 ** 24;
+ DDI_BUF_CTL_PORT_REVERSAL : constant := 1 * 2 ** 16;
+ DDI_BUF_CTL_PORT_WIDTH_MASK : constant := 7 * 2 ** 1;
+ DDI_BUF_CTL_PORT_WIDTH_1_LANE : constant := 0 * 2 ** 1;
+ DDI_BUF_CTL_PORT_WIDTH_2_LANES : constant := 1 * 2 ** 1;
+ DDI_BUF_CTL_PORT_WIDTH_4_LANES : constant := 3 * 2 ** 1;
+ DDI_BUF_CTL_IDLE_STATUS : constant := 1 * 2 ** 7;
+
+ type DDI_BUF_CTL_PORT_WIDTH_T is array (HW.GFX.DP_Lane_Count) of Word32;
+ DDI_BUF_CTL_PORT_WIDTH : constant DDI_BUF_CTL_PORT_WIDTH_T :=
+ DDI_BUF_CTL_PORT_WIDTH_T'
+ (HW.GFX.DP_Lane_Count_1 => DDI_BUF_CTL_PORT_WIDTH_1_LANE,
+ HW.GFX.DP_Lane_Count_2 => DDI_BUF_CTL_PORT_WIDTH_2_LANES,
+ HW.GFX.DP_Lane_Count_4 => DDI_BUF_CTL_PORT_WIDTH_4_LANES);
+ DDI_BUF_CTL : constant Port_Regs_Array :=
+ Port_Regs_Array'
+ (DDI_TC1 => Registers.DDI_BUF_CTL_USBC1,
+ DDI_TC2 => Registers.DDI_BUF_CTL_USBC2,
+ DDI_TC3 => Registers.DDI_BUF_CTL_USBC3,
+ DDI_TC4 => Registers.DDI_BUF_CTL_USBC4,
+ DDI_TC5 => Registers.DDI_BUF_CTL_USBC5,
+ DDI_TC6 => Registers.DDI_BUF_CTL_USBC6);
+
+ type Buffer_Trans is record
+ Vswing_Control : Word32;
+ Preshoot_Control : Word32;
+ Deemphasis_Control : Word32;
+ end record;
+
+ type Buffer_Trans_Range is new natural range 0 .. 9;
+ type Buffer_Trans_Array is array (Buffer_Trans_Range) of Buffer_Trans;
+ TGL_Buffer_Trans_DP_HBR2 : constant Buffer_Trans_Array :=
+ Buffer_Trans_Array'(
+ (16#7#, 16#0#, 16#00#),
+ (16#5#, 16#0#, 16#05#),
+ (16#2#, 16#0#, 16#0B#),
+ (16#0#, 16#0#, 16#19#),
+ (16#5#, 16#0#, 16#00#),
+ (16#2#, 16#0#, 16#08#),
+ (16#0#, 16#0#, 16#14#),
+ (16#2#, 16#0#, 16#00#),
+ (16#0#, 16#0#, 16#0B#),
+ (16#0#, 16#0#, 16#00#));
+ TGL_Buffer_Trans_DP_HBR : constant Buffer_Trans_Array :=
+ Buffer_Trans_Array'(
+ (16#7#, 16#0#, 16#00#),
+ (16#5#, 16#0#, 16#05#),
+ (16#2#, 16#0#, 16#0B#),
+ (16#0#, 16#0#, 16#18#),
+ (16#5#, 16#0#, 16#00#),
+ (16#2#, 16#0#, 16#08#),
+ (16#0#, 16#0#, 16#14#),
+ (16#2#, 16#0#, 16#00#),
+ (16#0#, 16#0#, 16#0B#),
+ (16#0#, 16#0#, 16#00#));
+ Buffer_Trans_HDMI : constant Buffer_Trans_Array :=
+ Buffer_Trans_Array'(
+ (16#7#, 16#0#, 16#0#),
+ (16#6#, 16#0#, 16#0#),
+ (16#4#, 16#0#, 16#0#),
+ (16#2#, 16#0#, 16#0#),
+ (16#0#, 16#0#, 16#0#),
+ (16#0#, 16#0#, 16#5#),
+ (16#0#, 16#0#, 16#6#),
+ (16#0#, 16#0#, 16#7#),
+ (16#0#, 16#0#, 16#8#),
+ (16#0#, 16#0#, 16#A#));
+ ADL_Buffer_Trans_DP_HBR2 : constant Buffer_Trans_Array :=
+ Buffer_Trans_Array'(
+ (16#7#, 16#0#, 16#00#),
+ (16#5#, 16#0#, 16#04#),
+ (16#2#, 16#0#, 16#0a#),
+ (16#0#, 16#0#, 16#18#),
+ (16#5#, 16#0#, 16#00#),
+ (16#2#, 16#0#, 16#06#),
+ (16#0#, 16#0#, 16#14#),
+ (16#2#, 16#0#, 16#00#),
+ (16#0#, 16#0#, 16#09#),
+ (16#0#, 16#0#, 16#00#));
+ ADL_Buffer_Trans_DP_HBR : constant Buffer_Trans_Array :=
+ Buffer_Trans_Array'(
+ (16#7#, 16#0#, 16#01#),
+ (16#5#, 16#0#, 16#06#),
+ (16#2#, 16#0#, 16#0b#),
+ (16#0#, 16#0#, 16#17#),
+ (16#5#, 16#0#, 16#00#),
+ (16#2#, 16#0#, 16#08#),
+ (16#0#, 16#0#, 16#14#),
+ (16#2#, 16#0#, 16#00#),
+ (16#0#, 16#0#, 16#0b#),
+ (16#0#, 16#0#, 16#00#));
+
+ type Vswing_Regs_Record is record
+ DKL_TX_PMD_LANE_SUS : Registers.Registers_Index;
+ DKL_TX_DPCNTL0 : Registers.Registers_Index;
+ DKL_TX_DPCNTL1 : Registers.Registers_Index;
+ DKL_TX_DPCNTL2 : Registers.Registers_Index;
+ end record;
+
+ type Vswing_Regs_Array is array (USBC_Port) of Vswing_Regs_Record;
+ Vswing_Regs : constant Vswing_Regs_Array :=
+ Vswing_Regs_Array'
+ (DDI_TC1 =>
+ (Registers.DKL_TX_PMD_LANE_SUS_1,
+ Registers.DKL_TX_DPCNTL0_1,
+ Registers.DKL_TX_DPCNTL1_1,
+ Registers.DKL_TX_DPCNTL2_1),
+ DDI_TC2 =>
+ (Registers.DKL_TX_PMD_LANE_SUS_2,
+ Registers.DKL_TX_DPCNTL0_2,
+ Registers.DKL_TX_DPCNTL1_2,
+ Registers.DKL_TX_DPCNTL2_2),
+ DDI_TC3 =>
+ (Registers.DKL_TX_PMD_LANE_SUS_3,
+ Registers.DKL_TX_DPCNTL0_3,
+ Registers.DKL_TX_DPCNTL1_3,
+ Registers.DKL_TX_DPCNTL2_3),
+ DDI_TC4 =>
+ (Registers.DKL_TX_PMD_LANE_SUS_4,
+ Registers.DKL_TX_DPCNTL0_4,
+ Registers.DKL_TX_DPCNTL1_4,
+ Registers.DKL_TX_DPCNTL2_4),
+ DDI_TC5 =>
+ (Registers.DKL_TX_PMD_LANE_SUS_5,
+ Registers.DKL_TX_DPCNTL0_5,
+ Registers.DKL_TX_DPCNTL1_5,
+ Registers.DKL_TX_DPCNTL2_5),
+ DDI_TC6 =>
+ (Registers.DKL_TX_PMD_LANE_SUS_6,
+ Registers.DKL_TX_DPCNTL0_6,
+ Registers.DKL_TX_DPCNTL1_6,
+ Registers.DKL_TX_DPCNTL2_6));
+
+ procedure Set_HIP_For_Port (P : USBC_Port; N : Natural) is
+ begin
+ Registers.Write (HIP_INDEX_REG (P), HIP_INDEX_VAL (P, Word32 (N)));
+ end Set_HIP_For_Port;
+
+ subtype Pin_Assignment_Type is natural range 0 .. 6;
+ procedure Get_Pin_Assignment
+ (P : in USBC_Port;
+ Assignment : out Pin_Assignment_Type)
+ is
+ Tmp : Word32;
+ A : Word32;
+ begin
+ Registers.Read (Fia_Regs (P).PORT_TX_DFLEXPA1, Tmp);
+ A := Shift_Right (Tmp, DP_PIN_ASSIGNMENT_SHIFT (P));
+ A := A and DP_PIN_ASSIGNMENT_MASK;
+
+ if natural (A) in Pin_Assignment_Type then
+ Assignment := Pin_Assignment_Type (A);
+ else
+ Assignment := Pin_Assignment_Type'First;
+ end if;
+ end Get_Pin_Assignment;
+
+ ---------------------------------------------------------------------
+
+ procedure Program_DP_Mode (P : USBC_Port; Lane_Count : Natural)
+ is
+ MG_DP_MODE_CFG_DP_X1_MODE : constant := 1 * 2 ** 6;
+ MG_DP_MODE_CFG_DP_X2_MODE : constant := 1 * 2 ** 7;
+ DP_X_MODE_MASK : constant Word32 :=
+ MG_DP_MODE_CFG_DP_X1_MODE or MG_DP_MODE_CFG_DP_X2_MODE;
+ Assignment : Pin_Assignment_Type;
+ Ln0, Ln1 : Word32;
+ begin
+ Set_HIP_For_Port (P, 0);
+ Registers.Read (DKL_DP_MODE (P), Ln0);
+ Set_HIP_For_Port (P, 1);
+ Registers.Read (DKL_DP_MODE (P), Ln1);
+
+ Ln0 := Ln0 and not DP_X_MODE_MASK;
+ Ln1 := Ln1 and not DP_X_MODE_MASK;
+
+ Get_Pin_Assignment (P, Assignment);
+ case Assignment is
+ when 0 =>
+ if Lane_Count = 1 then
+ Ln1 := Ln1 or MG_DP_MODE_CFG_DP_X1_MODE;
+ else
+ Ln0 := Ln0 or MG_DP_MODE_CFG_DP_X2_MODE;
+ Ln1 := Ln1 or MG_DP_MODE_CFG_DP_X2_MODE;
+ end if;
+ when 1 =>
+ if Lane_Count = 4 then
+ Ln0 := Ln0 or MG_DP_MODE_CFG_DP_X2_MODE;
+ Ln1 := Ln1 or MG_DP_MODE_CFG_DP_X2_MODE;
+ end if;
+ when 2 =>
+ if Lane_Count = 2 then
+ Ln0 := Ln0 or MG_DP_MODE_CFG_DP_X2_MODE;
+ Ln1 := Ln1 or MG_DP_MODE_CFG_DP_X2_MODE;
+ end if;
+ when 3 | 4 | 5 | 6 =>
+ if Lane_Count = 1 then
+ Ln0 := Ln0 or MG_DP_MODE_CFG_DP_X1_MODE;
+ Ln1 := Ln1 or MG_DP_MODE_CFG_DP_X1_MODE;
+ else
+ Ln0 := Ln0 or MG_DP_MODE_CFG_DP_X2_MODE;
+ Ln1 := Ln1 or MG_DP_MODE_CFG_DP_X2_MODE;
+ end if;
+ end case;
+
+ Set_HIP_For_Port (P, 0);
+ Registers.Unset_And_Set_Mask (DKL_DP_MODE (P), DP_X_MODE_MASK, Ln0);
+ Set_HIP_For_Port (P, 1);
+ Registers.Unset_And_Set_Mask (DKL_DP_MODE (P), DP_X_MODE_MASK, Ln1);
+ end Program_DP_Mode;
+
+ ---------------------------------------------------------------------
+
+ procedure TC_Cold_Request
+ (Request : in TC_Cold_Request_Type;
+ Success : out Boolean)
+ is
+ Result : Word64;
+ begin
+ for Try in 1 .. 3 loop
+ PCode.Mailbox_Read
+ (MBox => TGL_PCODE_TCCOLD,
+ Command => (if Request = Block
+ then TCCOLD_BLOCK_REQ
+ else TCCOLD_UNBLOCK_REQ),
+ Wait_Ready => True,
+ Reply => Result,
+ Success => Success);
+
+ if Success then
+ Success := (Result and TCCOLD_BLOCK_RESULT_FAIL) = 0;
+ end if;
+
+ exit when Success;
+
+ -- Wait 1 millisecond and try again
+ Time.U_Delay (1_000);
+ end loop;
+ end TC_Cold_Request;
+
+ ---------------------------------------------------------------------
+
+ procedure Set_Lane_Count (Port : USBC_Port; Lanes : Natural) is
+ begin
+ Registers.Unset_And_Set_Mask
+ (Register => Fia_Regs (Port).PORT_TX_DFLEXDPMLE1,
+ Mask_Unset => DFLEXDPMLE1_DPMLETC_MASK (Port),
+ Mask_Set => (case Lanes is
+ -- ML0 is not lane-reversed, ML3 is reverse
+ when 1 => DFLEXDPMLE1_DPMLETC_ML0 (Port),
+ -- ML1_0 is not reversed, ML3_2 is reverse
+ when 2 => DFLEXDPMLE1_DPMLETC_ML1_0 (Port),
+ -- symmetric
+ when 4 => DFLEXDPMLE1_DPMLETC_ML3_0 (Port),
+ when others => 0));
+ end Set_Lane_Count;
+
+ ---------------------------------------------------------------------
+
+ procedure Is_DP_Phy_Mode_Status_Complete
+ (Port : USBC_Port;
+ Success: out Boolean)
+ is
+ begin
+ Registers.Is_Set_Mask
+ (Register => Fia_Regs (Port).PORT_TX_DFLEXDPPMS,
+ Mask => DP_PHY_MODE_STATUS_COMPLETE (Port),
+ Result => Success);
+ end Is_DP_Phy_Mode_Status_Complete;
+
+ procedure Connect
+ (Port : in USBC_Port;
+ Success : out Boolean)
+ is
+ procedure Get_Lane_Assignment_Count
+ (Port : USBC_Port;
+ Lanes: out natural)
+ is
+ Lane_Mask : Word32;
+ Tmp : Word32;
+ begin
+ Registers.Read (Fia_Regs (Port).PORT_TX_DFLEXDPSP, Tmp);
+ Lane_Mask :=
+ Shift_Right (Tmp and DP_LANE_ASSIGNMENT_MASK (Port),
+ DP_LANE_ASSIGNMENT_SHIFT (Port));
+ Lanes :=
+ (case Lane_Mask is
+ when 1 | 2 | 4 | 8 => 1,
+ when 3 | 12 => 2,
+ when 15 => 4,
+ when others => 1);
+ end Get_Lane_Assignment_Count;
+ Lanes : natural;
+ begin
+ Is_DP_Phy_Mode_Status_Complete (Port, Success);
+ if not Success then
+ Debug.Put_Line ("DP PHY mode status not complete");
+ return;
+ end if;
+
+ Registers.Set_Mask
+ (Register => Fia_Regs (Port).PORT_TX_DFLEXDPCSSS,
+ Mask => DP_PHY_MODE_STATUS_NOT_SAFE (Port));
+
+ Registers.Is_Set_Mask
+ (Register => Fia_Regs (Port).PORT_TX_DFLEXDPSP,
+ Mask => TC_LIVE_STATE_TC (Port),
+ Result => Success);
+
+ if not Success then
+ pragma Debug (Debug.Put_Line ("Type-C Port is not connected."));
+ end if;
+
+ pragma Debug
+ (not Success, Debug.Put_Line ("Type-C Port is not connected."));
+
+ Get_Lane_Assignment_Count (Port, Lanes);
+ Set_Lane_Count (Port, Lanes);
+ end Connect;
+
+ ---------------------------------------------------------------------
+
+ procedure Disconnect (Port : USBC_Port) is
+ begin
+ Registers.Unset_Mask
+ (Register => Fia_Regs (Port).PORT_TX_DFLEXDPCSSS,
+ Mask => Word32 (Fia_Index (Port)));
+
+ Registers.Wait_Unset_mask
+ (Register => Fia_Regs (Port).PORT_TX_DFLEXDPPMS,
+ Mask => DP_PHY_MODE_STATUS_COMPLETE (Port));
+ end Disconnect;
+
+ ---------------------------------------------------------------------
+
+ procedure Set_Vswing_And_Deemphasis
+ (Port : USBC_Port;
+ Buf_Trans : Buffer_Trans)
+ is
+ -- Preshoot Coeff, Deemphasis Coeff, VSwing Control,
+ DPcnt_Mask : constant Word32 := 16#3_ff07#;
+ DPcnt_Val : constant Word32 :=
+ Buf_Trans.Vswing_Control or
+ Shift_Left (Buf_Trans.Deemphasis_Control, 8) or
+ Shift_Left (Buf_Trans.Preshoot_Control, 13);
+ DKL_TX_DP20BITMODE : constant := 1 * 2 ** 2;
+ begin
+ for Lane in 0 .. 1 loop
+ Set_HIP_For_Port (Port, Lane);
+ Registers.Write (Vswing_Regs (Port).DKL_TX_PMD_LANE_SUS, 0);
+ Registers.Unset_And_Set_Mask
+ (Vswing_Regs (Port).DKL_TX_DPCNTL0, DPcnt_Mask, DPcnt_Val);
+ Registers.Unset_And_Set_Mask
+ (Vswing_Regs (Port).DKL_TX_DPCNTL1, DPcnt_Mask, DPcnt_Val);
+ Registers.Unset_Mask
+ (Vswing_Regs (Port).DKL_TX_DPCNTL2, DKL_TX_DP20BITMODE);
+ end loop;
+
+ end Set_Vswing_And_Deemphasis;
+
+ ---------------------------------------------------------------------
+
+ procedure Set_Signal_Levels
+ (Port : USBC_Port;
+ Link : DP_Link;
+ Train_Set : DP_Info.Train_Set)
+ is
+ function To_Buf_Trans_Index
+ (Set : DP_Info.Train_Set) return Buffer_Trans_Range
+ is
+ begin
+ case Set.Voltage_Swing is
+ when DP_Info.VS_Level_0 =>
+ case Set.Pre_Emph is
+ when DP_Info.Emph_Level_0 => return 0;
+ when DP_Info.Emph_Level_1 => return 1;
+ when DP_Info.Emph_Level_2 => return 2;
+ when DP_Info.Emph_Level_3 => return 3;
+ end case;
+ when DP_Info.VS_Level_1 =>
+ case Set.Pre_Emph is
+ when DP_Info.Emph_Level_0 => return 4;
+ when DP_Info.Emph_Level_1 => return 5;
+ when DP_Info.Emph_Level_2 => return 6;
+ when others => return 0;
+ end case;
+ when DP_Info.VS_Level_2 =>
+ case Set.Pre_Emph is
+ when DP_Info.Emph_Level_0 => return 7;
+ when DP_Info.Emph_Level_1 => return 8;
+ when others => return 0;
+ end case;
+ when DP_Info.VS_Level_3 =>
+ case Set.Pre_Emph is
+ when DP_Info.Emph_Level_0 => return 9;
+ when others => return 0;
+ end case;
+ end case;
+ end To_Buf_Trans_Index;
+
+ Was_Enabled : Boolean;
+ Buf_Trans : Buffer_Trans;
+ Entry_Index : constant Buffer_Trans_Range :=
+ To_Buf_Trans_Index (Train_Set);
+ begin
+ pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+ Registers.Is_Set_Mask
+ (Register => DDI_BUF_CTL (Port),
+ Mask => DDI_BUF_CTL_BUFFER_ENABLE,
+ Result => Was_Enabled);
+
+ if Config.Has_TGL_Buffer_Translations then
+ if Link.Bandwidth > DP_Bandwidth_2_7 then
+ Buf_Trans := TGL_Buffer_Trans_DP_HBR2 (Entry_Index);
+ else
+ Buf_Trans := TGL_Buffer_Trans_DP_HBR (Entry_Index);
+ end if;
+ else
+ if Link.Bandwidth > DP_Bandwidth_2_7 then
+ Buf_Trans := ADL_Buffer_Trans_DP_HBR2 (Entry_Index);
+ else
+ Buf_Trans := ADL_Buffer_Trans_DP_HBR (Entry_Index);
+ end if;
+ end if;
+
+ Set_Vswing_And_Deemphasis (Port, Buf_Trans);
+
+ Registers.Unset_And_Set_Mask
+ (Register => DDI_BUF_CTL (Port),
+ Mask_Unset => DDI_BUF_CTL_TRANS_SELECT_MASK or
+ DDI_BUF_CTL_PORT_REVERSAL or
+ DDI_BUF_CTL_PORT_WIDTH_MASK,
+ Mask_Set => DDI_BUF_CTL_BUFFER_ENABLE or
+ DDI_BUF_CTL_PORT_WIDTH (Link.Lane_Count));
+ Registers.Posting_Read (DDI_BUF_CTL (Port));
+
+ if not Was_Enabled then
+ Registers.Wait_Unset_Mask (DDI_BUF_CTL (Port), DDI_BUF_CTL_IDLE_STATUS);
+ end if;
+ end Set_Signal_Levels;
+
+ procedure Enable_HDMI (Port : USBC_Port)
+ is
+ HDMI_Lane_Count : constant := 4;
+ Buf_Trans : constant Buffer_Trans :=
+ Buffer_Trans_HDMI (Buffer_Trans_HDMI'Last);
+ begin
+ Program_DP_Mode (Port, HDMI_Lane_Count);
+ Set_Vswing_And_Deemphasis (Port, Buf_Trans);
+ end Enable_HDMI;
+
+end HW.GFX.GMA.Connectors.TC;
diff --git a/common/tigerlake/hw-gfx-gma-connectors-tc.ads b/common/tigerlake/hw-gfx-gma-connectors-tc.ads
new file mode 100644
index 0000000..d169706
--- /dev/null
+++ b/common/tigerlake/hw-gfx-gma-connectors-tc.ads
@@ -0,0 +1,38 @@
+--
+-- Copyright (C) 2022 Google, LLC
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA.DP_Info;
+
+package HW.GFX.GMA.Connectors.TC is
+
+ procedure Connect (Port : in USBC_Port; Success: out Boolean);
+ procedure Disconnect (Port : USBC_Port);
+ procedure Program_DP_Mode (P : USBC_Port; Lane_Count : Natural);
+ procedure Set_Lane_Count (Port : USBC_Port; Lanes : Natural);
+ procedure Is_DP_Phy_Mode_Status_Complete
+ (Port : USBC_Port;
+ Success: out Boolean);
+ procedure Enable_HDMI (Port : USBC_Port);
+
+ procedure Set_Signal_Levels
+ (Port : USBC_Port;
+ Link : DP_Link;
+ Train_Set : DP_Info.Train_Set);
+
+ type TC_Cold_Request_Type is (Block, Unblock);
+ procedure TC_Cold_Request
+ (Request : in TC_Cold_Request_Type;
+ Success : out Boolean);
+
+end HW.GFX.GMA.Connectors.TC;
diff --git a/common/tigerlake/hw-gfx-gma-connectors.adb b/common/tigerlake/hw-gfx-gma-connectors.adb
index 73fafee..e02c7f2 100644
--- a/common/tigerlake/hw-gfx-gma-connectors.adb
+++ b/common/tigerlake/hw-gfx-gma-connectors.adb
@@ -12,60 +12,367 @@
-- GNU General Public License for more details.
--
+with HW.GFX.GMA.DP_Aux_Ch;
+with HW.GFX.DP_Training;
with HW.GFX.GMA.Config;
+with HW.GFX.GMA.Config_Helpers;
+with HW.GFX.GMA.Connectors.TC;
+with HW.GFX.GMA.Connectors.Combo_Phy;
+with HW.GFX.GMA.DP_Aux_Request;
+with HW.GFX.GMA.DP_Info;
with HW.GFX.GMA.Panel;
+with HW.GFX.GMA.Registers;
+with HW.GFX.GMA.Transcoder;
with HW.Debug;
with GNAT.Source_Info;
package body HW.GFX.GMA.Connectors is
- procedure Post_Reset_Off is
- begin
- pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
- end Post_Reset_Off;
+ type Pipe_Regs is array (Pipe_Index) of Registers.Registers_Index;
+ DP_TP_CTL : constant Pipe_Regs := Pipe_Regs'
+ (Primary => Registers.TGL_DP_TP_CTL_A,
+ Secondary => Registers.TGL_DP_TP_CTL_B,
+ Tertiary => Registers.TGL_DP_TP_CTL_C);
+ DP_TP_CTL_TRANSPORT_ENABLE : constant := 1 * 2 ** 31;
+ DP_TP_CTL_MODE_SST : constant := 0 * 2 ** 27;
+ DP_TP_CTL_MODE_MST : constant := 1 * 2 ** 27;
+ DP_TP_CTL_FORCE_ACT : constant := 1 * 2 ** 25;
+ DP_TP_CTL_ENHANCED_FRAME_ENABLE : constant := 1 * 2 ** 18;
+ DP_TP_CTL_LINK_TRAIN_MASK : constant := 7 * 2 ** 8;
+ DP_TP_CTL_LINK_TRAIN_PAT1 : constant := 0 * 2 ** 8;
+ DP_TP_CTL_LINK_TRAIN_PAT2 : constant := 1 * 2 ** 8;
+ DP_TP_CTL_LINK_TRAIN_IDLE : constant := 2 * 2 ** 8;
+ DP_TP_CTL_LINK_TRAIN_NORMAL : constant := 3 * 2 ** 8;
+ DP_TP_CTL_LINK_TRAIN_PAT3 : constant := 4 * 2 ** 8;
+ DP_TP_CTL_LINK_TRAIN_PAT4 : constant := 5 * 2 ** 8;
- procedure Initialize is
+ DP_TP_STATUS : constant Pipe_Regs := Pipe_Regs'
+ (Primary => Registers.TGL_DP_TP_STATUS_A,
+ Secondary => Registers.TGL_DP_TP_STATUS_B,
+ Tertiary => Registers.TGL_DP_TP_STATUS_C);
+ DP_TP_STATUS_MIN_IDLES_SENT : constant := 1 * 2 ** 25;
+
+ DDI_BUF_CTL_BUFFER_ENABLE : constant := 1 * 2 ** 31;
+ DDI_BUF_CTL_PORT_WIDTH_MASK : constant := 7 * 2 ** 1;
+ DDI_BUF_CTL_PORT_WIDTH_1_LANE : constant := 0 * 2 ** 1;
+ DDI_BUF_CTL_PORT_WIDTH_2_LANES : constant := 1 * 2 ** 1;
+ DDI_BUF_CTL_PORT_WIDTH_4_LANES : constant := 3 * 2 ** 1;
+ DDI_BUF_CTL_PORT_REVERSAL : constant := 1 * 2 ** 16;
+ DDI_BUF_CTL_IDLE_STATUS : constant := 1 * 2 ** 7;
+ DDI_BUF_CTL_TRANS_SELECT_MASK : constant := 16#f# * 2 ** 24;
+
+ type DDI_CLK_SEL_Shift_Array is array (Combo_Port) of Natural;
+ DDI_CLK_SEL_SHIFT : constant DDI_CLK_SEL_Shift_Array :=
+ DDI_CLK_SEL_Shift_Array'
+ (DIGI_A => 0,
+ DIGI_B => 2,
+ DIGI_C => 4);
+
+ type TGL_Digital_Port_Array is array (TGL_Digital_Port) of Word32;
+ DDI_CLK_OFF : constant TGL_Digital_Port_Array :=
+ TGL_Digital_Port_Array'
+ (DIGI_A => 1 * 2 ** 10,
+ DIGI_B => 1 * 2 ** 11,
+ DIGI_C => 1 * 2 ** 24,
+ DDI_TC1 => 1 * 2 ** 12,
+ DDI_TC2 => 1 * 2 ** 13,
+ DDI_TC3 => 1 * 2 ** 14,
+ DDI_TC4 => 1 * 2 ** 21,
+ DDI_TC5 => 1 * 2 ** 22,
+ DDI_TC6 => 1 * 2 ** 23,
+ others => 0);
+
+ type TGL_Digital_Port_Regs is array (TGL_Digital_Port) of Registers.Registers_Index;
+ DDI_BUF_CTL : constant TGL_Digital_Port_Regs :=
+ TGL_Digital_Port_Regs'
+ (DIGI_A => Registers.DDI_BUF_CTL_A,
+ DIGI_B => Registers.DDI_BUF_CTL_B,
+ DIGI_C => Registers.DDI_BUF_CTL_C,
+ DDI_TC1 => Registers.DDI_BUF_CTL_USBC1,
+ DDI_TC2 => Registers.DDI_BUF_CTL_USBC2,
+ DDI_TC3 => Registers.DDI_BUF_CTL_USBC3,
+ DDI_TC4 => Registers.DDI_BUF_CTL_USBC4,
+ DDI_TC5 => Registers.DDI_BUF_CTL_USBC5,
+ DDI_TC6 => Registers.DDI_BUF_CTL_USBC6,
+ others => Registers.DDI_BUF_CTL_A);
+
+ type DDI_CLK_SEL_Array is array (USBC_Port) of Registers.Registers_Index;
+ DDI_CLK_SEL : constant DDI_CLK_SEL_Array :=
+ DDI_CLK_SEL_Array'
+ (DDI_TC1 => Registers.DDI_CLK_SEL_USBC1,
+ DDI_TC2 => Registers.DDI_CLK_SEL_USBC2,
+ DDI_TC3 => Registers.DDI_CLK_SEL_USBC3,
+ DDI_TC4 => Registers.DDI_CLK_SEL_USBC4,
+ DDI_TC5 => Registers.DDI_CLK_SEL_USBC5,
+ DDI_TC6 => Registers.DDI_CLK_SEL_USBC6);
+
+ type Training_Port_Info is record
+ Port : TGL_Digital_Port;
+ Pipe : Pipe_Index;
+ eDP : Boolean;
+ end record;
+
+ function To_DP (Port_Info : Training_Port_Info) return DP_Port is
+ (case Port_Info.Port is
+ when DIGI_A => DP_A,
+ when DIGI_B => DP_B,
+ when DIGI_C => DP_C,
+ when DDI_TC1 => DP_D,
+ when DDI_TC2 => DP_E,
+ when DDI_TC3 => DP_F,
+ when DDI_TC4 => DP_G,
+ when DDI_TC5 => DP_H,
+ when DDI_TC6 => DP_I,
+ when others => DP_A);
+
+ ---------------------------------------------------------------------
+
+ procedure Off (Pipe : Pipe_Index; Port : TGL_Digital_Port)
+ is
+ Enabled : Boolean;
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
- end Initialize;
+ Registers.Is_Set_Mask
+ (Register => DDI_BUF_CTL (Port),
+ Mask => DDI_BUF_CTL_BUFFER_ENABLE,
+ Result => Enabled);
+
+ if Enabled then
+ Registers.Unset_Mask
+ (Register => DDI_BUF_CTL (Port),
+ Mask => DDI_BUF_CTL_BUFFER_ENABLE);
+ end if;
+
+ Registers.Unset_Mask
+ (Register => DP_TP_CTL (Pipe),
+ Mask => DP_TP_CTL_TRANSPORT_ENABLE);
+
+ if Enabled then
+ Registers.Wait_Set_Mask
+ (Register => DDI_BUF_CTL (Port),
+ Mask => DDI_BUF_CTL_IDLE_STATUS);
+ end if;
+
+ Registers.Set_Mask
+ (Register => Registers.DPCLKA_CFGCR0,
+ Mask => DDI_CLK_OFF (Port));
+ end Off;
+
+ procedure Off (Port_Info : Training_Port_Info) is
+ begin
+ Off (Port_Info.Pipe, Port_Info.Port);
+ end Off;
+
+ ---------------------------------------------------------------------
+
+ procedure Set_TP_CTL
+ (Pipe : Pipe_Index;
+ Link : DP_Link;
+ Pattern : DP_Info.Training_Pattern)
+ is
+ type DP_TP_CTL_LINK_TRAIN_ARRAY is
+ array (DP_Info.Training_Pattern) of Word32;
+ DP_TP_CTL_LINK_TRAIN : constant DP_TP_CTL_LINK_TRAIN_ARRAY :=
+ DP_TP_CTL_LINK_TRAIN_ARRAY'
+ (DP_Info.TP_1 => DP_TP_CTL_LINK_TRAIN_PAT1,
+ DP_Info.TP_2 => DP_TP_CTL_LINK_TRAIN_PAT2,
+ DP_Info.TP_3 => DP_TP_CTL_LINK_TRAIN_PAT3,
+ DP_Info.TP_Idle => DP_TP_CTL_LINK_TRAIN_IDLE,
+ DP_Info.TP_None => DP_TP_CTL_LINK_TRAIN_NORMAL);
+
+ DP_TP_CTL_Enhanced_Frame : Word32 := 0;
+ begin
+ if Link.Enhanced_Framing then
+ DP_TP_CTL_Enhanced_Frame := DP_TP_CTL_ENHANCED_FRAME_ENABLE;
+ end if;
+
+ Registers.Write
+ (Register => DP_TP_CTL (Pipe),
+ Value => DP_TP_CTL_TRANSPORT_ENABLE or
+ DP_TP_CTL_Enhanced_Frame or
+ DP_TP_CTL_MODE_SST or
+ DP_TP_CTL_LINK_TRAIN (Pattern));
+ Registers.Posting_Read (DP_TP_CTL (Pipe));
+ end Set_TP_CTL;
+
+ procedure Set_Training_Pattern
+ (Port_Info : Training_Port_Info;
+ Link : DP_Link;
+ Pattern : DP_Info.Training_Pattern)
+ is
+ use type DP_Info.Training_Pattern;
+ Pipe : Pipe_Index renames Port_Info.Pipe;
+ begin
+ if Pattern < DP_Info.TP_Idle then
+ Set_TP_CTL (Pipe, Link, Pattern);
+ else
+ Set_TP_CTL (Pipe, Link, DP_Info.TP_Idle);
+ Registers.Wait_Set_Mask
+ (Register => DP_TP_STATUS (Pipe),
+ Mask => DP_TP_STATUS_MIN_IDLES_SENT);
+ Set_TP_CTL (Pipe, Link, DP_Info.TP_None);
+ end if;
+ end Set_Training_Pattern;
+
+ ---------------------------------------------------------------------
+
+ pragma Warnings (GNATprove, Off, "unused variable ""Port_Info""",
+ Reason => "Needed for a common interface");
+ function Max_V_Swing
+ (Port_Info : Training_Port_Info) return DP_Info.DP_Voltage_Swing
+ is
+ (DP_Info.VS_Level_3);
+
+ function Max_Pre_Emph
+ (Port_Info : Training_Port_Info;
+ Train_Set : DP_Info.Train_Set)
+ return DP_Info.DP_Pre_Emph
+ is
+ begin
+ return
+ (case Train_Set.Voltage_Swing is
+ when DP_Info.VS_Level_0 => DP_Info.Emph_Level_3,
+ when DP_Info.VS_Level_1 => DP_Info.Emph_Level_2,
+ when DP_Info.VS_Level_2 => DP_Info.Emph_Level_1,
+ when others => DP_Info.Emph_Level_0);
+ end Max_Pre_Emph;
+ pragma Warnings (GNATprove, On, "unused variable ""Port_Info""");
+
+ ---------------------------------------------------------------------
+
+ procedure Set_Signal_Levels
+ (Port_Info : Training_Port_Info;
+ Link : DP_Link;
+ Train_Set : DP_Info.Train_Set)
+ is
+ Port : TGL_Digital_Port renames Port_Info.Port;
+ begin
+ if Port in Combo_Port then
+ Combo_Phy.Set_Signal_Levels (Port, Port_Info.eDP, Link, Train_Set);
+ elsif Port in USBC_Port then
+ TC.Set_Signal_Levels (Port, Link, Train_Set);
+ end if;
+ end Set_Signal_Levels;
+
+ ---------------------------------------------------------------------
+
+ procedure Map_PLL_To_Port
+ (Port : TGL_Digital_Port;
+ PLL_Hint : Word32)
+ is
+ CLOCK_SELECT_MASK : constant := 16#f000_0000#;
+ CLOCK_SELECT_TYPEC : constant := 16#8000_0000#;
+ DDI_CLK_SEL_MASK : constant := 3;
+ Clk_Sel_Shift : Natural;
+ begin
+ if Port in USBC_Port then
+ Registers.Unset_And_Set_Mask
+ (Register => DDI_CLK_SEL (Port),
+ Mask_Unset => CLOCK_SELECT_MASK,
+ Mask_Set => CLOCK_SELECT_TYPEC);
+ end if;
+
+ if Port in Combo_Port then
+ Clk_Sel_Shift := DDI_CLK_SEL_SHIFT (Port);
+ Registers.Unset_And_Set_Mask
+ (Register => Registers.DPCLKA_CFGCR0,
+ Mask_Unset => Shift_Left (DDI_CLK_SEL_MASK, Clk_Sel_Shift),
+ Mask_Set => Shift_Left (PLL_Hint, Clk_Sel_Shift));
+ Registers.Posting_Read (Registers.DPCLKA_CFGCR0);
+ end if;
+ end Map_PLL_To_Port;
procedure Pre_On
(Pipe : in Pipe_Index;
Port_Cfg : in Port_Config;
PLL_Hint : in Word32;
- Success : out Boolean) is
+ Success : out Boolean)
+ is
+ package Training is new DP_Training
+ (TPS3_Supported => True,
+ T => Training_Port_Info,
+ Aux_T => DP_Port,
+ Aux_Ch => HW.GFX.GMA.DP_Aux_Ch,
+ DP_Info => DP_Info,
+ To_Aux => To_DP,
+ Max_V_Swing => Max_V_Swing,
+ Max_Pre_Emph => Max_Pre_Emph,
+ Set_Pattern => Set_Training_Pattern,
+ Set_Signal_Levels => Set_Signal_Levels,
+ Off => Off);
+ Port : TGL_Digital_Port;
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
- Success := True;
+
+ if Port_Cfg.Port not in TGL_Digital_Port then
+ Success := False;
+ return;
+ end if;
+
+ Port := Port_Cfg.Port;
+ Map_PLL_To_Port (Port, PLL_Hint);
+
+ Registers.Unset_Mask
+ (Register => Registers.DPCLKA_CFGCR0,
+ Mask => DDI_CLK_OFF (Port));
+
+ if Port_Cfg.Display = DP then
+ if Port in USBC_Port then
+ TC.Program_DP_Mode
+ (Port, Natural (Lane_Count_As_Integer (Port_Cfg.DP.Lane_Count)));
+ end if;
+ Transcoder.Enable_Pipe_Clock (Pipe, Port_Cfg);
+ Transcoder.Configure (Pipe, Port_Cfg, False);
+
+ Training.Train_DP
+ (Port => (Port, Pipe, eDP => Port_Cfg.Is_eDP),
+ Link => Port_Cfg.DP,
+ Success => Success);
+ elsif Port_Cfg.Display = HDMI then
+ Transcoder.Enable_Pipe_Clock (Pipe, Port_Cfg);
+ Transcoder.Configure (Pipe, Port_Cfg, False);
+
+ Success := True;
+ if Port in Combo_Port then
+ Combo_Phy.Enable_HDMI (Port);
+ elsif Port in USBC_Port then
+ TC.Enable_HDMI (Port);
+ else
+ Success := False;
+ end if;
+ else
+ Success := False;
+ end if;
end Pre_On;
+ ---------------------------------------------------------------------
+
procedure Post_On
(Pipe : in Pipe_Index;
Port_Cfg : in Port_Config;
PLL_Hint : in Word32;
Success : out Boolean) is
begin
- pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
Panel.Backlight_On (Port_Cfg.Panel);
Success := True;
end Post_On;
procedure Pre_Off (Pipe : Pipe_Index; Port_Cfg : Port_Config) is
begin
- pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
Panel.Backlight_Off (Port_Cfg.Panel);
Panel.Off (Port_Cfg.Panel);
end Pre_Off;
procedure Post_Off (Pipe : Pipe_Index; Port_Cfg : Port_Config) is
begin
- pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+ if Port_Cfg.Port in Combo_Port then
+ Off (Pipe, Port_Cfg.Port);
+ end if;
end Post_Off;
procedure Pre_All_Off is
begin
- pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
for P in Valid_Panels loop
Panel.Backlight_Off (P);
Panel.Off (P);
@@ -74,7 +381,29 @@
procedure Post_All_Off is
begin
- pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+ for Port in Combo_Port loop
+ Off (Pipe_Index'First, Port); -- pipe index is arbitrary
+ end loop;
end Post_All_Off;
+ pragma Warnings (GNATprove, Off, "subprogram ""Post_On"" has no effect",
+ Reason => "Not supported");
+ procedure Post_On (Pipe : Pipe_Index; Port_Cfg : Port_Config) is
+ begin
+ pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+ end Post_On;
+ pragma Warnings (GNATprove, On, "subprogram ""Post_On"" has no effect");
+
+ procedure Post_Reset_Off is
+ begin
+ for Port in Combo_Port loop
+ Off (Pipe_Index'First, Port);
+ end loop;
+ end Post_Reset_Off;
+
+ procedure Initialize is
+ begin
+ pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+ end Initialize;
+
end HW.GFX.GMA.Connectors;
diff --git a/common/tigerlake/hw-gfx-gma-power_and_clocks.adb b/common/tigerlake/hw-gfx-gma-power_and_clocks.adb
index 88e932d..099376a 100644
--- a/common/tigerlake/hw-gfx-gma-power_and_clocks.adb
+++ b/common/tigerlake/hw-gfx-gma-power_and_clocks.adb
@@ -19,6 +19,8 @@
with HW.GFX.GMA.PCode;
with HW.GFX.GMA.Registers;
with HW.GFX.GMA.Transcoder;
+with HW.GFX.GMA.Connectors;
+with HW.GFX.GMA.Connectors.TC;
use type HW.Word64;
@@ -222,6 +224,7 @@
procedure Pre_On (PD : Power_Domain)
is
DP_AUX_CH_CTL_TBT_IO : constant := 1 * 2 ** 11;
+ Success : Boolean;
begin
if PD in AUX_USBC_Domain then
-- Disable TBT IO mode for AUX
@@ -229,9 +232,20 @@
(Register => AUX_CTL_Regs (PD),
Mask => DP_AUX_CH_CTL_TBT_IO);
+ Connectors.TC.Connect (Aux_To_Port (PD), Success);
+ if not Success then
+ Debug.Put_Line ("Connection flow failed!");
+ end if;
end if;
end Pre_On;
+ procedure Pre_Off (PD : Power_Domain) is
+ begin
+ if PD in AUX_USBC_Domain then
+ Connectors.TC.Disconnect (Aux_To_Port (PD));
+ end if;
+ end Pre_Off;
+
procedure Post_On (PD : Power_Domain)
is
DKL_CMN_UC_DW_27_UC_HEALTH : constant := 1 * 2 ** 15;
@@ -801,9 +815,15 @@
procedure Power_Up (Old_Configs, New_Configs : Pipe_Configs)
is
+ Success : Boolean;
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+ Connectors.TC.TC_Cold_Request (Connectors.TC.Block, Success);
+ if not Success then
+ Debug.Put_Line ("Failed to unblock TCCOLD");
+ end if;
+
for PD in Power_Domain loop
if not Need_PD (PD, Old_Configs) and Need_PD (PD, New_Configs) then
PD_On (PD);
@@ -813,6 +833,7 @@
procedure Power_Down (Old_Configs, Tmp_Configs, New_Configs : Pipe_Configs)
is
+ Success : Boolean;
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
for PD in reverse Power_Domain loop
@@ -823,6 +844,10 @@
end if;
end loop;
+ Connectors.TC.TC_Cold_Request (Connectors.TC.Unblock, Success);
+ if not Success then
+ Debug.Put_Line ("Failed to unblock TCCOLD");
+ end if;
end Power_Down;
procedure Pre_All_Off is
--
To view, visit https://review.coreboot.org/c/libgfxinit/+/82144?usp=email
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Gerrit-Project: libgfxinit
Gerrit-Branch: cros
Gerrit-Change-Id: I908e8bef8451d21eecde9ce6defddc2b3df7f738
Gerrit-Change-Number: 82144
Gerrit-PatchSet: 1
Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com>
Gerrit-Attention: Nico Huber <nico.h(a)gmx.de>
Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com>
Gerrit-MessageType: newchange
1
0
[S] Change in libgfxinit[cros]: gma connectors: Add `Pipe' parameter to Pre_/Post_Off procedures
by Dinesh Gehlot (Code Review) 30 Apr '24
by Dinesh Gehlot (Code Review) 30 Apr '24
30 Apr '24
Attention is currently required from: Nico Huber.
Hello Nico Huber,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/libgfxinit/+/82143?usp=email
to review the following change.
Change subject: gma connectors: Add `Pipe' parameter to Pre_/Post_Off procedures
......................................................................
gma connectors: Add `Pipe' parameter to Pre_/Post_Off procedures
Change-Id: I01dbf3cae3dfef2130fa10116f70f23238c7a48c
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
M common/g45/hw-gfx-gma-connectors.adb
M common/haswell_shared/hw-gfx-gma-connectors.adb
M common/hw-gfx-gma-connectors.ads
M common/hw-gfx-gma.adb
M common/ironlake/hw-gfx-gma-connectors.adb
M common/tigerlake/hw-gfx-gma-connectors.adb
6 files changed, 14 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/43/82143/1
diff --git a/common/g45/hw-gfx-gma-connectors.adb b/common/g45/hw-gfx-gma-connectors.adb
index ff689bb..114fae3 100644
--- a/common/g45/hw-gfx-gma-connectors.adb
+++ b/common/g45/hw-gfx-gma-connectors.adb
@@ -69,7 +69,7 @@
----------------------------------------------------------------------------
- procedure Pre_Off (Port_Cfg : Port_Config)
+ procedure Pre_Off (Pipe : Pipe_Index; Port_Cfg : Port_Config)
is
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
@@ -78,7 +78,7 @@
Panel.Off (Port_Cfg.Panel);
end Pre_Off;
- procedure Post_Off (Port_Cfg : Port_Config)
+ procedure Post_Off (Pipe : Pipe_Index; Port_Cfg : Port_Config)
is
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
diff --git a/common/haswell_shared/hw-gfx-gma-connectors.adb b/common/haswell_shared/hw-gfx-gma-connectors.adb
index e81322e..b8a39ce 100644
--- a/common/haswell_shared/hw-gfx-gma-connectors.adb
+++ b/common/haswell_shared/hw-gfx-gma-connectors.adb
@@ -69,7 +69,7 @@
----------------------------------------------------------------------------
- procedure Pre_Off (Port_Cfg : Port_Config)
+ procedure Pre_Off (Pipe : Pipe_Index; Port_Cfg : Port_Config)
is
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
@@ -78,7 +78,7 @@
Panel.Off (Port_Cfg.Panel);
end Pre_Off;
- procedure Post_Off (Port_Cfg : Port_Config)
+ procedure Post_Off (Pipe : Pipe_Index; Port_Cfg : Port_Config)
is
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
diff --git a/common/hw-gfx-gma-connectors.ads b/common/hw-gfx-gma-connectors.ads
index a1d0d1e..d16f3a2 100644
--- a/common/hw-gfx-gma-connectors.ads
+++ b/common/hw-gfx-gma-connectors.ads
@@ -33,10 +33,10 @@
Port_Cfg : in Port_Config;
PLL_Hint : in Word32;
Success : out Boolean);
- pragma Warnings (GNATprove, On, "unused variable ""P*""");
- procedure Pre_Off (Port_Cfg : Port_Config);
- procedure Post_Off (Port_Cfg : Port_Config);
+ procedure Pre_Off (Pipe : Pipe_Index; Port_Cfg : Port_Config);
+ procedure Post_Off (Pipe : Pipe_Index; Port_Cfg : Port_Config);
+ pragma Warnings (GNATprove, On, "unused variable ""P*""");
procedure Pre_All_Off;
procedure Post_All_Off;
diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb
index c3073d3..6331020 100644
--- a/common/hw-gfx-gma.adb
+++ b/common/hw-gfx-gma.adb
@@ -200,7 +200,7 @@
if not Success then
Display_Controller.Off (Pipe);
- Connectors.Post_Off (Port_Cfg);
+ Connectors.Post_Off (Pipe, Port_Cfg);
end if;
end if;
@@ -241,9 +241,9 @@
Display_Controller.Legacy_VGA_Off;
end if;
- Connectors.Pre_Off (Port_Cfg);
+ Connectors.Pre_Off (Pipe, Port_Cfg);
Display_Controller.Off (Pipe);
- Connectors.Post_Off (Port_Cfg);
+ Connectors.Post_Off (Pipe, Port_Cfg);
PLLs.Free (Allocated_PLLs (Pipe));
end if;
diff --git a/common/ironlake/hw-gfx-gma-connectors.adb b/common/ironlake/hw-gfx-gma-connectors.adb
index 1c3a243..bfe3047 100644
--- a/common/ironlake/hw-gfx-gma-connectors.adb
+++ b/common/ironlake/hw-gfx-gma-connectors.adb
@@ -104,7 +104,7 @@
----------------------------------------------------------------------------
- procedure Pre_Off (Port_Cfg : Port_Config)
+ procedure Pre_Off (Pipe : Pipe_Index; Port_Cfg : Port_Config)
is
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
@@ -115,7 +115,7 @@
end if;
end Pre_Off;
- procedure Post_Off (Port_Cfg : Port_Config)
+ procedure Post_Off (Pipe : Pipe_Index; Port_Cfg : Port_Config)
is
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
diff --git a/common/tigerlake/hw-gfx-gma-connectors.adb b/common/tigerlake/hw-gfx-gma-connectors.adb
index 5e66b96..73fafee 100644
--- a/common/tigerlake/hw-gfx-gma-connectors.adb
+++ b/common/tigerlake/hw-gfx-gma-connectors.adb
@@ -51,14 +51,14 @@
Success := True;
end Post_On;
- procedure Pre_Off (Port_Cfg : Port_Config) is
+ procedure Pre_Off (Pipe : Pipe_Index; Port_Cfg : Port_Config) is
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
Panel.Backlight_Off (Port_Cfg.Panel);
Panel.Off (Port_Cfg.Panel);
end Pre_Off;
- procedure Post_Off (Port_Cfg : Port_Config) is
+ procedure Post_Off (Pipe : Pipe_Index; Port_Cfg : Port_Config) is
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
end Post_Off;
--
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Gerrit-Project: libgfxinit
Gerrit-Branch: cros
Gerrit-Change-Id: I01dbf3cae3dfef2130fa10116f70f23238c7a48c
Gerrit-Change-Number: 82143
Gerrit-PatchSet: 1
Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Attention: Nico Huber <nico.h(a)gmx.de>
Gerrit-MessageType: newchange
1
0
[XS] Change in libgfxinit[cros]: gma: Add `eDP' flag to Port_Config
by Dinesh Gehlot (Code Review) 30 Apr '24
by Dinesh Gehlot (Code Review) 30 Apr '24
30 Apr '24
Attention is currently required from: Nico Huber.
Hello Nico Huber,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/libgfxinit/+/82142?usp=email
to review the following change.
Change subject: gma: Add `eDP' flag to Port_Config
......................................................................
gma: Add `eDP' flag to Port_Config
Start with a simple check if the dedicated eDP port is used. In the
future, this might change if another port is used for eDP.
Change-Id: Idd40b4258c08ba88ec7b0ab631e683aba848f9c1
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
M common/hw-gfx-gma-config_helpers.adb
M common/hw-gfx-gma.ads
2 files changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/42/82142/1
diff --git a/common/hw-gfx-gma-config_helpers.adb b/common/hw-gfx-gma-config_helpers.adb
index 868d514..d91dfd2 100644
--- a/common/hw-gfx-gma-config_helpers.adb
+++ b/common/hw-gfx-gma-config_helpers.adb
@@ -218,6 +218,7 @@
Panel => To_Panel (Port),
Mode => Mode,
Is_FDI => Config.Is_FDI_Port (Port),
+ Is_eDP => Port = eDP,
FDI => Default_DP,
DP => Default_DP);
@@ -254,6 +255,7 @@
Panel => No_Panel,
Mode => Invalid_Mode,
Is_FDI => False,
+ Is_eDP => False,
FDI => Default_DP,
DP => Default_DP);
end if;
diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads
index 43e88e1..8ef2247 100644
--- a/common/hw-gfx-gma.ads
+++ b/common/hw-gfx-gma.ads
@@ -321,6 +321,7 @@
Panel : Panel_Control;
Mode : Mode_Type;
Is_FDI : Boolean;
+ Is_eDP : Boolean;
FDI : DP_Link;
DP : DP_Link;
end record;
--
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Gerrit-Change-Number: 82142
Gerrit-PatchSet: 1
Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Attention: Nico Huber <nico.h(a)gmx.de>
Gerrit-MessageType: newchange
1
0
[L] Change in libgfxinit[cros]: gma tgl: Add support for allocating PLLs
by Dinesh Gehlot (Code Review) 30 Apr '24
by Dinesh Gehlot (Code Review) 30 Apr '24
30 Apr '24
Attention is currently required from: Tim Wawrzynczak.
Hello Tim Wawrzynczak,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/libgfxinit/+/82141?usp=email
to review the following change.
Change subject: gma tgl: Add support for allocating PLLs
......................................................................
gma tgl: Add support for allocating PLLs
This patch adds support for allocating both combo PHY PLLs and USB
Type-C PLLs for Tiger Lake.
Verified Combo PHY (HDMI, eDP) and Type-C (DP Alt mode) on
Google/delbin.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: I9dd7e0d0180f70d73eb50d7e58718261e5e74071
---
M common/hw-gfx-gma-config.ads.template
M common/tigerlake/Makefile.inc
A common/tigerlake/hw-gfx-gma-plls-combo_phy.adb
A common/tigerlake/hw-gfx-gma-plls-combo_phy.ads
A common/tigerlake/hw-gfx-gma-plls-dkl.adb
A common/tigerlake/hw-gfx-gma-plls-dkl.ads
M common/tigerlake/hw-gfx-gma-plls.adb
M common/tigerlake/hw-gfx-gma-plls.ads
8 files changed, 930 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/41/82141/1
diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template
index b7af801..e168144 100644
--- a/common/hw-gfx-gma-config.ads.template
+++ b/common/hw-gfx-gma-config.ads.template
@@ -261,6 +261,7 @@
Has_Broadwell_CDClk : <hswbool> := CPU_Broadwell;
Can_Switch_CDClk : <hswbool> := Broadwell_On;
Has_Fractional_RawClk : <genbool> := Cannon_Point_On;
+ Has_New_Type_C_PLL_Enable : <tglbool> := Alderlake_On;
----------- DDI: -------------
End_EDP_Training_Late : <genbool> := Gen_Haswell;
diff --git a/common/tigerlake/Makefile.inc b/common/tigerlake/Makefile.inc
index e9ed51f..86ed920 100644
--- a/common/tigerlake/Makefile.inc
+++ b/common/tigerlake/Makefile.inc
@@ -6,3 +6,7 @@
gfxinit-y += hw-gfx-gma-port_detect.adb
gfxinit-y += hw-gfx-gma-plls.adb
gfxinit-y += hw-gfx-gma-plls.ads
+gfxinit-y += hw-gfx-gma-plls-combo_phy.adb
+gfxinit-y += hw-gfx-gma-plls-combo_phy.ads
+gfxinit-y += hw-gfx-gma-plls-dkl.adb
+gfxinit-y += hw-gfx-gma-plls-dkl.ads
diff --git a/common/tigerlake/hw-gfx-gma-plls-combo_phy.adb b/common/tigerlake/hw-gfx-gma-plls-combo_phy.adb
new file mode 100644
index 0000000..4e149b6
--- /dev/null
+++ b/common/tigerlake/hw-gfx-gma-plls-combo_phy.adb
@@ -0,0 +1,351 @@
+--
+-- Copyright (C) 2022 Google, LLC
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA.Config;
+with HW.GFX.GMA.Registers;
+with HW.GFX.GMA.Power_And_Clocks;
+
+package body HW.GFX.GMA.PLLs.Combo_Phy is
+
+ subtype HDMI_Clock_Range is Frequency_Type range
+ 25_000_000 .. Config.HDMI_Max_Clock_24bpp;
+ subtype DCO_Range is Pos64 range
+ 7_998_000_000 .. 10_000_000_000;
+
+ type PLL_Regs_Record is record
+ DPLL_ENABLE : Registers.Registers_Index;
+ DPLL_CFGCR0 : Registers.Registers_Index;
+ DPLL_CFGCR1 : Registers.Registers_Index;
+ DPLL_SSC : Registers.Registers_Index;
+ end record;
+ type PLL_Regs_Array is array (Combo_DPLLs) of PLL_Regs_Record;
+ PLL_Regs : constant PLL_Regs_Array :=
+ PLL_Regs_Array'
+ (DPLL0 =>
+ (Registers.DPLL_0_ENABLE,
+ Registers.DPLL_0_CFGCR0,
+ Registers.DPLL_0_CFGCR1,
+ Registers.DPLL_0_SSC),
+ DPLL1 =>
+ (Registers.DPLL_1_ENABLE,
+ Registers.DPLL_1_CFGCR0,
+ Registers.DPLL_1_CFGCR1,
+ Registers.DPLL_1_SSC));
+
+ DPLL_ENABLE_PLL_ENABLE : constant := 1 * 2 ** 31;
+ DPLL_ENABLE_PLL_LOCK : constant := 1 * 2 ** 30;
+ DPLL_ENABLE_POWER_ENABLE : constant := 1 * 2 ** 27;
+ DPLL_ENABLE_POWER_STATE : constant := 1 * 2 ** 26;
+ DPLL_SSC_DP : constant := 16#200#;
+
+ subtype PDiv_Range is Positive range 1 .. 8;
+ subtype QDiv_Range is Natural range 0 .. 255;
+ subtype KDiv_Range is Positive range 1 .. 5;
+
+ type PLL_Params is record
+ DCO_Integer : Word32;
+ DCO_Fraction : Word32;
+ PDiv : PDiv_Range;
+ KDiv : KDiv_Range;
+ QDiv_Mode : natural range 0 .. 1;
+ QDiv_Ratio : QDiv_Range;
+ end record;
+
+ type DP_PLL_Params_Array is array (DP_Bandwidth) of PLL_Params;
+
+ PLL_Params_19_2MHz : constant DP_PLL_Params_Array := DP_PLL_Params_Array'
+ (DP_Bandwidth_5_4 =>
+ (DCO_Integer => 16#1a5#,
+ DCO_Fraction => 16#7000#,
+ PDiv => 2,
+ KDiv => 1,
+ QDiv_Mode => 0,
+ QDiv_Ratio => 0),
+ DP_Bandwidth_2_7 =>
+ (DCO_Integer => 16#1a5#,
+ DCO_Fraction => 16#7000#,
+ PDiv => 2,
+ KDiv => 2,
+ QDiv_Mode => 0,
+ QDiv_Ratio => 0),
+ DP_Bandwidth_1_62 =>
+ (DCO_Integer => 16#1a5#,
+ DCO_Fraction => 16#7000#,
+ PDiv => 4,
+ KDiv => 2,
+ QDiv_Mode => 0,
+ QDiv_Ratio => 0));
+
+ PLL_Params_24MHz : constant DP_PLL_Params_Array := DP_PLL_Params_Array'
+ (DP_Bandwidth_5_4 =>
+ (DCO_Integer => 16#151#,
+ DCO_Fraction => 16#4000#,
+ PDiv => 2,
+ KDiv => 1,
+ QDiv_Mode => 0,
+ QDiv_Ratio => 0),
+ DP_Bandwidth_2_7 =>
+ (DCO_Integer => 16#151#,
+ DCO_Fraction => 16#4000#,
+ PDiv => 2,
+ KDiv => 2,
+ QDiv_Mode => 0,
+ QDiv_Ratio => 0),
+ DP_Bandwidth_1_62 =>
+ (DCO_Integer => 16#151#,
+ DCO_Fraction => 16#4000#,
+ PDiv => 2,
+ KDiv => 2,
+ QDiv_Mode => 0,
+ QDiv_Ratio => 0));
+
+ procedure Calc_DP_PLL_Dividers
+ (Bandwidth : in DP_Bandwidth;
+ Params : out PLL_Params)
+ is
+ Refclk : Frequency_Type;
+ begin
+ Power_And_Clocks.Get_Refclk (Refclk);
+ if Refclk = 24_000_000 then
+ Params := PLL_Params_24MHz (Bandwidth);
+ else
+ Params := PLL_Params_19_2MHz (Bandwidth);
+ end if;
+ end Calc_DP_PLL_Dividers;
+
+ procedure Calc_HDMI_PLL_Dividers
+ (Dotclock : in Frequency_Type;
+ Params : out PLL_Params;
+ Success : out Boolean)
+ is
+ subtype Div_Range is Pos64 range 2 .. 102;
+ subtype Candidate_Index is Positive range 1 .. 46;
+ type Candidate_Array is array (Candidate_Index) of Div_Range;
+ Candidates : constant Candidate_Array := Candidate_Array'
+ (2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 24, 28, 30, 32, 36, 40, 42, 44,
+ 48, 50, 52, 54, 56, 60, 64, 66, 68, 70, 72, 76, 78, 80, 84, 88, 90,
+ 92, 96, 98, 100, 102, 3, 5, 7, 9, 15, 21);
+ AFE_Clk : constant Int64 := Dotclock * 5;
+ DCO_Mid : constant Int64 := (DCO_Range'First + DCO_Range'Last) / 2;
+ Best_DCO_Centrality : Int64 := Frequency_Type'Last;
+ Best_Div_Index : Candidate_Index := Candidate_Index'First;
+ Best_Div : Div_Range;
+ Best_DCO : DCO_Range := DCO_Range'First;
+ DCO_Found : Boolean := False;
+ PDiv : PDiv_Range := PDiv_Range'First;
+ QDiv : QDiv_Range := QDiv_Range'First;
+ KDiv : KDiv_Range := KDiv_Range'First;
+ Refclk_Freq : Power_And_Clocks.Refclk_Range;
+ begin
+ Success := False;
+ Params := (DCO_Integer => 0,
+ DCO_Fraction => 0,
+ PDiv => PDiv,
+ KDiv => KDiv,
+ QDiv_Mode => 0,
+ QDiv_Ratio => QDiv_Range'First);
+ for Index in Candidate_Index loop
+ pragma Loop_Invariant
+ (Best_DCO >= DCO_Range'First and Best_DCO <= DCO_Range'Last);
+ declare
+ DCO : constant Int64 := AFE_Clk * Candidates(Index);
+ DCO_Centrality : constant Int64 := abs (DCO - DCO_Mid);
+ begin
+ if DCO <= DCO_Range'Last and DCO >= DCO_Range'First and
+ DCO_Centrality < Best_DCO_Centrality
+ then
+ DCO_Found := True;
+ Best_DCO_Centrality := DCO_Centrality;
+ Best_Div_Index := Index;
+ Best_DCO := DCO;
+ end if;
+ end;
+ end loop;
+
+ if not DCO_Found then
+ return;
+ end if;
+
+ Best_Div := Candidates(Best_Div_Index);
+ if Best_Div mod 2 = 0 then
+ pragma Assert (Best_Div > 1);
+ if Best_Div = 2 then
+ PDiv := 2;
+ QDiv := 1;
+ KDiv := 1;
+ elsif Best_Div mod 4 = 0 then
+ PDiv := 2;
+ QDiv := QDiv_Range (Best_Div / 4);
+ KDiv := 2;
+ elsif Best_Div mod 6 = 0 then
+ PDiv := 3;
+ QDiv := QDiv_Range (Best_Div / 6);
+ KDiv := 2;
+ elsif Best_Div mod 5 = 0 then
+ PDiv := 5;
+ QDiv := QDiv_Range (Best_Div / 10);
+ KDiv := 2;
+ elsif Best_Div mod 14 = 0 then
+ PDiv := 7;
+ QDiv := QDiv_Range (Best_Div / 14);
+ KDiv := 2;
+ end if;
+ else
+ if Best_Div = 3 or Best_Div = 5 or Best_Div = 7 then
+ PDiv := PDiv_Range (Best_Div);
+ QDiv := 1;
+ KDiv := 1;
+ else
+ PDiv := PDiv_Range (Best_Div / 3);
+ QDiv := 1;
+ KDiv := 3;
+ end if;
+ end if;
+ Params.KDiv := (case KDiv is
+ when 1 => 1,
+ when 2 => 2,
+ when 3 => 4,
+ when others => 1);
+ Params.PDiv := (case PDiv is
+ when 2 => 1,
+ when 3 => 2,
+ when 5 => 4,
+ when 7 => 8,
+ when others => 1);
+ Params.QDiv_Ratio := QDiv;
+ Params.QDiv_Mode := (if QDiv = 1 then 0 else 1);
+ Power_And_Clocks.Get_Refclk (Refclk_Freq);
+
+ -- DPLL will auto-divide by 2 if refclk is 38.4 MHz
+ if Refclk_Freq = 38_400_000 then
+ Refclk_Freq := 19_200_000;
+ end if;
+
+ declare
+ DCO : constant Int64 :=
+ (Best_DCO / 1_000) * (2 ** 15) / (Refclk_Freq / 1_000);
+ begin
+ Params.DCO_Integer := Word32 (DCO / (2 ** 15));
+ Params.DCO_Fraction := Word32 (DCO) and 16#7fff#;
+ end;
+
+ Success := True;
+ end Calc_HDMI_PLL_Dividers;
+
+ procedure On
+ (PLL : in Combo_DPLLs;
+ Port_Cfg : in Port_Config;
+ Success : out Boolean)
+ is
+ Params : PLL_Params;
+ Refclk : Frequency_Type;
+ begin
+ if Port_Cfg.Display = DP then
+ Calc_DP_PLL_Dividers (Port_Cfg.DP.Bandwidth, Params);
+ Success := True;
+ else
+ if Port_Cfg.Mode.Dotclock not in HDMI_Clock_Range then
+ Debug.Put_Line ("Unsupported HDMI Pixel clock");
+ Success := False;
+ return;
+ end if;
+ declare
+ Color_Depth : constant Int64 := Port_Cfg.Mode.BPC * 3;
+ Pll_Freq : constant Frequency_Type := Color_Depth * Port_Cfg.Mode.Dotclock / 24;
+ begin
+ Calc_HDMI_PLL_Dividers (Pll_Freq, Params, Success);
+ end;
+ end if;
+
+ if not Success then
+ Debug.Put_Line ("Failed to calculate PLL dividers!");
+ return;
+ end if;
+
+ -- Display WA #22010492432: ehl, tgl, adl-p
+ -- Program half of the nominal DCO divider fraction value
+ -- for 38.4 MHz refclk
+ Power_And_Clocks.Get_Refclk (Refclk);
+ if Refclk = 38_400_000 then
+ Params.DCO_Fraction := Shift_Right (Params.DCO_Fraction, 1);
+ end if;
+
+ Registers.Set_Mask
+ (Register => PLL_Regs (PLL).DPLL_ENABLE,
+ Mask => DPLL_ENABLE_POWER_ENABLE);
+ Registers.Wait_Set_Mask
+ (Register => PLL_Regs (PLL).DPLL_ENABLE,
+ Mask => DPLL_ENABLE_POWER_STATE,
+ Success => Success);
+
+ if not Success then
+ Debug.Put_Line ("Failed to enable PLL!");
+ return;
+ end if;
+
+ -- Configure DPLL_SSC
+ Registers.Write
+ (Register => PLL_Regs (PLL).DPLL_SSC,
+ Value => (if Port_Cfg.Display = DP then DPLL_SSC_DP else 0));
+
+ Registers.Write
+ (Register => PLL_Regs (PLL).DPLL_CFGCR0,
+ Value => Shift_Left (Params.DCO_Fraction, 10) or
+ Params.DCO_Integer);
+
+ Registers.Write
+ (Register => PLL_Regs (PLL).DPLL_CFGCR1,
+ Value => Shift_Left (Word32 (Params.QDiv_Ratio), 10) or
+ Shift_Left (Word32 (Params.QDiv_Mode), 9) or
+ Shift_left (Word32 (Params.KDiv), 6) or
+ Shift_Left (Word32 (Params.PDiv), 2));
+ Registers.Posting_Read(PLL_Regs (PLL).DPLL_CFGCR1);
+
+ -- Enable DPLL
+ Registers.Set_Mask
+ (Register => PLL_Regs (PLL).DPLL_ENABLE,
+ Mask => DPLL_ENABLE_PLL_ENABLE);
+ -- Wait for PLL Lock status
+ Registers.Wait_Set_Mask
+ (Register => PLL_Regs (PLL).DPLL_ENABLE,
+ Mask => DPLL_ENABLE_PLL_LOCK,
+ Success => Success);
+ end On;
+
+ procedure Free (PLL : Combo_DPLLs)
+ is
+ begin
+ Registers.Unset_Mask
+ (Register => PLL_Regs (PLL).DPLL_ENABLE,
+ Mask => DPLL_ENABLE_PLL_ENABLE);
+ Registers.Wait_Unset_Mask
+ (Register => PLL_Regs (PLL).DPLL_ENABLE,
+ Mask => DPLL_ENABLE_PLL_LOCK);
+
+ Registers.Unset_Mask
+ (Register => PLL_Regs (PLL).DPLL_ENABLE,
+ Mask => DPLL_ENABLE_POWER_ENABLE);
+ Registers.Wait_Unset_Mask
+ (Register => PLL_Regs (PLL).DPLL_ENABLE,
+ Mask => DPLL_ENABLE_POWER_STATE);
+ end Free;
+
+ procedure All_Off is
+ begin
+ for PLL in Combo_DPLLs loop
+ Free (PLL);
+ end loop;
+ end All_Off;
+
+end HW.GFX.GMA.PLLs.Combo_Phy;
diff --git a/common/tigerlake/hw-gfx-gma-plls-combo_phy.ads b/common/tigerlake/hw-gfx-gma-plls-combo_phy.ads
new file mode 100644
index 0000000..8857b8c
--- /dev/null
+++ b/common/tigerlake/hw-gfx-gma-plls-combo_phy.ads
@@ -0,0 +1,33 @@
+--
+-- Copyright (C) 2022 Google, LLC
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.Debug;
+with GNAT.Source_Info;
+
+private package HW.GFX.GMA.PLLs.Combo_Phy is
+
+ procedure On
+ (PLL : in Combo_DPLLs;
+ Port_Cfg : in Port_Config;
+ Success : out Boolean);
+
+ procedure Free (PLL : Combo_DPLLs);
+
+ procedure All_Off;
+
+ type Value_Array is array (Combo_DPLLs) of Word32;
+ Register_Value : constant Value_Array := Value_Array'
+ (DPLL0 => 0, DPLL1 => 1);
+
+end HW.GFX.GMA.PLLs.Combo_Phy;
diff --git a/common/tigerlake/hw-gfx-gma-plls-dkl.adb b/common/tigerlake/hw-gfx-gma-plls-dkl.adb
new file mode 100644
index 0000000..cca7f24
--- /dev/null
+++ b/common/tigerlake/hw-gfx-gma-plls-dkl.adb
@@ -0,0 +1,409 @@
+--
+-- Copyright (C) 2022 Google, LLC
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA.Config;
+with HW.GFX.GMA.Registers;
+with HW.GFX.GMA.Power_And_Clocks;
+
+package body HW.GFX.GMA.PLLs.DKL is
+
+ use type HW.Word64;
+
+ subtype Frequency_KHz is Pos64
+ range (Frequency_Type'First / 1_000) .. (Frequency_Type'Last / 1_000);
+ subtype DCO_Range_KHz is Pos64 range 7_992_000 .. 10_000_000;
+
+ DPLL_ENABLE_PLL_ENABLE : constant := 1 * 2 ** 31;
+ DPLL_ENABLE_PLL_LOCK : constant := 1 * 2 ** 30;
+ DPLL_ENABLE_POWER_ENABLE : constant := 1 * 2 ** 27;
+ DPLL_ENABLE_POWER_STATE : constant := 1 * 2 ** 26;
+
+ function HIP_INDEX_REG (P : DKL_DPLLs) return Registers.Registers_Index
+ is (if P <= TCPLL4
+ then Registers.HIP_INDEX_REG0
+ else Registers.HIP_INDEX_REG1);
+
+ function HIP_INDEX_VAL (P : DKL_DPLLs; Val : Word32) return Word32 is
+ (case P is
+ when TCPLL1 => Val * 2 ** 0,
+ when TCPLL2 => Val * 2 ** 8,
+ when TCPLL3 => Val * 2 ** 16,
+ when TCPLL4 => Val * 2 ** 24,
+ when TCPLL5 => Val * 2 ** 0,
+ when TCPLL6 => Val * 2 ** 8);
+
+ function DKL_PLL_ENABLE (P : DKL_DPLLs) return Registers.Registers_Index
+ is
+ type PLL_Enable_Regs_Array is array (DKL_DPLLs) of Registers.Registers_Index;
+ DKL_ENABLE : constant PLL_Enable_Regs_Array :=
+ PLL_Enable_Regs_Array'
+ (TCPLL1 => Registers.MGPLL1_ENABLE,
+ TCPLL2 => Registers.MGPLL2_ENABLE,
+ TCPLL3 => Registers.MGPLL3_ENABLE,
+ TCPLL4 => Registers.MGPLL4_ENABLE,
+ TCPLL5 => Registers.MGPLL5_ENABLE,
+ TCPLL6 => Registers.MGPLL6_ENABLE);
+ DKL_NEW_TYPE_C_ENABLE : constant PLL_Enable_Regs_Array :=
+ PLL_Enable_Regs_Array'
+ (TCPLL1 => Registers.PORTTC1_PLL1_ENABLE,
+ TCPLL2 => Registers.PORTTC2_PLL1_ENABLE,
+ TCPLL3 => Registers.PORTTC3_PLL1_ENABLE,
+ TCPLL4 => Registers.PORTTC4_PLL1_ENABLE,
+ TCPLL5 => Registers.MGPLL5_ENABLE,
+ TCPLL6 => Registers.MGPLL6_ENABLE);
+ begin
+ if Config.Has_New_Type_C_PLL_Enable then
+ return DKL_NEW_TYPE_C_ENABLE (P);
+ else
+ return DKL_ENABLE (P);
+ end if;
+ end DKL_PLL_ENABLE;
+
+ type PLL_Regs_Record is record
+ DKL_REFCLKIN_CTL : Registers.Registers_Index;
+ DKL_CLKTOP2_CORECLKCTL1 : Registers.Registers_Index;
+ DKL_CLKTOP2_HSCLKCTL : Registers.Registers_Index;
+ DKL_PLL_DIV0 : Registers.Registers_Index;
+ DKL_PLL_DIV1 : Registers.Registers_Index;
+ DKL_PLL_SSC : Registers.Registers_Index;
+ DKL_PLL_BIAS : Registers.Registers_Index;
+ DKL_PLL_COLDST_BIAS : Registers.Registers_Index;
+ end record;
+
+ type PLL_Regs_Array is array (DKL_DPLLs) of PLL_Regs_Record;
+ PLL_Regs : constant PLL_Regs_Array :=
+ PLL_Regs_Array'
+ (TCPLL1 =>
+ (Registers.DKL_REFCLKIN_CTL_1,
+ Registers.DKL_CLKTOP2_CCC1_1,
+ Registers.DKL_CLKTOP2_HSCC_1,
+ Registers.DKL_PLL_DIV0_1,
+ Registers.DKL_PLL_DIV1_1,
+ Registers.DKL_PLL_SSC_1,
+ Registers.DKL_PLL_BIAS_1,
+ Registers.DKL_PLL_COLDST_BIAS_1),
+ TCPLL2 =>
+ (Registers.DKL_REFCLKIN_CTL_2,
+ Registers.DKL_CLKTOP2_CCC1_2,
+ Registers.DKL_CLKTOP2_HSCC_2,
+ Registers.DKL_PLL_DIV0_2,
+ Registers.DKL_PLL_DIV1_2,
+ Registers.DKL_PLL_SSC_2,
+ Registers.DKL_PLL_BIAS_2,
+ Registers.DKL_PLL_COLDST_BIAS_2),
+ TCPLL3 =>
+ (Registers.DKL_REFCLKIN_CTL_3,
+ Registers.DKL_CLKTOP2_CCC1_3,
+ Registers.DKL_CLKTOP2_HSCC_3,
+ Registers.DKL_PLL_DIV0_3,
+ Registers.DKL_PLL_DIV1_3,
+ Registers.DKL_PLL_SSC_3,
+ Registers.DKL_PLL_BIAS_3,
+ Registers.DKL_PLL_COLDST_BIAS_3),
+ TCPLL4 =>
+ (Registers.DKL_REFCLKIN_CTL_4,
+ Registers.DKL_CLKTOP2_CCC1_4,
+ Registers.DKL_CLKTOP2_HSCC_4,
+ Registers.DKL_PLL_DIV0_4,
+ Registers.DKL_PLL_DIV1_4,
+ Registers.DKL_PLL_SSC_4,
+ Registers.DKL_PLL_BIAS_4,
+ Registers.DKL_PLL_COLDST_BIAS_4),
+ TCPLL5 =>
+ (Registers.DKL_REFCLKIN_CTL_5,
+ Registers.DKL_CLKTOP2_CCC1_5,
+ Registers.DKL_CLKTOP2_HSCC_5,
+ Registers.DKL_PLL_DIV0_5,
+ Registers.DKL_PLL_DIV1_5,
+ Registers.DKL_PLL_SSC_5,
+ Registers.DKL_PLL_BIAS_5,
+ Registers.DKL_PLL_COLDST_BIAS_5),
+ TCPLL6 =>
+ (Registers.DKL_REFCLKIN_CTL_6,
+ Registers.DKL_CLKTOP2_CCC1_6,
+ Registers.DKL_CLKTOP2_HSCC_6,
+ Registers.DKL_PLL_DIV0_6,
+ Registers.DKL_PLL_DIV1_6,
+ Registers.DKL_PLL_SSC_6,
+ Registers.DKL_PLL_BIAS_6,
+ Registers.DKL_PLL_COLDST_BIAS_6));
+
+ DKL_REFCLKIN_CTL_OD_2_MUX_MASK : constant := 7 * 2 ** 8;
+ DKL_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK : constant := 16#ff# * 2 ** 8;
+ DKL_CLKTOP2_HSCLKCTL_MASK : constant := 16#1_FF00#;
+ DKL_PLL_DIV0_MASK : constant := 16#1F_FFFF#;
+ DKL_PLL_DIV1_MASK : constant := 16#1F_00FF#;
+ DKL_PLL_SSC_MASK : constant := 16#E0FF_3A00#;
+ DKL_PLL_BIAS_MASK : constant := 16#7FFF_FF00#;
+ DKL_PLL_COLD_BIAS_MASK : constant := 16#ffff#;
+ DKL_PLL_BIAS_FRAC_EN_H : constant := 1 * 2 ** 30;
+
+ procedure Calc_Dividers
+ (Clock : in Frequency_Type;
+ Display : in Display_Type;
+ DKL_Refclkin_Ctl : out Word32;
+ DKL_Clktop2_Coreclkctl1 : out Word32;
+ DKL_Clktop2_HSClkCtl : out Word32;
+ DCO_Khz : out DCO_Range_KHz;
+ Success : out Boolean)
+ is
+ DCO_Min_Freq, DCO_Max_Freq : Int64;
+ type Dividers_List is array (1 .. 4) of Int64;
+ Dividers : constant Dividers_List := (7, 5, 3, 2);
+ DKL_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 : constant := 0 * 2 ** 12;
+ DKL_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 : constant := 1 * 2 ** 12;
+ DKL_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 : constant := 2 * 2 ** 12;
+ DKL_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 : constant := 3 * 2 ** 12;
+ function DKL_REFCLKIN_CTL_OD_2_MUX (N : Word32) return Word32
+ is (Shift_Left (N, 8));
+ function DKL_CLKTOP2_CORECLKCTL1_A_DIVRATIO (N : Word32) return Word32
+ is (Shift_Left (N, 8));
+ function DKL_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL (N : Word32) return Word32
+ is (Shift_Left (N, 14));
+ function DKL_CLKTOP2_HSCLKCTL_CORE_INPUTSEL (N : Word32) return Word32
+ is (Shift_Left (N, 16));
+ function DKL_CLKTOP2_HSCLKCTL_DSDIV_RATIO (N : Word32) return Word32
+ is (Shift_Left (N, 8));
+ A_DivRatio, TLineDrv, Inputsel, Hsdiv : Word32;
+ Clock_Khz : constant Frequency_KHz := Frequency_KHz(Clock / 1_000);
+ begin
+ if Display = DP then
+ DCO_Min_Freq := 8_100_000;
+ DCO_Max_Freq := 8_100_000;
+ else
+ DCO_Min_Freq := DCO_Range_KHz'First;
+ DCO_Max_Freq := DCO_Range_KHz'Last;
+ end if;
+
+ DKL_Refclkin_Ctl := 0;
+ DKL_clktop2_coreclkctl1 := 0;
+ DKL_CLKTOP2_hsclkctl := 0;
+
+ DCO_KHz := DCO_Min_Freq;
+ Success := False;
+ for I in Dividers'Range loop
+ pragma Loop_Invariant (DCO_KHz >= DCO_Min_Freq and DCO_KHz <= DCO_Max_Freq);
+ for Div2 in reverse 1 .. 10 loop
+ declare
+ Tmp: constant Pos64 := Dividers (I) * Pos64 (Div2) * Pos64(Clock_Khz) * 5;
+ begin
+ if Tmp >= DCO_Min_Freq and then Tmp <= DCO_Max_Freq then
+ DCO_KHz := Tmp;
+ if Div2 >= 2 then
+ A_DivRatio := (if Display = DP then 10 else 5);
+ TLineDrv := 1;
+ else
+ A_DivRatio := 5;
+ TLineDrv := 0;
+ end if;
+ Inputsel := (if Display = DP then 0 else 1);
+ Hsdiv := (case Dividers (I) is
+ when 2 => DKL_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2,
+ when 3 => DKL_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3,
+ when 5 => DKL_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5,
+ when 7 => DKL_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7,
+ when others => DKL_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2);
+ DKL_Refclkin_Ctl := DKL_REFCLKIN_CTL_OD_2_MUX (1);
+ DKL_clktop2_coreclkctl1 :=
+ DKL_CLKTOP2_CORECLKCTL1_A_DIVRATIO (A_DivRatio);
+ DKL_CLKTOP2_hsclkctl :=
+ DKL_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL (TLineDrv) or
+ DKL_CLKTOP2_HSCLKCTL_CORE_INPUTSEL (Inputsel) or
+ Hsdiv or
+ DKL_CLKTOP2_HSCLKCTL_DSDIV_RATIO (Word32 (Div2));
+ Success := True;
+ end if;
+ exit when Success;
+ end;
+ end loop;
+ exit when Success;
+ end loop;
+ end Calc_Dividers;
+
+ procedure On
+ (PLL : in DKL_DPLLs;
+ Port_Cfg : in Port_Config;
+ Success : out Boolean)
+ is
+ DKL_Refclkin_Ctl : Word32;
+ DKL_Clktop2_Coreclkctl1 : Word32;
+ DKL_Clktop2_HSClkCtl : Word32;
+ DCO_Khz : DCO_Range_KHz;
+ Clock : Frequency_Type;
+ begin
+ if Port_Cfg.Display = HDMI then
+ Clock := Port_Cfg.Mode.Dotclock;
+ else
+ Clock := Frequency_Type (DP_Symbol_Rate (Port_Cfg.DP.Bandwidth));
+ end if;
+
+ Calc_Dividers
+ (Clock => Clock,
+ Display => Port_Cfg.Display,
+ DKL_Refclkin_Ctl => DKL_Refclkin_Ctl,
+ DKL_Clktop2_Coreclkctl1 => DKL_Clktop2_Coreclkctl1,
+ DKL_Clktop2_HSClkCtl => DKL_Clktop2_HSClkCtl,
+ DCO_Khz => DCO_Khz,
+ Success => Success);
+
+ if not Success then
+ Debug.Put_Line ("Could not find dividers for port!");
+ return;
+ end if;
+
+ Registers.Set_Mask
+ (Register => DKL_PLL_ENABLE (PLL),
+ Mask => DPLL_ENABLE_POWER_ENABLE);
+
+ Registers.Wait_Set_Mask
+ (Register => DKL_PLL_ENABLE (PLL),
+ Mask => DPLL_ENABLE_POWER_STATE);
+
+ declare
+ Tmp : Int64;
+ Refclk : Power_And_Clocks.Refclk_Range;
+ Refclk_Khz : Power_And_Clocks.Refclk_Range_KHz;
+ FeedFwGain : Word32;
+ M1Div : constant := 2;
+ M2Div_Int, M2Div_Rem: Int64;
+ M2Div_Frac : Word32;
+ TDC_Target : Word32;
+ Prop_Coeff, Int_Coeff : Word32;
+ IRef_Ndiv, Iref_Itrim : Word32;
+ begin
+ Power_And_Clocks.Get_Refclk (Refclk);
+ Refclk_Khz := Power_And_Clocks.Refclk_Range_KHz (Refclk / 1_000);
+ M2Div_Int := Int64(DCO_Khz / (Refclk_Khz * M1Div));
+ M2Div_Rem := Int64(DCO_Khz rem (Refclk_Khz * M1Div));
+ Tmp := M2Div_Rem * 2 ** 22;
+ M2Div_Frac := Word32 (Tmp / Int64(Refclk_Khz * M1Div));
+
+ case Refclk is
+ when 24_000_000 =>
+ Iref_Ndiv := 1;
+ Iref_Itrim := 25;
+ when 38_400_000 =>
+ Iref_Ndiv := 2;
+ Iref_Itrim := 28;
+ when others =>
+ Iref_Ndiv := 1;
+ Iref_Itrim := 28;
+ end case;
+
+ -- Real number math converted to fixed point
+ -- see note in i915 about these calculations
+ TDC_Target := Word32 (2 * 1_000 * 100_000 * 10 / (132 * Refclk_Khz) + 5) / 10;
+
+ if M2Div_Rem > 0 then
+ FeedFwGain := (M1Div * 1_000_000 * 100) / (Word32 (DCO_Khz) * 3 / 10);
+ else
+ FeedFwGain := 0;
+ end if;
+
+ if DCO_Khz >= 9_000_000 then
+ Prop_Coeff := 5;
+ Int_Coeff := 10;
+ else
+ Prop_Coeff := 4;
+ Int_Coeff := 8;
+ end if;
+
+ -- The following DKL registers are at MMIO index 2
+ Registers.Write (HIP_INDEX_REG (PLL), HIP_INDEX_VAL (PLL, 2));
+
+ Registers.Unset_And_Set_Mask
+ (Register => PLL_Regs (PLL).DKL_REFCLKIN_CTL,
+ Mask_Unset => DKL_REFCLKIN_CTL_OD_2_MUX_MASK,
+ Mask_Set => DKL_Refclkin_Ctl);
+
+ Registers.Unset_And_Set_Mask
+ (Register => PLL_Regs (PLL).DKL_CLKTOP2_CORECLKCTL1,
+ Mask_Unset => DKL_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK,
+ Mask_Set => DKL_Clktop2_Coreclkctl1);
+
+ Registers.Unset_And_Set_Mask
+ (Register => PLL_Regs (PLL).DKL_CLKTOP2_HSCLKCTL,
+ Mask_Unset => DKL_CLKTOP2_HSCLKCTL_MASK,
+ Mask_Set => DKL_CLKTOP2_hsclkctl);
+
+ Registers.Unset_And_Set_mask
+ (Register => PLL_Regs (PLL).DKL_PLL_DIV0,
+ Mask_Unset => DKL_PLL_DIV0_MASK,
+ Mask_Set => Shift_Left (Int_Coeff, 16) or
+ Shift_Left (Prop_Coeff, 12) or
+ Shift_Left (M1Div, 8) or
+ Word32(M2Div_Int));
+
+ Registers.Unset_And_Set_Mask
+ (Register => PLL_Regs (PLL).DKL_PLL_DIV1,
+ Mask_Unset => DKL_PLL_DIV1_MASK,
+ Mask_Set => Shift_Left (Iref_Itrim, 16) or
+ TDC_Target);
+
+ Registers.Unset_And_Set_Mask
+ (Register => PLL_Regs (PLL).DKL_PLL_SSC,
+ Mask_Unset => DKL_PLL_SSC_MASK,
+ Mask_Set => Shift_Left (Iref_Ndiv, 29) or
+ Shift_Left (4, 11)); -- SSC_STEP_NUM (always 4)
+
+ Registers.Unset_And_Set_Mask
+ (Register => PLL_Regs (PLL).DKL_PLL_BIAS,
+ Mask_Unset => DKL_PLL_BIAS_MASK,
+ Mask_Set => Shift_Left (M2Div_Frac, 8) or
+ (if M2Div_Frac > 0 then DKL_PLL_BIAS_FRAC_EN_H else 0));
+
+ Registers.Unset_And_Set_Mask
+ (Register => PLL_Regs (PLL).DKL_PLL_COLDST_BIAS,
+ Mask_Unset => DKL_PLL_COLD_BIAS_MASK,
+ Mask_Set => FeedFwGain);
+
+ -- Read back the last programmed PHY PLL register
+ Registers.Posting_Read (PLL_Regs (PLL).DKL_PLL_COLDST_BIAS);
+
+ Registers.Set_Mask
+ (Register => DKL_PLL_ENABLE (PLL),
+ Mask => DPLL_ENABLE_PLL_ENABLE);
+
+ Registers.Wait_Set_Mask
+ (Register => DKL_PLL_ENABLE (PLL),
+ Mask => DPLL_ENABLE_PLL_LOCK);
+ end;
+ end On;
+
+ procedure Free (PLL : DKL_DPLLs)
+ is
+ begin
+ Registers.Unset_Mask
+ (Register => DKL_PLL_ENABLE (PLL),
+ Mask => DPLL_ENABLE_PLL_ENABLE);
+ Registers.Wait_Unset_Mask
+ (Register => DKL_PLL_ENABLE (PLL),
+ Mask => DPLL_ENABLE_PLL_LOCK);
+
+ Registers.Unset_Mask
+ (Register => DKL_PLL_ENABLE (PLL),
+ Mask => DPLL_ENABLE_POWER_ENABLE);
+ Registers.Wait_Unset_Mask
+ (Register => DKL_PLL_ENABLE (PLL),
+ Mask => DPLL_ENABLE_POWER_STATE);
+ end Free;
+
+ procedure All_Off is
+ begin
+ for PLL in DKL_DPLLs loop
+ Free (PLL);
+ end loop;
+ end All_Off;
+
+end HW.GFX.GMA.PLLs.DKL;
diff --git a/common/tigerlake/hw-gfx-gma-plls-dkl.ads b/common/tigerlake/hw-gfx-gma-plls-dkl.ads
new file mode 100644
index 0000000..51070e5
--- /dev/null
+++ b/common/tigerlake/hw-gfx-gma-plls-dkl.ads
@@ -0,0 +1,29 @@
+--
+-- Copyright (C) 2022 Google, LLC
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.Debug;
+with GNAT.Source_Info;
+
+private package HW.GFX.GMA.PLLs.DKL is
+
+ procedure On
+ (PLL : in DKL_DPLLs;
+ Port_Cfg : in Port_Config;
+ Success : out Boolean);
+
+ procedure Free (PLL : DKL_DPLLs);
+
+ procedure All_Off;
+
+end HW.GFX.GMA.PLLs.DKL;
diff --git a/common/tigerlake/hw-gfx-gma-plls.adb b/common/tigerlake/hw-gfx-gma-plls.adb
index 2823870..f7f0eb3 100644
--- a/common/tigerlake/hw-gfx-gma-plls.adb
+++ b/common/tigerlake/hw-gfx-gma-plls.adb
@@ -14,16 +14,28 @@
with HW.Debug;
with GNAT.Source_Info;
+with HW.GFX.GMA.PLLs.Combo_Phy;
+with HW.GFX.GMA.PLLs.DKL;
+with HW.GFX.GMA.Config;
package body HW.GFX.GMA.PLLs
with
Refined_State => (State => PLLs)
is
- type Count_Range is new Natural range 0 .. 2;
+ type PLL_Type is (PLL_Unknown, PLL_Combo_Phy, PLL_DKL);
+ function Port_PLL_Type (Port : GPU_Port) return PLL_Type is
+ (case Port is
+ when DIGI_A | DIGI_B | DIGI_C => PLL_Combo_Phy,
+ when DDI_TC1 | DDI_TC2 | DDI_TC3 | DDI_TC4 | DDI_TC5 | DDI_TC6 => PLL_DKL,
+ when others => PLL_Unknown);
+ type Count_Range is new Natural range 0 .. 2;
type PLL_State is record
Use_Count : Count_Range;
+ Used_For_DP : Boolean;
+ Link_Rate : DP_Bandwidth;
+ Mode : Mode_Type;
end record;
type PLL_State_Array is array (Configurable_DPLLs) of PLL_State;
@@ -41,7 +53,10 @@
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
PLLs :=
(Configurable_DPLLs =>
- (Use_Count => 0));
+ (Use_Count => 0,
+ Used_For_DP => False,
+ Link_Rate => DP_Bandwidth'First,
+ Mode => Invalid_Mode));
end Initialize;
procedure Alloc
@@ -49,26 +64,105 @@
PLL : out T;
Success : out Boolean)
is
+ function Port_PLL_Match (Port : GPU_Port; PLL : T) return Boolean
+ is
+ begin
+ if Port in Combo_Port and PLL in Combo_DPLLs then
+ return True;
+ elsif Port in USBC_Port and PLL in DKL_DPLLs then
+ if (Port = DDI_TC1 and PLL = TCPLL1) or
+ (Port = DDI_TC2 and PLL = TCPLL2) or
+ (Port = DDI_TC3 and PLL = TCPLL3) or
+ (Port = DDI_TC4 and PLL = TCPLL4) or
+ (Port = DDI_TC5 and PLL = TCPLL5) or
+ (Port = DDI_TC6 and PLL = TCPLL6)
+ then
+ return True;
+ end if;
+ end if;
+
+ return False;
+ end Port_PLL_Match;
+
+ function Config_Matches (PE : HW.GFX.GMA.PLLs.PLL_State) return Boolean
+ is
+ begin
+ return
+ PE.Used_For_DP = (Port_Cfg.Display = DP) and
+ ((PE.Used_For_DP and PE.Link_Rate = Port_Cfg.DP.Bandwidth) or
+ (not PE.Used_For_DP and PE.Mode = Port_Cfg.Mode));
+ end Config_Matches;
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
- PLL := Invalid_PLL;
- Success := True;
+
+ for P in Configurable_DPLLs loop
+ Success := PLLs (P).Use_Count /= 0 and
+ PLLs (P).Use_Count /= Count_Range'Last and
+ Port_PLL_Match (Port_Cfg.Port, P) and
+ Config_Matches (PLLs (P));
+ if Success then
+ PLL := P;
+ PLLs (PLL).Use_Count := PLLs (PLL).Use_Count + 1;
+ return;
+ end if;
+ end loop;
+
+ for P in Configurable_DPLLs loop
+ if PLLs (P).Use_Count = 0 and Port_PLL_Match (Port_Cfg.Port, P) then
+ PLL := P;
+ if P in Combo_DPLLs then
+ Combo_Phy.On (PLL, Port_Cfg, Success);
+ else--if P in DKL_DPLLs then
+ DKL.On (PLL, Port_Cfg, Success);
+ end if;
+
+ if Success then
+ PLLs (PLL) :=
+ (Use_Count => 1,
+ Used_For_DP => Port_Cfg.Display = DP,
+ Link_Rate => Port_Cfg.DP.Bandwidth,
+ Mode => Port_Cfg.Mode);
+ end if;
+ return;
+ end if;
+ end loop;
+
+ PLL := Invalid;
+ Success := False;
end Alloc;
procedure Free (PLL : T) is
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+ if PLL /= Invalid_PLL then
+ PLLs (PLL).Use_Count := 0;
+ end if;
+
+ if PLL in Combo_DPLLs then
+ Combo_Phy.Free (PLL);
+ elsif PLL in DKL_DPLLs then
+ DKL.Free (PLL);
+ end if;
end Free;
procedure All_Off is
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+ Combo_Phy.All_Off;
+ DKL.All_Off;
end All_Off;
function Register_Value (PLL : T) return Word32
is
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
- Return 0;
+
+ -- Only required for combo ports
+ if PLL in Combo_DPLLs then
+ return Combo_Phy.Register_Value (PLL);
+ end if;
+
+ return 0;
end Register_Value;
end HW.GFX.GMA.PLLs;
diff --git a/common/tigerlake/hw-gfx-gma-plls.ads b/common/tigerlake/hw-gfx-gma-plls.ads
index 3e55044..ff758a4 100644
--- a/common/tigerlake/hw-gfx-gma-plls.ads
+++ b/common/tigerlake/hw-gfx-gma-plls.ads
@@ -18,36 +18,25 @@
is
-- XXX: Types should be private (but that triggers a bug in SPARK GPL 2016)
- type T is (Invalid_PLL, DPLL0, DPLL1, DPLL4, DPLL2);
- subtype Configurable_DPLLs is T range DPLL0 .. DPLL4;
+ type T is (Invalid_PLL, DPLL0, DPLL1, TCPLL1, TCPLL2, TCPLL3, TCPLL4, TCPLL5, TCPLL6);
+ subtype Configurable_DPLLs is T range DPLL0 .. TCPLL6;
+ subtype Combo_DPLLs is T range DPLL0 .. DPLL1;
+ subtype DKL_DPLLs is T range TCPLL1 .. TCPLL6;
Invalid : constant T := Invalid_PLL;
procedure Initialize
with
Global => (Output => State);
- pragma Warnings (Off, "unused variable ""Port_Cfg""",
- Reason => "Not yet implemented.");
procedure Alloc
(Port_Cfg : in Port_Config;
PLL : out T;
Success : out Boolean);
- pragma Warnings (On, "unused variable ""Port_Cfg""");
-
- pragma Warnings (Off, "subprogram ""Free"" has no effect",
- Reason => "Not yet implemented.");
procedure Free (PLL : T);
- pragma Warnings (On, "subprogram ""Free"" has no effect");
- pragma Warnings (Off, "subprogram ""All_Off"" has no effect",
- Reason => "Not yet implemented.");
procedure All_Off;
- pragma Warnings (On, "subprogram ""All_Off"" has no effect");
- pragma Warnings (Off, "unused variable ""PLL""",
- Reason => "Not yet implemented.");
function Register_Value (PLL : T) return Word32;
- pragma Warnings (On, "unused variable ""PLL""");
end HW.GFX.GMA.PLLs;
--
To view, visit https://review.coreboot.org/c/libgfxinit/+/82141?usp=email
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Gerrit-Project: libgfxinit
Gerrit-Branch: cros
Gerrit-Change-Id: I9dd7e0d0180f70d73eb50d7e58718261e5e74071
Gerrit-Change-Number: 82141
Gerrit-PatchSet: 1
Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com>
Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com>
Gerrit-MessageType: newchange
1
0
[L] Change in libgfxinit[cros]: gma tgl: Fill out power and clocks module
by Dinesh Gehlot (Code Review) 30 Apr '24
by Dinesh Gehlot (Code Review) 30 Apr '24
30 Apr '24
Attention is currently required from: Jérémy Compostella, Tim Wawrzynczak.
Hello Jérémy Compostella, Tim Wawrzynczak,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/libgfxinit/+/82140?usp=email
to review the following change.
Change subject: gma tgl: Fill out power and clocks module
......................................................................
gma tgl: Fill out power and clocks module
This is the modeset sequence for the display engine itself. TGL has
similarities to both SKL and BXT, but also adds new programming, like
MBUS credits, Bandwidth Buddy, and of course new chicken bits.
Tested on google/delbin; can still boot successfully to the kernel and
the kernel can still properly perform its own modeset and not crash :)
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
Change-Id: I8f09696588aa73cebc7a44583ae5e029c705a535
---
M common/tigerlake/hw-gfx-gma-power_and_clocks.adb
M common/tigerlake/hw-gfx-gma-power_and_clocks.ads
2 files changed, 818 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/40/82140/1
diff --git a/common/tigerlake/hw-gfx-gma-power_and_clocks.adb b/common/tigerlake/hw-gfx-gma-power_and_clocks.adb
index 0a78217..88e932d 100644
--- a/common/tigerlake/hw-gfx-gma-power_and_clocks.adb
+++ b/common/tigerlake/hw-gfx-gma-power_and_clocks.adb
@@ -12,55 +12,851 @@
-- GNU General Public License for more details.
--
-with HW.Debug;
with GNAT.Source_Info;
-
+with HW.Debug;
+with HW.GFX.GMA.Combo_Phy;
with HW.GFX.GMA.Config;
+with HW.GFX.GMA.PCode;
+with HW.GFX.GMA.Registers;
+with HW.GFX.GMA.Transcoder;
+
+use type HW.Word64;
package body HW.GFX.GMA.Power_And_Clocks is
- procedure Pre_All_Off is
- begin
- pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
- end Pre_All_Off;
+ type Power_Domain is
+ (PW1, PW2, PW3, PW4, PW5,
+ AUX_A, AUX_B, AUX_C,
+ AUX_USBC1, AUX_USBC2, AUX_USBC3, AUX_USBC4, AUX_USBC5, AUX_USBC6,
+ DDI_A, DDI_B, DDI_C,
+ DDI_USBC1, DDI_USBC2, DDI_USBC3, DDI_USBC4, DDI_USBC5, DDI_USBC6);
+ type Power_Domain_Types is (Power_Well, Power_DDI, Power_AUX);
+ subtype PW_Domain is Power_Domain range PW1 .. PW5;
+ subtype DDI_Domain is Power_Domain range DDI_A .. DDI_USBC6;
+ subtype AUX_Domain is Power_Domain range AUX_A .. AUX_USBC6;
+ subtype AUX_USBC_Domain is Power_Domain range AUX_USBC1 .. AUX_USBC6;
- procedure Post_All_Off is
+ PCH_DPMGUNIT_CLOCK_GATE_DISABLE : constant := 1 * 2 ** 15;
+ NDE_RSTWRN_OPT_RST_PCH_Handshake_En : constant := 1 * 2 ** 4;
+
+ ----------------------------------------------------------------------------
+
+ DBUF_CTL_DBUF_POWER_REQUEST : constant := 1 * 2 ** 31;
+ DBUF_CTL_TRACKER_STATE_SERVICE_MASK : constant := 16#f8_0000#;
+ DBUF_CTL_TRACKER_STATE_SERVICE_SHIFT : constant := 19;
+ DBUF_CTL_DBUF_POWER_STATE : constant := 1 * 2 ** 30;
+
+ ----------------------------------------------------------------------------
+
+ MBUS_ABOX_CTL_BW_CREDITS_MASK : constant := 16#3# * 2 ** 20;
+ MBUS_ABOX_CTL_B_CREDITS_MASK : constant := 16#f# * 2 ** 16;
+ MBUS_ABOX_CTL_BT_CREDITS_POOL1_MASK : constant := 16#1f# * 2 ** 0;
+ MBUS_ABOX_CTL_BT_CREDITS_POOL2_MASK : constant := 16#1f# * 2 ** 8;
+ MBUS_ABOX_CTL_BW_CREDITS_SHIFT : constant := 20;
+ MBUS_ABOX_CTL_B_CREDITS_SHIFT : constant := 16;
+ MBUS_ABOX_CTL_BT_CREDITS_POOL1_SHIFT : constant := 0;
+ MBUS_ABOX_CTL_BT_CREDITS_POOL2_SHIFT : constant := 8;
+
+ MBUS_ABOX_MASK : constant := Word32'(
+ MBUS_ABOX_CTL_BW_CREDITS_MASK or
+ MBUS_ABOX_CTL_B_CREDITS_MASK or
+ MBUS_ABOX_CTL_BT_CREDITS_POOL1_MASK or
+ MBUS_ABOX_CTL_BT_CREDITS_POOL2_MASK);
+ MBUS_ABOX_CREDITS : constant := Word32'(
+ 1 * 2 ** MBUS_ABOX_CTL_BW_CREDITS_SHIFT or
+ 1 * 2 ** MBUS_ABOX_CTL_B_CREDITS_SHIFT or
+ 16 * 2 ** MBUS_ABOX_CTL_BT_CREDITS_POOL1_SHIFT or
+ 16 * 2 ** MBUS_ABOX_CTL_BT_CREDITS_POOL2_SHIFT);
+
+ type MBUSRegs is array (Natural range 0 .. 2) of Registers.Registers_Index;
+ MBUS_ABOX_CTL : constant MBUSRegs := MBUSRegs'
+ (Registers.MBUS_ABOX_CTL,
+ Registers.MBUS_ABOX1_CTL,
+ Registers.MBUS_ABOX2_CTL);
+
+ ----------------------------------------------------------------------------
+
+ DCPR_MASK_MAXLATENCY_MEMUP_CLR : constant := 1 * 2 ** 27;
+ DCPR_MASK_LPMODE : constant := 1 * 2 ** 26;
+ DCPR_SEND_RESP_IMM : constant := 1 * 2 ** 25;
+ DCPR_CLEAR_MEMSTAT_DIS : constant := 1 * 2 ** 24;
+
+ ----------------------------------------------------------------------------
+
+ function HIP_INDEX_REG (A : AUX_USBC_Domain) return Registers.Registers_Index
+ is (if A <= AUX_USBC4
+ then Registers.HIP_INDEX_REG0
+ else Registers.HIP_INDEX_REG1);
+
+ function HIP_INDEX_VAL (A : AUX_USBC_Domain; Val : Word32) return Word32 is
+ (case A is
+ when AUX_USBC1 | AUX_USBC3 | AUX_USBC5 => Val * 2 ** 0,
+ when AUX_USBC2 | AUX_USBC4 | AUX_USBC6 => Val * 2 ** 8);
+
+ type DKL_Regs is array (AUX_USBC_Domain) of Registers.Registers_Index;
+ DKL_CMN_UC_DW_27 : constant DKL_Regs := DKL_Regs'
+ (AUX_USBC1 => Registers.DKL_CMN_UC_DW_27_1,
+ AUX_USBC2 => Registers.DKL_CMN_UC_DW_27_2,
+ AUX_USBC3 => Registers.DKL_CMN_UC_DW_27_3,
+ AUX_USBC4 => Registers.DKL_CMN_UC_DW_27_4,
+ AUX_USBC5 => Registers.DKL_CMN_UC_DW_27_5,
+ AUX_USBC6 => Registers.DKL_CMN_UC_DW_27_6);
+
+ ----------------------------------------------------------------------------
+
+ function Power_Domain_Type (PD : Power_Domain) return Power_Domain_Types is
+ (if PD in PW_Domain then Power_Well
+ elsif PD in DDI_Domain then Power_DDI
+ else Power_AUX);
+
+ type Power_Well_Regs is array (Power_Domain_Types) of Registers.Registers_Index;
+ PWR_CTL_BIOS : constant Power_Well_Regs :=
+ (Power_Well => Registers.PWR_WELL_CTL_BIOS,
+ Power_DDI => Registers.PWR_DDI_CTL_BIOS,
+ Power_AUX => Registers.PWR_AUX_CTL_BIOS);
+ PWR_CTL_DRIVER : constant Power_Well_Regs :=
+ (Power_Well => Registers.PWR_WELL_CTL_DRIVER,
+ Power_DDI => Registers.PWR_DDI_CTL_DRIVER,
+ Power_AUX => Registers.PWR_AUX_CTL_DRIVER);
+
+ function PW_Index (PW : PW_Domain) return Natural
+ is
+ (Power_Domain'Pos (PW) - Power_Domain'Pos (PW1));
+
+ function DDI_Index (DDI : DDI_Domain) return Natural
+ is
+ (Power_Domain'Pos (DDI) - Power_Domain'Pos (DDI_A));
+
+ function AUX_Index (AUX : AUX_Domain) return Natural
+ is
+ (Power_Domain'Pos (AUX) - Power_Domain'Pos (AUX_A));
+
+ function PW_Request_Mask (PW : PW_Domain) return Word32 is
+ (2 * 2 ** (2 * PW_Index (PW)));
+ function PW_State_Mask (PW : PW_Domain) return Word32 is
+ (1 * 2 ** (2 * PW_Index (PW)));
+
+ function DDI_Request_Mask (DDI : DDI_Domain) return Word32 is
+ (2 * 2 ** (2 * DDI_Index (DDI)));
+ function DDI_State_Mask (DDI : DDI_Domain) return Word32 is
+ (1 * 2 ** (2 * DDI_Index (DDI)));
+
+ function AUX_Request_Mask (AUX : AUX_Domain) return Word32 is
+ (2 * 2 ** (2 * AUX_Index (AUX)));
+ function AUX_State_Mask (AUX : AUX_Domain) return Word32 is
+ (1 * 2 ** (2 * AUX_Index (AUX)));
+
+ ----------------------------------------------------------------------------
+
+ FUSE_STATUS_PG0_DIST_STATUS : constant := 1 * 2 ** 27;
+ type Power_Well_Values is array (PW_Domain) of Word32;
+ FUSE_STATUS_PGx_DIST_STATUS : constant Power_Well_Values :=
+ (PW1 => 1 * 2 ** 26,
+ PW2 => 1 * 2 ** 25,
+ PW3 => 1 * 2 ** 24,
+ PW4 => 1 * 2 ** 23,
+ PW5 => 1 * 2 ** 22);
+
+ ----------------------------------------------------------------------------
+
+ TGL_PCODE_MEM_SUBSYSTEM_INFO : constant := 16#d#;
+ TGL_PCODE_MEM_SS_READ_GLOBAL_INFO : constant := 0 * 2 ** 8;
+ TGL_PCODE_CDCLK_CONTROL : constant := 7;
+ TGL_CDCLK_PREPARE_FOR_CHANGE : constant := 3;
+ TGL_CDCLK_READY_FOR_CHANGE : constant := 1;
+
+ ----------------------------------------------------------------------------
+
+ CDCLK_PLL_ENABLE_PLL_RATIO_MASK : constant := 16#ff#;
+ CDCLK_PLL_ENABLE_PLL_ENABLE : constant := 1 * 2 ** 31;
+ CDCLK_PLL_ENABLE_PLL_LOCK : constant := 1 * 2 ** 30;
+ CDCLK_CD2X_DIV_SEL_MASK : constant := 3 * 2 ** 22;
+ CDCLK_CD2X_DIV_SEL_1 : constant := 0 * 2 ** 22;
+ CDCLK_CD2X_DIV_SEL_2 : constant := 2 * 2 ** 22;
+ CDCLK_CD2X_PIPE_NONE : constant := 7 * 2 ** 19;
+ CDCLK_CTL_CD_FREQ_DECIMAL_MASK : constant := 16#7ff#;
+
+ ----------------------------------------------------------------------------
+
+ function Power_Request_Mask (PD : Power_Domain) return Word32 is
+ begin
+ if PD in PW_Domain then
+ return PW_Request_Mask (PD);
+ elsif PD in DDI_Domain then
+ return DDI_Request_Mask (PD);
+ else
+ return AUX_Request_Mask (PD);
+ end if;
+ end Power_Request_Mask;
+
+ function Power_State_Mask (PD : Power_Domain) return Word32 is
+ begin
+ if PD in PW_Domain then
+ return PW_State_Mask (PD);
+ elsif PD in DDI_Domain then
+ return DDI_State_Mask (PD);
+ else
+ return AUX_State_Mask (PD);
+ end if;
+ end Power_State_Mask;
+
+ type AUX_CTL_Array is array (AUX_USBC_Domain) of Registers.Registers_Index;
+ AUX_CTL_Regs : constant AUX_CTL_Array :=
+ AUX_CTL_Array'
+ (AUX_USBC1 => Registers.DDI_AUX_CTL_USBC1,
+ AUX_USBC2 => Registers.DDI_AUX_CTL_USBC2,
+ AUX_USBC3 => Registers.DDI_AUX_CTL_USBC3,
+ AUX_USBC4 => Registers.DDI_AUX_CTL_USBC4,
+ AUX_USBC5 => Registers.DDI_AUX_CTL_USBC5,
+ AUX_USBC6 => Registers.DDI_AUX_CTL_USBC6);
+
+ function Aux_To_Port (PD : AUX_USBC_Domain) return USBC_Port
+ is (case PD is
+ when AUX_USBC1 => DDI_TC1,
+ when AUX_USBC2 => DDI_TC2,
+ when AUX_USBC3 => DDI_TC3,
+ when AUX_USBC4 => DDI_TC4,
+ when AUX_USBC5 => DDI_TC5,
+ when AUX_USBC6 => DDI_TC6);
+
+ procedure Pre_On (PD : Power_Domain)
+ is
+ DP_AUX_CH_CTL_TBT_IO : constant := 1 * 2 ** 11;
+ begin
+ if PD in AUX_USBC_Domain then
+ -- Disable TBT IO mode for AUX
+ Registers.Unset_Mask
+ (Register => AUX_CTL_Regs (PD),
+ Mask => DP_AUX_CH_CTL_TBT_IO);
+
+ end if;
+ end Pre_On;
+
+ procedure Post_On (PD : Power_Domain)
+ is
+ DKL_CMN_UC_DW_27_UC_HEALTH : constant := 1 * 2 ** 15;
+ begin
+ if PD in PW_Domain then
+ Registers.Wait_Set_Mask (Registers.FUSE_STATUS,
+ FUSE_STATUS_PGx_DIST_STATUS (PD));
+ elsif PD in AUX_USBC_Domain then
+ Registers.Write (HIP_INDEX_REG (PD), HIP_INDEX_VAL (PD, 2));
+ Registers.Wait_Set_Mask
+ (Register => DKL_CMN_UC_DW_27 (PD),
+ Mask => DKL_CMN_UC_DW_27_UC_HEALTH);
+ end if;
+ end Post_On;
+
+ procedure PD_On (PD : Power_Domain)
+ is
+ Ctl1, Ctl2 : Word32;
+ PD_Type : constant Power_Domain_Types := Power_Domain_Type (PD);
+ Success : Boolean;
+ begin
+ Pre_On (PD);
+
+ Registers.Read (PWR_CTL_BIOS (PD_Type), Ctl1);
+ Registers.Read (PWR_CTL_DRIVER (PD_Type), Ctl2);
+
+ if ((Ctl1 or Ctl2) and Power_Request_Mask (PD)) = 0 then
+ Registers.Wait_Unset_Mask
+ (Register => PWR_CTL_DRIVER (PD_Type),
+ Mask => Power_State_Mask (PD));
+ end if;
+
+ if (Ctl2 and Power_Request_Mask (PD)) = 0 then
+ Registers.Set_Mask (PWR_CTL_DRIVER (PD_Type), Power_Request_Mask (PD));
+ Registers.Wait_Set_Mask
+ (Register => PWR_CTL_DRIVER (PD_Type),
+ Mask => Power_State_Mask (PD),
+ Success => Success);
+
+ if not Success then
+ Debug.Put_Line ("Failed to enable power domain!");
+ return;
+ end if;
+ end if;
+
+ Post_On (PD);
+ end PD_On;
+
+ procedure PD_Off (PD : Power_Domain)
+ is
+ Ctl1, Ctl2 : Word32;
+ PD_Type : constant Power_Domain_Types := Power_Domain_Type (PD);
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
- end Post_All_Off;
+ Registers.Read (PWR_CTL_BIOS (PD_Type), Ctl1);
+ Registers.Read (PWR_CTL_DRIVER (PD_Type), Ctl2);
+
+ if ((Ctl1 or Ctl2) and Power_Request_Mask (PD)) /= 0 then
+ Registers.Wait_Set_Mask
+ (Register => PWR_CTL_DRIVER (PD_Type),
+ Mask => Power_State_Mask (PD));
+ end if;
+
+ if (Ctl2 and Power_Request_Mask (PD)) /= 0 then
+ Registers.Unset_Mask (PWR_CTL_DRIVER (PD_Type), Power_Request_Mask (PD));
+ Registers.Unset_Mask (PWR_CTL_BIOS (PD_Type), Power_Request_Mask (PD));
+ end if;
+ end PD_Off;
+
+ type Port_Array is array (natural range <>) of Active_Port_Type;
+ Conventional_Ports : constant Port_Array :=
+ (DP1, DP2, DP3, HDMI1, HDMI2, HDMI3);
+ TC_Ports : constant Port_Array :=
+ (USBC1_DP, USBC2_DP, USBC3_DP, USBC4_DP, USBC5_DP, USBC6_DP,
+ USBC1_HDMI, USBC1_HDMI, USBC1_HDMI, USBC1_HDMI, USBC1_HDMI,
+ USBC1_HDMI);
+
+ function Need_PD (PD : Power_Domain; Configs : Pipe_Configs) return Boolean
+ is
+ function Any_Port_Is (Port : Active_Port_Type) return Boolean is
+ (Configs (Primary).Port = Port or Configs (Secondary).Port = Port or
+ Configs (Tertiary).Port = Port);
+
+ function Any_Port_In (Ports : Port_Array) return Boolean is
+ begin
+ for P of Ports loop
+ if (Configs (Primary).Port = P) or
+ (Configs (Secondary).Port = P) or
+ (Configs (Tertiary).Port = P)
+ then
+ return True;
+ end if;
+ end loop;
+ return False;
+ end Any_Port_In;
+
+ function Num_Active_Pipes return Natural is
+ Count : Natural := 0;
+ begin
+ for I in Pipe_Index loop
+ if Configs (I).Port /= Disabled then
+ Count := Count + 1;
+ end if;
+ end loop;
+ return Count;
+ end Num_Active_Pipes;
+ begin
+ case PD is
+ when PW1 | PW2 =>
+ return Configs (Primary).Port /= Disabled or Any_Port_In (Conventional_Ports);
+ when PW3 =>
+ return Configs (Secondary).Port /= Disabled or Any_Port_In (TC_Ports);
+ when PW4 =>
+ return Configs (Tertiary).Port /= Disabled;
+ when PW5 =>
+ return False;
+ when DDI_A | AUX_A =>
+ return Any_Port_Is (DP1) or Any_Port_Is (HDMI1) or Any_Port_Is (eDP);
+ when DDI_B | AUX_B =>
+ return Any_Port_Is (DP2) or Any_Port_Is (HDMI2);
+ when DDI_C | AUX_C =>
+ return Any_Port_Is (DP3) or Any_Port_Is (HDMI3);
+ when DDI_USBC1 | AUX_USBC1 =>
+ return Any_Port_Is (USBC1_DP) or Any_Port_Is (USBC1_HDMI);
+ when DDI_USBC2 | AUX_USBC2 =>
+ return Any_Port_Is (USBC2_DP) or Any_Port_Is (USBC2_HDMI);
+ when DDI_USBC3 | AUX_USBC3 =>
+ return Any_Port_Is (USBC3_DP) or Any_Port_Is (USBC3_HDMI);
+ when DDI_USBC4 | AUX_USBC4 =>
+ return Any_Port_Is (USBC4_DP) or Any_Port_Is (USBC4_HDMI);
+ when DDI_USBC5 | AUX_USBC5 =>
+ return Any_Port_Is (USBC5_DP) or Any_Port_Is (USBC5_HDMI);
+ when DDI_USBC6 | AUX_USBC6 =>
+ return Any_Port_Is (USBC6_DP) or Any_Port_Is (USBC6_HDMI);
+ end case;
+ end Need_PD;
+
+ procedure Get_RefClk (Refclk : out Refclk_Range)
+ is
+ DSSM : Word32;
+ DSSM_REFERENCE_FREQUENCY_MASK : constant := 16#e000_0000#;
+ DSSM_REFERENCE_FREQUENCY_24MHZ : constant := 16#0000_0000#;
+ DSSM_REFERENCE_FREQUENCY_19_2MHZ : constant := 16#2000_0000#;
+ DSSM_REFERENCE_FREQUENCY_38_4MHZ : constant := 16#4000_0000#;
+ begin
+ Registers.Read (Registers.DSSM, DSSM);
+ Refclk :=
+ (case DSSM and DSSM_REFERENCE_FREQUENCY_MASK is
+ when DSSM_REFERENCE_FREQUENCY_24MHZ => 24_000_000,
+ when DSSM_REFERENCE_FREQUENCY_19_2MHZ => 19_200_000,
+ when DSSM_REFERENCE_FREQUENCY_38_4MHZ => 38_400_000,
+ when others => 24_000_000);
+ end Get_Refclk;
+
+ procedure Get_RawClk (Rawclk : out Frequency_Type)
+ is
+ Raw_Frequency_24_MHz : Boolean;
+ SFUSE_STRAP_RAW_FREQUENCY : constant := 1 * 2 ** 8;
+ begin
+ Rawclk := Config.Default_RawClk_Freq;
+ Registers.Is_Set_Mask
+ (Register => Registers.SFUSE_STRAP,
+ Mask => SFUSE_STRAP_RAW_FREQUENCY,
+ Result => Raw_Frequency_24_MHz);
+
+ if not Raw_Frequency_24_MHz then
+ Rawclk := 19_200_000;
+ end if;
+ end Get_RawClk;
+
+ procedure Get_Max_CDClk (CDClk : out Config.CDClk_Range)
+ is
+ Refclk_Freq : Frequency_Type;
+ begin
+ Get_Refclk (Refclk_Freq);
+ CDClk :=
+ (case Refclk_Freq is
+ when 24_000_000 => 648_000_000,
+ when others => 652_800_000);
+ end Get_Max_CDClk;
+
+ procedure Normalize_CDClk (CDClk : in Int64; Normalized: out Frequency_Type)
+ with
+ Post => Normalized >= 172_800_000
+ is
+ Refclk_Freq : Frequency_Type;
+ begin
+ Get_Refclk (Refclk_Freq);
+ Normalized :=
+ (case Refclk_Freq is
+ when 19_200_000 | 38_400_000 =>
+ (if CDClk <= 172_800_000 then 172_800_000
+ elsif CDClk <= 192_000_000 then 192_000_000
+ elsif CDClk <= 307_200_000 then 307_200_000
+ elsif CDClk <= 326_400_000 then 326_400_000
+ elsif CDClk <= 556_800_000 then 556_800_000
+ else 652_800_000),
+ when others =>
+ (if CDClk <= 180_000_000 then 180_000_000
+ elsif CDClk <= 192_000_000 then 192_000_000
+ elsif CDClk <= 312_000_000 then 312_000_000
+ elsif CDClk <= 324_000_000 then 324_000_000
+ elsif CDClk <= 552_000_000 then 552_000_000
+ else 648_000_000));
+ end Normalize_CDClk;
+
+ procedure Get_Cur_CDClk (CDClk : out Config.CDClk_Range)
+ with
+ Post => CDClk >= 172_800_000
+ is
+ CDCLK_CTL : Word32;
+ begin
+ Registers.Read (Registers.CDCLK_CTL, CDCLK_CTL);
+ CDCLK_CTL := CDCLK_CTL and CDCLK_CTL_CD_FREQ_DECIMAL_MASK;
+ Normalize_CDClk (Int64 (CDCLK_CTL) * 500_000 + 1_000_000, CDClk);
+ end Get_Cur_CDClk;
+
+ procedure Set_CDClk (CDClk_In : Frequency_Type)
+ is
+ subtype PLL_Ratio_Range is natural range 0 .. 68;
+ function Ratio_For_19_2_MHz (CDCLk : Frequency_Type) return PLL_Ratio_Range is
+ begin
+ case CDClk is
+ when 172_800_000 => return 18;
+ when 192_000_000 => return 20;
+ when 307_200_000 => return 32;
+ when 326_400_000 | 652_800_000 => return 68;
+ when 556_800_000 => return 58;
+ when others => return 0;
+ end case;
+ end Ratio_For_19_2_MHz;
+
+ function Ratio_For_24_MHz (CDCLk : Frequency_Type) return PLL_Ratio_Range is
+ begin
+ case CDClk is
+ when 180_800_000 => return 15;
+ when 192_000_000 => return 16;
+ when 312_000_000 => return 26;
+ when 324_000_000 | 648_000_000 => return 54;
+ when 552_000_000 => return 46;
+ when others => return 0;
+ end case;
+ end Ratio_For_24_MHz;
+
+ function CDCLK_CTL_CD_FREQ_DECIMAL (Freq : Frequency_Type) return Word32 with
+ Pre => Freq > 1_000_000
+ is
+ begin
+ -- Weirdest representation: CDClk - 1MHz in 10.1 (10 + 1 fractional bit)
+ return Word32 (Div_Round_Closest (Int64 (Freq) - 1_000_000, 500_000));
+ end CDCLK_CTL_CD_FREQ_DECIMAL;
+
+ Success : Boolean;
+ CD2X : Word32;
+ PLL_Ratio : PLL_Ratio_Range;
+ CDClk : Config.CDClk_Range;
+ Refclk_Freq : Refclk_Range;
+ VCO : Pos64;
+ begin
+ pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+ Normalize_CDClk (Frequency_Type'Min (CDClk_In, Config.Max_CDClk), CDClk);
+ Get_Refclk (Refclk_Freq);
+ case Refclk_Freq is
+ when 19_200_000 => PLL_Ratio := Ratio_For_19_2_MHz (CDClk);
+ when 38_400_000 => PLL_Ratio := Ratio_For_19_2_MHz (CDClk) / 2;
+ when 24_000_000 => PLL_Ratio := Ratio_For_24_MHz (CDClk);
+ when others => PLL_Ratio := 0;
+ end case;
+
+ if PLL_Ratio = 0 then
+ pragma Debug (Debug.Put_Line
+ ("ERROR: Invalid Refclk frequency, bad hardware?"));
+ return;
+ end if;
+
+ PCode.Mailbox_Request
+ (Mbox => TGL_PCODE_CDCLK_CONTROL,
+ Command => TGL_CDCLK_PREPARE_FOR_CHANGE,
+ Reply_Mask => TGL_CDCLK_READY_FOR_CHANGE,
+ Wait_Ready => True,
+ Success => Success);
+
+ if not Success then
+ pragma Debug (Debug.Put_Line
+ ("ERROR: PCODE not ready for frequency change."));
+ return;
+ end if;
+
+ Registers.Unset_Mask
+ (Register => Registers.CDCLK_PLL_ENABLE,
+ Mask => CDCLK_PLL_ENABLE_PLL_ENABLE);
+ Registers.Wait_Unset_Mask
+ (Register => Registers.CDCLK_PLL_ENABLE,
+ Mask => CDCLK_PLL_ENABLE_PLL_LOCK);
+
+ Registers.Write
+ (Register => Registers.CDCLK_PLL_ENABLE,
+ Value => Word32(PLL_Ratio));
+ Registers.Write
+ (Register => Registers.CDCLK_PLL_ENABLE,
+ Value => Word32(PLL_Ratio) or CDCLK_PLL_ENABLE_PLL_ENABLE);
+ Registers.Wait_Set_Mask
+ (Register => Registers.CDCLK_PLL_ENABLE,
+ Mask => CDCLK_PLL_ENABLE_PLL_LOCK,
+ Success => Success);
+
+ if not Success then
+ Debug.Put_Line ("CDClk PLL failed to lock!");
+ return;
+ end if;
+
+ VCO := (Refclk_Freq / 1_000) * Pos64(PLL_Ratio);
+ CD2X :=
+ (case (Div_Round_Closest (VCO, CDClk / 1_000)) is
+ when 2 => CDCLK_CD2X_DIV_SEL_1,
+ when 4 => CDCLK_CD2X_DIV_SEL_2,
+ when others => CDCLK_CD2X_DIV_SEL_1);
+
+ Registers.Write
+ (Register => Registers.CDCLK_CTL,
+ Value => (case CDClk is
+ when 168_000_000 => 16#14e#,
+ when 172_800_000 => 16#158#,
+ when 179_200_000 => 16#164#,
+ when 180_000_000 => 16#166#,
+ when 192_000_000 => 16#17e#,
+ when 307_200_000 => 16#264#,
+ when 312_000_000 => 16#26e#,
+ when 324_000_000 => 16#286#,
+ when 326_400_000 => 16#28b#,
+ when 480_000_000 => 16#3be#,
+ when 552_000_000 => 16#44e#,
+ when 556_800_000 => 16#458#,
+ when 648_000_000 => 16#50e#,
+ when 652_800_000 => 16#518#,
+ when others => CDCLK_CTL_CD_FREQ_DECIMAL (CDClk)) or
+ CDCLK_CD2X_PIPE_NONE or
+ CD2X);
+
+ PCode.Mailbox_Write
+ (MBox => TGL_PCODE_CDCLK_CONTROL,
+ Command => (if CDClk <= 312_000_000 then 0
+ elsif CDClk <= 326_400_000 then 1
+ elsif CDClk <= 556_800_000 then 2
+ else 3));
+ Config.CDClk := CDClk;
+ end Set_CDClk;
+
+ procedure Configure_Bandwidth_Buddy
+ is
+ BW_BUDDY_DISABLE : constant := 1 * 2 ** 31;
+ BW_BUDDY_TLB_REQ_TIMER_MASK : constant := 16#3f_0000#;
+
+ type DRAM_Module_Type is (DDR4, DDR5, LPDDR4, LPDDR5);
+ type Bw_Buddy_Info is record
+ DRAM_Channels : Natural;
+ DRAM_Type : DRAM_Module_Type;
+ BW_BUDDY_MASK : Word32;
+ end record;
+ type Bw_Buddy_Info_Array is array (Natural range 0 .. 3) of Bw_Buddy_Info;
+ Buddy_Info_Wa : constant Bw_Buddy_Info_Array :=
+ -- wa_1409767108_buddy_page_masks
+ ((1, DDR4, 1),
+ (1, LPDDR4, 1),
+ (2, DDR4, 3),
+ (2, LPDDR4, 3));
+ Buddy_Info : constant Bw_Buddy_Info_Array :=
+ -- tgl_buddy_page_masks
+ ((1, DDR4, 16#f#),
+ (2, LPDDR4, 16#1c#),
+ (2, DDR4, 16#1f#),
+ (4, LPDDR4, 16#1c#));
+ Result : Word64;
+ Module_Type: DRAM_Module_Type;
+ Channels : Natural;
+ Success : Boolean;
+ Found : Boolean := False;
+ begin
+ PCode.Mailbox_Read(MBox => TGL_PCODE_MEM_SUBSYSTEM_INFO or
+ TGL_PCODE_MEM_SS_READ_GLOBAL_INFO,
+ Wait_Ready => True,
+ Reply => Result,
+ Success => Success);
+ if not Success then
+ pragma Debug (Debug.Put_Line
+ ("ERROR: PCODE didn't return memory info."));
+ return;
+ end if;
+
+ case (Result and 16#f#) is
+ when 0 => Module_Type := DDR4;
+ when 1 => Module_Type := DDR5;
+ when 2 => Module_Type := LPDDR5;
+ when 3 => Module_Type := LPDDR4;
+ when others =>
+ pragma Debug (Debug.Put_Line ("ERROR: Invalid DRAM Module Type."));
+ return;
+ end case;
+
+ Channels := Natural (Shift_Right (Result and 16#f0#, 4));
+ for I in Buddy_Info'Range loop
+ if Buddy_Info (I).DRAM_Type = Module_Type and
+ Buddy_Info (I).DRAM_Channels = Channels
+ then
+ Registers.Set_Mask
+ (Register => Registers.BW_BUDDY1_PAGE_MASK,
+ Mask => Buddy_Info (I).BW_BUDDY_MASK);
+ Registers.Set_Mask
+ (Register => Registers.BW_BUDDY2_PAGE_MASK,
+ Mask => Buddy_Info (I).BW_BUDDY_MASK);
+
+ -- Wa_22010178259:tgl,rkl
+ Registers.Unset_And_Set_Mask
+ (Register => Registers.BW_BUDDY1_CTL,
+ Mask_Unset => BW_BUDDY_TLB_REQ_TIMER_MASK,
+ Mask_Set => 8 * 2 ** 16);
+ Registers.Unset_And_Set_Mask
+ (Register => Registers.BW_BUDDY2_CTL,
+ Mask_Unset => BW_BUDDY_TLB_REQ_TIMER_MASK,
+ Mask_Set => 8 * 2 ** 16);
+
+ Found := True;
+ end if;
+ exit when Found;
+ end loop;
+
+ if not Found then
+ Registers.Write (Registers.BW_BUDDY1_CTL, BW_BUDDY_DISABLE);
+ Registers.Write (Registers.BW_BUDDY2_CTL, BW_BUDDY_DISABLE);
+ end if;
+ end Configure_Bandwidth_Buddy;
+
+ ----------------------------------------------------------------------------
procedure Initialize is
+ procedure Get_Default_CDClk (CDClk: out Frequency_Type)
+ is
+ Refclk_Freq : Frequency_Type;
+ begin
+ Get_Refclk (Refclk_Freq);
+ case Refclk_Freq is
+ when 19_200_000 | 38_400_000 => CDClk := 172_800_000;
+ when others => CDClk := 180_000_000;
+ end case;
+ end Get_Default_CDClk;
+ Default_CDClk_Freq : Frequency_Type;
+ CDClk : Frequency_Type;
+ RawClk: Frequency_Type;
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+ Get_Default_CDClk(Default_CDClk_Freq);
+ -- USBC AUX is not supposed to be enabled until the connect flow
+ for AUX in reverse AUX_USBC1 .. AUX_USBC6 loop
+ PD_Off (AUX);
+ end loop;
+
+ Registers.Set_Mask
+ (Register => Registers.NDE_RSTWRN_OPT,
+ Mask => NDE_RSTWRN_OPT_RST_PCH_Handshake_En);
+
+ Combo_Phy.Initialize;
+
+ Registers.Wait_Set_Mask
+ (Register => Registers.FUSE_STATUS,
+ Mask => FUSE_STATUS_PG0_DIST_STATUS);
+ PD_On (PW1);
+
+ Get_Cur_CDClk (CDClk);
+ Config.CDClk := CDClk;
+ Get_Max_CDClk (Config.Max_CDClk);
+ if Config.CDClk /= Default_CDClk_Freq then
+ Set_CDClk (Default_CDClk_Freq);
+ end if;
+
+ Get_RawClk (Rawclk);
+ Config.Raw_Clock := RawClk;
+
+ for PW in PW2 .. PW4 loop
+ PD_On (PW);
+ end loop;
+
+ PD_On (DDI_A);
+ PD_On (AUX_A);
+
+ -- Enable first DBUF slice
+ Registers.Set_Mask (Registers.DBUF_CTL_S0, DBUF_CTL_DBUF_POWER_REQUEST);
+ Registers.Posting_Read (Registers.DBUF_CTL_S0);
+ Registers.Wait_Set_Mask (Registers.DBUF_CTL_S0, DBUF_CTL_DBUF_POWER_STATE);
+
+ for I in MBUS_ABOX_CTL'Range loop
+ Registers.Unset_And_Set_Mask
+ (Register => MBUS_ABOX_CTL (I),
+ Mask_Unset => MBUS_ABOX_MASK,
+ Mask_Set => MBUS_ABOX_CREDITS);
+ end loop;
+
+ -- Set DBUF Tracker State Service to 8
+ Registers.Unset_And_Set_Mask
+ (Register => Registers.DBUF_CTL_S0,
+ Mask_Unset => DBUF_CTL_TRACKER_STATE_SERVICE_MASK,
+ Mask_Set => 8 * 2 ** DBUF_CTL_TRACKER_STATE_SERVICE_SHIFT);
+ Registers.Unset_And_Set_Mask
+ (Register => Registers.DBUF_CTL_S2,
+ Mask_Unset => DBUF_CTL_TRACKER_STATE_SERVICE_MASK,
+ Mask_Set => 8 * 2 ** DBUF_CTL_TRACKER_STATE_SERVICE_SHIFT);
+
+ Configure_Bandwidth_Buddy;
+
+ -- Display WA #14011508470 tgl,dg1,rkl,adl-s,adl-p
+ Registers.Set_Mask
+ (Register => Registers.GEN11_CHICKEN_DCPR_2,
+ Mask => DCPR_MASK_MAXLATENCY_MEMUP_CLR or DCPR_MASK_LPMODE or
+ DCPR_SEND_RESP_IMM or DCPR_CLEAR_MEMSTAT_DIS);
end Initialize;
procedure Limit_Dotclocks
(Configs : in out Pipe_Configs;
- CDClk_Switch : out Boolean) is
+ CDClk_Switch : out Boolean)
+ is
+ CDClk : Frequency_Type;
begin
- CDClk_Switch := False;
- pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+ Config_Helpers.Limit_Dotclocks (Configs, Config.Max_CDClk);
+ Normalize_CDClk (Config_Helpers.Highest_Dotclock (Configs), CDClk);
+ CDClk_Switch := Config.CDClk /= CDClk;
end Limit_Dotclocks;
- procedure Update_CDClk (Configs : in out Pipe_Configs) is
+ procedure Update_CDClk (Configs : in out Pipe_Configs)
+ is
+ New_CDClk : constant Frequency_Type :=
+ Config_Helpers.Highest_Dotclock (Configs);
begin
- pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+ Set_CDClk (New_CDClk);
+ Config_Helpers.Limit_Dotclocks (Configs, Config.CDClk);
end Update_CDClk;
+ procedure Enable_CDClk
+ is
+ Refclk_Freq : Frequency_Type;
+ Bypass_Freq : Frequency_Type;
+ begin
+ Get_Refclk (Refclk_Freq);
+
+ if Config.CDClk = Refclk_Freq then
+ Bypass_Freq := Refclk_Freq / 2;
+ Set_CDClk (Bypass_Freq);
+ end if;
+ end Enable_CDClk;
+
procedure Power_Set_To (Configs : Pipe_Configs) is
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+ for PD in reverse Power_Domain loop
+ if not Need_PD (PD, Configs) then
+ PD_Off (PD);
+ end if;
+ end loop;
+
+ for PD in Power_Domain loop
+ if Need_PD (PD, Configs) then
+ PD_On (PD);
+ end if;
+ end loop;
end Power_Set_To;
- procedure Power_Up (Old_Configs, New_Configs : Pipe_Configs) is
+ procedure Power_Up (Old_Configs, New_Configs : Pipe_Configs)
+ is
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+ for PD in Power_Domain loop
+ if not Need_PD (PD, Old_Configs) and Need_PD (PD, New_Configs) then
+ PD_On (PD);
+ end if;
+ end loop;
end Power_Up;
procedure Power_Down (Old_Configs, Tmp_Configs, New_Configs : Pipe_Configs)
is
begin
pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+ for PD in reverse Power_Domain loop
+ if (Need_PD (PD, Old_Configs) or Need_PD (PD, Tmp_Configs)) and
+ not Need_PD (PD, New_Configs)
+ then
+ PD_Off (PD);
+ end if;
+ end loop;
+
end Power_Down;
+ procedure Pre_All_Off is
+ begin
+ Transcoder.PSR_Off;
+ end Pre_All_Off;
+
+ procedure Post_All_Off is
+ Refclk : Frequency_Type;
+ begin
+ pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+
+ Registers.Unset_Mask
+ (Registers.DBUF_CTL_S0, DBUF_CTL_DBUF_POWER_REQUEST);
+ Registers.Wait_Unset_Mask
+ (Registers.DBUF_CTL_S0, DBUF_CTL_DBUF_POWER_STATE);
+
+ -- Disable CD clock, bypass frequency is Refclk / 2
+ Get_Refclk (Refclk);
+ Set_CDClk (Refclk / 2);
+
+ for AUX in reverse AUX_A .. AUX_USBC6 loop
+ PD_Off (AUX);
+ end loop;
+
+ for DDI in reverse DDI_A .. DDI_USBC6 loop
+ PD_Off (DDI);
+ end loop;
+
+ for PW in reverse PW1 .. PW5 loop
+ PD_Off (PW);
+ end loop;
+
+ Combo_Phy.All_Off;
+ end Post_All_Off;
+
end HW.GFX.GMA.Power_And_Clocks;
diff --git a/common/tigerlake/hw-gfx-gma-power_and_clocks.ads b/common/tigerlake/hw-gfx-gma-power_and_clocks.ads
index 72854e8..b3302fb 100644
--- a/common/tigerlake/hw-gfx-gma-power_and_clocks.ads
+++ b/common/tigerlake/hw-gfx-gma-power_and_clocks.ads
@@ -16,29 +16,30 @@
private package HW.GFX.GMA.Power_And_Clocks is
- pragma Warnings (Off, "subprogram ""*"" has no effect",
- Reason => "Not yet implemented.");
+ subtype Refclk_Range is Frequency_Type range 19_200_000 .. 38_400_000;
+ subtype Refclk_Range_KHz is Pos64
+ range (Refclk_Range'First / 1000) .. (Refclk_Range'Last / 1000);
+
procedure Pre_All_Off;
procedure Post_All_Off;
procedure Initialize;
- pragma Warnings (Off, """Configs"" is not modified, could be IN",
- Reason => "Not yet implemented.");
procedure Limit_Dotclocks
(Configs : in out Pipe_Configs;
CDClk_Switch : out Boolean)
with
Post => Config_Helpers.Stable_FB (Configs'Old, Configs);
+
procedure Update_CDClk (Configs : in out Pipe_Configs)
with
Post => Config_Helpers.Stable_FB (Configs'Old, Configs);
- pragma Warnings (On, """Configs"" is not modified, could be IN");
- procedure Enable_CDClk is null;
+ procedure Enable_CDClk;
procedure Power_Set_To (Configs : Pipe_Configs);
procedure Power_Up (Old_Configs, New_Configs : Pipe_Configs);
procedure Power_Down (Old_Configs, Tmp_Configs, New_Configs : Pipe_Configs);
- pragma Warnings (On, "subprogram ""*"" has no effect");
+
+ procedure Get_Refclk (Refclk : out Refclk_Range);
end HW.GFX.GMA.Power_And_Clocks;
--
To view, visit https://review.coreboot.org/c/libgfxinit/+/82140?usp=email
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Gerrit-Project: libgfxinit
Gerrit-Branch: cros
Gerrit-Change-Id: I8f09696588aa73cebc7a44583ae5e029c705a535
Gerrit-Change-Number: 82140
Gerrit-PatchSet: 1
Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com>
Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com>
Gerrit-MessageType: newchange
1
0
[L] Change in libgfxinit[cros]: gma tgl: Add combo PHY programming sequence
by Dinesh Gehlot (Code Review) 30 Apr '24
by Dinesh Gehlot (Code Review) 30 Apr '24
30 Apr '24
Attention is currently required from: Tim Wawrzynczak.
Hello Tim Wawrzynczak,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/libgfxinit/+/82139?usp=email
to review the following change.
Change subject: gma tgl: Add combo PHY programming sequence
......................................................................
gma tgl: Add combo PHY programming sequence
This is required before any combo PHY ports can be used, so it will be
performed early in the modeset.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: Id0c2495872250e84057c3130cab19dea05a00b75
---
M common/tigerlake/Makefile.inc
A common/tigerlake/hw-gfx-gma-combo_phy.adb
A common/tigerlake/hw-gfx-gma-combo_phy.ads
3 files changed, 265 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/39/82139/1
diff --git a/common/tigerlake/Makefile.inc b/common/tigerlake/Makefile.inc
index b99a57e..e9ed51f 100644
--- a/common/tigerlake/Makefile.inc
+++ b/common/tigerlake/Makefile.inc
@@ -1,3 +1,5 @@
+gfxinit-y += hw-gfx-gma-combo_phy.adb
+gfxinit-y += hw-gfx-gma-combo_phy.ads
gfxinit-y += hw-gfx-gma-power_and_clocks.adb
gfxinit-y += hw-gfx-gma-power_and_clocks.ads
gfxinit-y += hw-gfx-gma-connectors.adb
diff --git a/common/tigerlake/hw-gfx-gma-combo_phy.adb b/common/tigerlake/hw-gfx-gma-combo_phy.adb
new file mode 100644
index 0000000..d732219
--- /dev/null
+++ b/common/tigerlake/hw-gfx-gma-combo_phy.adb
@@ -0,0 +1,243 @@
+--
+-- Copyright (C) 2022 Google, LLC
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with GNAT.Source_Info;
+with HW.Debug;
+with HW.GFX.GMA.Registers;
+
+package body HW.GFX.GMA.Combo_Phy is
+
+ PORT_PCS_DW1_DCC_MODE_SELECT_MASK : constant := 3 * 2 ** 20;
+ PORT_PCS_DW1_DCC_MODE_SELECT_CONTINUOUS : constant := 3 * 2 ** 20;
+ PORT_COMP_DW0_COMP_INIT : constant := 1 * 2 ** 31;
+ ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 : constant := 1 * 2 ** 29;
+ PORT_CL_DW5_POWER_DOWN_ENABLE : constant := 1 * 2 ** 4;
+ PHY_MISC_DE_TO_IO_COMP_PWR_DOWN : constant := 1 * 2 ** 23;
+ PORT_TX_DW8_ODCC_DIV_SEL_MASK : constant := 3 * 2 ** 29;
+ PORT_TX_DW8_ODCC_CLKSEL : constant := 1 * 2 ** 31;
+ PORT_COMP_DW8_IREFGEN : constant := 1 * 2 ** 24;
+ PORT_COMP_DW1_REF_MASK : constant := 16#ff_00ff#;
+
+ type Combo_Phy is (DDI_A, DDI_B, DDI_C);
+
+ type Phy_Regs_Record is record
+ PHY_MISC : Registers.Registers_Index;
+ PORT_CL_DW5 : Registers.Registers_Index;
+ PORT_COMP_DW0 : Registers.Registers_Index;
+ PORT_COMP_DW1 : Registers.Registers_Index;
+ PORT_COMP_DW3 : Registers.Registers_Index;
+ PORT_TX_DW8_LN0 : Registers.Registers_Index;
+ PORT_TX_DW8_GRP : Registers.Registers_Index;
+ PORT_PCS_DW1_LN0 : Registers.Registers_Index;
+ PORT_PCS_DW1_GRP : Registers.Registers_Index;
+ PORT_COMP_DW8 : Registers.Registers_Index;
+ PORT_COMP_DW9 : Registers.Registers_Index;
+ PORT_COMP_DW10 : Registers.Registers_Index;
+ end record;
+
+ type Combo_Phy_Regs is array (Combo_Phy) of Phy_Regs_Record;
+ Phy_Regs : constant Combo_Phy_Regs := Combo_Phy_Regs'
+ (DDI_A => Phy_Regs_Record'
+ (PHY_MISC => Registers.PHY_MISC_A,
+ PORT_CL_DW5 => Registers.PORT_CL_DW5_A,
+ PORT_COMP_DW0 => Registers.PORT_COMP_DW0_A,
+ PORT_COMP_DW1 => Registers.PORT_COMP_DW1_A,
+ PORT_COMP_DW3 => Registers.PORT_COMP_DW3_A,
+ PORT_TX_DW8_LN0 => Registers.PORT_TX_DW8_LN0_A,
+ PORT_TX_DW8_GRP => Registers.PORT_TX_DW8_GRP_A,
+ PORT_PCS_DW1_LN0 => Registers.PORT_PCS_DW1_LN0_A,
+ PORT_PCS_DW1_GRP => Registers.PORT_PCS_DW1_GRP_A,
+ PORT_COMP_DW8 => Registers.PORT_COMP_DW8_A,
+ PORT_COMP_DW9 => Registers.PORT_COMP_DW9_A,
+ PORT_COMP_DW10 => Registers.PORT_COMP_DW10_A),
+ DDI_B => Phy_Regs_Record'
+ (PHY_MISC => Registers.PHY_MISC_B,
+ PORT_CL_DW5 => Registers.PORT_CL_DW5_B,
+ PORT_COMP_DW0 => Registers.PORT_COMP_DW0_B,
+ PORT_COMP_DW1 => Registers.PORT_COMP_DW1_B,
+ PORT_COMP_DW3 => Registers.PORT_COMP_DW3_B,
+ PORT_TX_DW8_LN0 => Registers.PORT_TX_DW8_LN0_B,
+ PORT_TX_DW8_GRP => Registers.PORT_TX_DW8_GRP_B,
+ PORT_PCS_DW1_LN0 => Registers.PORT_PCS_DW1_LN0_B,
+ PORT_PCS_DW1_GRP => Registers.PORT_PCS_DW1_GRP_B,
+ PORT_COMP_DW8 => Registers.PORT_COMP_DW8_B,
+ PORT_COMP_DW9 => Registers.PORT_COMP_DW9_B,
+ PORT_COMP_DW10 => Registers.PORT_COMP_DW10_B),
+ DDI_C => Phy_Regs_Record'
+ (PHY_MISC => Registers.PHY_MISC_C,
+ PORT_CL_DW5 => Registers.PORT_CL_DW5_C,
+ PORT_COMP_DW0 => Registers.PORT_COMP_DW0_C,
+ PORT_COMP_DW1 => Registers.PORT_COMP_DW1_C,
+ PORT_COMP_DW3 => Registers.PORT_COMP_DW3_C,
+ PORT_TX_DW8_LN0 => Registers.PORT_TX_DW8_LN0_C,
+ PORT_TX_DW8_GRP => Registers.PORT_TX_DW8_GRP_C,
+ PORT_PCS_DW1_LN0 => Registers.PORT_PCS_DW1_LN0_C,
+ PORT_PCS_DW1_GRP => Registers.PORT_PCS_DW1_GRP_C,
+ PORT_COMP_DW8 => Registers.PORT_COMP_DW8_C,
+ PORT_COMP_DW9 => Registers.PORT_COMP_DW9_C,
+ PORT_COMP_DW10 => Registers.PORT_COMP_DW10_C));
+
+ procedure Config_DCC_SusClk (Phy : Combo_Phy)
+ is
+ DW8 : Word32;
+ DW1 : Word32;
+ begin
+ -- Read from lane 0 and write to the group
+ Registers.Read (Phy_Regs (Phy).PORT_TX_DW8_LN0, DW8);
+ DW8 := DW8 and not PORT_TX_DW8_ODCC_DIV_SEL_MASK;
+ DW8 := DW8 or PORT_TX_DW8_ODCC_CLKSEL;
+ DW8 := DW8 or ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2;
+ Registers.Write (Phy_Regs (Phy).PORT_TX_DW8_GRP, DW8);
+
+ Registers.Read (Phy_Regs (Phy).PORT_PCS_DW1_LN0, DW1);
+ DW1 := DW1 and not PORT_PCS_DW1_DCC_MODE_SELECT_MASK;
+ DW1 := DW1 or PORT_PCS_DW1_DCC_MODE_SELECT_CONTINUOUS;
+ Registers.Write (Phy_Regs (Phy).PORT_PCS_DW1_GRP, DW1);
+ end Config_DCC_SusClk;
+
+ procedure Config_Procmon_Reference (Phy : Combo_Phy)
+ is
+ type Procmon_Voltage is (VOLT_0_85, VOLT_0_95, VOLT_1_05);
+ type Procmon_Process is (DOT0, DOT1);
+ type Procmon_References is record
+ DW1 : Word32;
+ DW9 : Word32;
+ DW10 : Word32;
+ end record;
+
+ DOT0_VOLT_0_85 : constant Procmon_References :=
+ (DW1 => 16#0000_0000#,
+ DW9 => 16#62ab_67bb#,
+ DW10 => 16#5191_4f96#);
+ DOT0_VOLT_0_95 : constant Procmon_References :=
+ (DW1 => 16#0000_0000#,
+ DW9 => 16#86e1_72c7#,
+ DW10 => 16#77ca_5eab#);
+ DOT0_VOLT_1_05 : constant Procmon_References :=
+ (DW1 => 16#0000_0000#,
+ DW9 => 16#98fa_82dd#,
+ DW10 => 16#89e4_6dc1#);
+ DOT1_VOLT_0_95 : constant Procmon_References :=
+ (DW1 => 16#0000_0000#,
+ DW9 => 16#93f8_7fe1#,
+ DW10 => 16#8ae8_71c5#);
+ DOT1_VOLT_1_05 : constant Procmon_References :=
+ (DW1 => 16#0044_0000#,
+ DW9 => 16#9a00_ab25#,
+ DW10 => 16#8ae3_8ff1#);
+ procedure Read_DW3 (Phy : Combo_Phy; References : out Procmon_References)
+ is
+ DW3, Tmp : Word32;
+ Process : Procmon_Process;
+ Voltage : Procmon_Voltage;
+ PROCESS_MASK : constant := 7 * 2 ** 26;
+ VOLTAGE_MASK : constant := 3 * 2 ** 24;
+ begin
+ Registers.Read (Phy_Regs (Phy).PORT_COMP_DW3, DW3);
+
+ Tmp := Shift_Right (DW3 and VOLTAGE_MASK, 24);
+ case (Tmp) is
+ when 0 => Voltage := VOLT_0_85;
+ when 1 => Voltage := VOLT_0_95;
+ when 2 => Voltage := VOLT_1_05;
+ when others => Voltage := VOLT_0_85;
+ end case;
+
+ Tmp := Shift_Right (DW3 and PROCESS_MASK, 26);
+ case (Tmp) is
+ when 0 => Process := DOT0;
+ when 1 => Process := DOT1;
+ when others => Process := DOT0;
+ end case;
+
+ if Process = DOT0 then
+ case (Voltage) is
+ when VOLT_0_85 => References := DOT0_VOLT_0_85;
+ when VOLT_0_95 => References := DOT0_VOLT_0_95;
+ when VOLT_1_05 => References := DOT0_VOLT_1_05;
+ end case;
+ else
+ case (Voltage) is
+ -- [DOT1, VOLT_0_85] is actually an invalid combination
+ when VOLT_0_95 | VOLT_0_85 => References := DOT1_VOLT_0_95;
+ when VOLT_1_05 => References := DOT1_VOLT_1_05;
+ end case;
+ end if;
+ end Read_DW3;
+
+ References : Procmon_References;
+ begin
+ Read_DW3 (Phy, References);
+ Registers.Unset_And_Set_Mask (Register => Phy_Regs (Phy).PORT_COMP_DW1,
+ Mask_Unset => PORT_COMP_DW1_REF_MASK,
+ Mask_Set => References.DW1);
+ Registers.Write (Phy_Regs (Phy).PORT_COMP_DW9 , References.DW9);
+ Registers.Write (Phy_Regs (Phy).PORT_COMP_DW10, References.DW10);
+ end Config_Procmon_Reference;
+
+ function Phy_Is_Master (Phy : Combo_Phy) return Boolean is
+ begin
+ case Phy is
+ when DDI_A => return True;
+ when others => return False;
+ end case;
+ end Phy_Is_Master;
+
+ procedure Initialize
+ is
+ Was_Enabled : Boolean;
+ begin
+ pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity));
+ -- Initialize all combo PHYs with Combo PHY DDI Buffer Combo PHY Init Sequence
+ for Phy in Combo_Phy'range loop
+ Registers.Is_Set_Mask (
+ Phy_Regs (Phy).PORT_COMP_DW0,
+ PORT_COMP_DW0_COMP_INIT,
+ Was_Enabled);
+
+ if not Was_Enabled then
+ Config_DCC_SusClk (Phy);
+
+ Registers.Unset_Mask
+ (Phy_Regs (Phy).PHY_MISC,
+ PHY_MISC_DE_TO_IO_COMP_PWR_DOWN);
+
+ Config_Procmon_Reference (Phy);
+
+ if Phy_Is_Master (Phy) then
+ Registers.Set_Mask (Register => Phy_Regs (Phy).PORT_COMP_DW8,
+ Mask => PORT_COMP_DW8_IREFGEN);
+ end if;
+
+ Registers.Set_Mask (Register => Phy_Regs (Phy).PORT_COMP_DW0,
+ Mask => PORT_COMP_DW0_COMP_INIT);
+
+ Registers.Set_Mask (Register => Phy_Regs (Phy).PORT_CL_DW5,
+ Mask => PORT_CL_DW5_POWER_DOWN_ENABLE);
+ end if;
+ end loop;
+ end Initialize;
+
+ procedure All_Off is
+ begin
+ for Phy in Combo_Phy'range loop
+ Registers.Set_Mask (Phy_Regs (Phy).PHY_MISC,
+ PHY_MISC_DE_TO_IO_COMP_PWR_DOWN);
+
+ Registers.Unset_Mask (Phy_Regs (Phy).PORT_COMP_DW0,
+ PORT_COMP_DW0_COMP_INIT);
+ end loop;
+ end All_Off;
+
+end HW.GFX.GMA.Combo_Phy;
diff --git a/common/tigerlake/hw-gfx-gma-combo_phy.ads b/common/tigerlake/hw-gfx-gma-combo_phy.ads
new file mode 100644
index 0000000..ed3b05d
--- /dev/null
+++ b/common/tigerlake/hw-gfx-gma-combo_phy.ads
@@ -0,0 +1,20 @@
+--
+-- Copyright (C) 2022 Google, LLC
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+private package HW.GFX.GMA.Combo_Phy is
+
+ procedure Initialize;
+ procedure All_Off;
+
+end HW.GFX.GMA.Combo_Phy;
--
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Gerrit-Project: libgfxinit
Gerrit-Branch: cros
Gerrit-Change-Id: Id0c2495872250e84057c3130cab19dea05a00b75
Gerrit-Change-Number: 82139
Gerrit-PatchSet: 1
Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com>
Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com>
Gerrit-MessageType: newchange
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