Attention is currently required from: Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu, Ziang Wang.
Hello Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, Ziang Wang, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#7).
The following approvals got outdated and were removed:
Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins)
Change subject: soc/intel/xeon_sp: Add device to proximity domain map utils
......................................................................
soc/intel/xeon_sp: Add device to proximity domain map utils
In NUMA architecture, all devices (cpu, memory and PCI device)
belong to specific proximity domain. Add utils to map device
instance to their proximity domain.
Proximity domain ID is the index assigned at the creation of
proximity domains. There is no hard relationship between proximity
domain ID and the device identities (e.g. socket ID). Hence we
need the map utils to explicitly link them.
For now the Sub-NUMA config isn't taken into account.
TEST=Build and boot on intel/archercity CRB
Change-Id: Icd14a98823491ccfc38473e44a26dddfbbcaa7c0
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Co-authored-by: Ziang Wang <ziang.wang(a)intel.com>
Co-authored-by: Gang Chen <gang.c.chen(a)intel.com>
---
M src/soc/intel/xeon_sp/include/soc/numa.h
M src/soc/intel/xeon_sp/numa.c
M src/soc/intel/xeon_sp/spr/soc_acpi.c
M src/soc/intel/xeon_sp/uncore_acpi.c
M src/soc/intel/xeon_sp/uncore_acpi_cxl.c
5 files changed, 59 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/81440/7
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Attention is currently required from: Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu, Ziang Wang.
Hello Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, Ziang Wang, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins)
Change subject: soc/intel/xeon_sp: Make NUMA support by default
......................................................................
soc/intel/xeon_sp: Make NUMA support by default
TEST=Build and boot on intel/archercity CRB
Change-Id: I84f07c16e24e441a885144df8c805f1310acae29
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Co-authored-by: Ziang Wang <ziang.wang(a)intel.com>
Co-authored-by: Gang Chen <gang.c.chen(a)intel.com>
---
M src/soc/intel/xeon_sp/Makefile.mk
M src/soc/intel/xeon_sp/cpx/soc_util.c
M src/soc/intel/xeon_sp/numa.c
M src/soc/intel/xeon_sp/skx/soc_util.c
M src/soc/intel/xeon_sp/uncore.c
5 files changed, 20 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/81439/6
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79684?usp=email )
Change subject: payloads/iPXE: add TRUST_CMD switch
......................................................................
Patch Set 7:
(2 comments)
File payloads/external/iPXE/Kconfig:
https://review.coreboot.org/c/coreboot/+/79684/comment/d236d06b_98f201ad :
PS5, Line 112: config PXE_CUSTOM_BUILD_ID
> Yess, fixed [here](https://review.coreboot.org/c/coreboot/+/79684/5.. […]
Done
File payloads/external/iPXE/Kconfig:
https://review.coreboot.org/c/coreboot/+/79684/comment/2e0091aa_fd5859c2 :
PS7, Line 114: depends on BUILD_IPXE
not needed, remove. it's already guarded by if.
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Hello Angel Pons, Felix Held, Jérémy Compostella, Patrick Rudolph, Shuo Liu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/82148?usp=email
to look at the new patch set (#2).
Change subject: arch/x86: Include page tables in each stage
......................................................................
arch/x86: Include page tables in each stage
Change-Id: Iefe0429db7d6ef5c434beffd39aacaf7a72ce244
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/assembly_entry.S
M src/arch/x86/c_start.S
2 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/82148/2
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Change subject: Makefile.mk: Align romstage to page directory pointer requirements
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
@Appukuttan, could you check if this resolve your issue?
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Change subject: Makefile.mk: Align romstage to page directory pointer requirements
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82102/comment/fcd00a3a_a710925c :
PS1, Line 10: an
> a
Done
https://review.coreboot.org/c/coreboot/+/82102/comment/bf1e9a10_f26ed2e3 :
PS1, Line 10: which have an larger alignment requirement.
> … So, increase them from 64 bytes to 4 kB.
Done
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Change subject: Makefile.mk: Align romstage to page directory pointer requirements
......................................................................
Makefile.mk: Align romstage to page directory pointer requirements
On x86_64 romstage can contain page tables and a page table pointer
which have a larger alignment requirement. So, increase them from 64 bytes to 4 kB.
Change-Id: I94e4a4209b7441ecb2966a1342c3d46625771bb8
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M Makefile.mk
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/82102/2
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