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Change subject: arch/x86: Use a new page tables in each stage
......................................................................
arch/x86: Use a new page tables in each stage
Change-Id: Iefe0429db7d6ef5c434beffd39aacaf7a72ce244
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/assembly_entry.S
M src/arch/x86/c_start.S
2 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/82148/3
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Change subject: soc/intel/xeon_sp: Make NUMA support by default
......................................................................
Patch Set 7: Code-Review+2
(1 comment)
File src/soc/intel/xeon_sp/numa.c:
https://review.coreboot.org/c/coreboot/+/81439/comment/b350ef77_0878fc6b :
PS7, Line 75: #if CONFIG(SOC_INTEL_HAS_CXL)
> I have to use macro again since otherwise, the SoCs without CXL_NODE_INFO defined in their FSP heade […]
Ack, I thought this might be a possibility. I might refactor this in the future
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Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
......................................................................
Patch Set 58:
(1 comment)
Patchset:
PS58:
> For this one, seems no new opens, should we close the threads and move ahead?
@Nico thoughts about the resource reporting?
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Change subject: soc/intel/xeon_sp: Make NUMA support by default
......................................................................
Patch Set 7:
(1 comment)
File src/soc/intel/xeon_sp/numa.c:
https://review.coreboot.org/c/coreboot/+/81439/comment/64b36a5f_06ec8e68 :
PS7, Line 75: #if CONFIG(SOC_INTEL_HAS_CXL)
I have to use macro again since otherwise, the SoCs without CXL_NODE_INFO defined in their FSP headers cannot pass build.
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Code-Review+1 by Angel Pons
Change subject: soc/intel/xeon_sp: Make NUMA support by default
......................................................................
soc/intel/xeon_sp: Make NUMA support by default
TEST=Build and boot on intel/archercity CRB
Change-Id: I84f07c16e24e441a885144df8c805f1310acae29
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
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---
M src/soc/intel/xeon_sp/Makefile.mk
M src/soc/intel/xeon_sp/cpx/soc_util.c
M src/soc/intel/xeon_sp/numa.c
M src/soc/intel/xeon_sp/skx/soc_util.c
M src/soc/intel/xeon_sp/uncore.c
5 files changed, 21 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/81439/7
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Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
......................................................................
Patch Set 58:
(1 comment)
Patchset:
PS58:
For this one, seems no new opens, should we close the threads and move ahead?
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Change subject: soc/intel/xeon_sp: Add device to proximity domain map utils
......................................................................
Patch Set 9: Code-Review+2
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Change subject: soc/intel/xeon_sp: Remove unused xeonsp_acpi_create_madt_lapics
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82110/comment/2763e95b_394adc80 :
PS1, Line 9: Remove
> Remove unused xeonsp_acpi_create_madt_lapics.
Done
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Change subject: soc/intel/xeon_sp: Add device to proximity domain map utils
......................................................................
Patch Set 9:
(4 comments)
File src/soc/intel/xeon_sp/include/soc/numa.h:
https://review.coreboot.org/c/coreboot/+/81440/comment/f1d8d057_4fac397c :
PS7, Line 13: XEONSP_PROXIMITY_DOMAIN_MAX
> `XEONSP_INVALID_PD_INDEX` maybe?
Done
File src/soc/intel/xeon_sp/numa.c:
https://review.coreboot.org/c/coreboot/+/81440/comment/35b6fe15_aabfdfa7 :
PS7, Line 129: not finding
> could not find
Done
https://review.coreboot.org/c/coreboot/+/81440/comment/8f878635_62163343 :
PS7, Line 137: bounded
> nit: `bound` (`bind` is an irregular verb)
Done
https://review.coreboot.org/c/coreboot/+/81440/comment/3097faa4_3b9ea39c :
PS7, Line 149: not finding
> could not find
Done
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