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Code-Review+2 by Lean Sheng Tan
Change subject: soc/intel/xeon_sp: Add get_cxl_mode
......................................................................
soc/intel/xeon_sp: Add get_cxl_mode
Configuration variable implementation (VPD, et al) is regarded to
be mainboard specific and should not be bounded to SoC codes.
Add get_cxl_mode so that SoC codes do not need to get this
configuration from VPD any more.
TEST=Build and boot on intel/archercity CRB with no significant log
differences
Change-Id: I1e08e92ad769112d7e570ee12cf973451a3befc0
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M src/drivers/ocp/include/vpd.h
M src/mainboard/intel/archercity_crb/Makefile.mk
A src/mainboard/intel/archercity_crb/util.c
M src/mainboard/inventec/transformers/Makefile.mk
A src/mainboard/inventec/transformers/util.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/include/soc/util.h
M src/soc/intel/xeon_sp/spr/romstage.c
M src/soc/intel/xeon_sp/uncore.c
M src/soc/intel/xeon_sp/util.c
10 files changed, 78 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/82092/9
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Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82115?usp=email )
Change subject: soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZE
......................................................................
Patch Set 3: Code-Review+2
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Hello Hung-Te Lin, Mingjin Ge, Xuxin Xiong, Yang Wu, Yidi Lin, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/corsola: Initialize USB port 0
......................................................................
mb/google/corsola: Initialize USB port 0
The default MT8186 platform is to initialize USB3 port 1.
Use option bit 27 in fw_config to enable initialization of USB2 port 0
to support devices mounted on it.
BUG=b:335124437
TEST=boot to OS from USB-A
boot to OS from SD Card
BRANCH=corsola
Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134
Signed-off-by: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/corsola/devicetree.cb
M src/mainboard/google/corsola/mainboard.c
M src/soc/mediatek/common/include/soc/usb_common.h
M src/soc/mediatek/common/usb.c
A src/soc/mediatek/common/usb_secondary.c
M src/soc/mediatek/mt8186/Makefile.mk
M src/soc/mediatek/mt8186/include/soc/addressmap.h
7 files changed, 43 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/82089/13
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Wentao Qin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82089?usp=email )
Change subject: mb/google/corsola: Add initialize USB port 0
......................................................................
Patch Set 12:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82089/comment/72dbc84d_dab808cd :
PS11, Line 7: /var/wugtrio
> Actually, this patch uses fw_config to decide the initialization, and isn't directly related to a pa […]
Done
https://review.coreboot.org/c/coreboot/+/82089/comment/dff4fb1a_7258248e :
PS11, Line 10: option 27th in fwconfig
> bit 27 in fw_config
Done
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/corsola: Add initialize USB port 0
......................................................................
mb/google/corsola: Add initialize USB port 0
The default MT8186 platform is to initialize USB3 port 1.
Use option bit 27 in fw_config to enable initialization of USB2 port 0
to support devices mounted on it.
BUG=b:335124437
TEST=boot to OS from USB-A
boot to OS from SD Card
BRANCH=corsola
Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134
Signed-off-by: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/corsola/devicetree.cb
M src/mainboard/google/corsola/mainboard.c
M src/soc/mediatek/common/include/soc/usb_common.h
M src/soc/mediatek/common/usb.c
A src/soc/mediatek/common/usb_secondary.c
M src/soc/mediatek/mt8186/Makefile.mk
M src/soc/mediatek/mt8186/include/soc/addressmap.h
7 files changed, 43 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/82089/12
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Eren Peng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82108?usp=email )
Change subject: mb/google/brox/var/greenbayupoc: Add data.vbt
......................................................................
mb/google/brox/var/greenbayupoc: Add data.vbt
Copy the data.vbt from brox to greenbayupoc
BUG=b:326413034
TEST=emerge-brox coreboot chromeos-bootimage, flash and boot on DUT
Change-Id: I1e8101519ab2ecbb4654c20485fbe83c90656e4d
Signed-off-by: Eren Peng <peng.eren(a)inventec.corp-partner.google.com>
---
A src/mainboard/google/brox/variants/greenbayupoc/data.vbt
1 file changed, 0 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/82108/1
diff --git a/src/mainboard/google/brox/variants/greenbayupoc/data.vbt b/src/mainboard/google/brox/variants/greenbayupoc/data.vbt
new file mode 100644
index 0000000..716d09f
--- /dev/null
+++ b/src/mainboard/google/brox/variants/greenbayupoc/data.vbt
Binary files differ
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82116?usp=email )
Change subject: doc/release/24.05: Add git submodule updates
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
Let's hold this a little bit longer just in case another submodule update sneaks in.
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