coreboot-gerrit April 2024

coreboot-gerrit@coreboot.org

1 participants
3293 discussions

[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned
by Appukuttan V K (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Arthur Heymans, Felix Held, Krishna P Bhat D, Subrata Banik, Wonkyu Kim. Appukuttan V K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81661?usp=email ) Change subject: drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned ...................................................................... Patch Set 14: (1 comment) File src/drivers/intel/fsp2_0/memory_init.c: https://review.coreboot.org/c/coreboot/+/81661/comment/a157da69_b3744136 : PS6, Line 37: static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(16); > i'd align the stack to 16 bytes in all cases just to be on the safe side and not have different case […] Thanks Felix. I am making it 16 for both x32 and x64 to be on the safe side as you have suggested. We might end up having few bytes of unused memory in x32 mode due to the 16bytes alignment and I guess that would not have any major impact. -- To view, visit https://review.coreboot.org/c/coreboot/+/81661?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86048c5d3623a29f17a5e492cd67568e4844589c Gerrit-Change-Number: 81661 Gerrit-PatchSet: 14 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 29 Apr 2024 06:12:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Appukuttan V K <appukuttan.vk(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned
by Appukuttan V K (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Appukuttan V K, Arthur Heymans, Krishna P Bhat D, Subrata Banik, Wonkyu Kim. Hello Andrey Petrov, Krishna P Bhat D, Ronak Kanabar, Subrata Banik, Wonkyu Kim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81661?usp=email to look at the new patch set (#14). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned ...................................................................... drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned - Stack alignment: 1. FSP functions must be called with the stack 16-bytes aligned in x86_64 mode.This is already setup properly with the default value of the `mpreferred-stack-boundary' compiler option (4). 2. The FSP heap buffer supplied by coreboot through the `StackBase' UPD must be 16-bytes aligned. This alignment is consistent for both x86_64 and x86_32 modes to simplify the implementation. BUG=b:329034258 TEST=Verified on Meteor Lake board (Rex) Change-Id: I86048c5d3623a29f17a5e492cd67568e4844589c Signed-off-by: Appukuttan V K <appukuttan.vk(a)intel.com> --- M src/drivers/intel/fsp2_0/memory_init.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/81661/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/81661?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86048c5d3623a29f17a5e492cd67568e4844589c Gerrit-Change-Number: 81661 Gerrit-PatchSet: 14 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[main]: block/fast_spi: Use read32p/write32p for SPI RW
by Ashish Kumar Mishra (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Arthur Heymans, Ashish Kumar Mishra, Paul Menzel, Saurabh Mishra, Subrata Banik. Hello Saurabh Mishra, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82079?usp=email to look at the new patch set (#4). Change subject: block/fast_spi: Use read32p/write32p for SPI RW ...................................................................... block/fast_spi: Use read32p/write32p for SPI RW The current fast_spi code uses memcpy for rw. The SPI flash read/write has 4 byte limit, due to which the current 64 bit memcpy doesn't work. Hence update rw ops to use read32p/write32p. BUG=b:242829490 TEST=Build and boot mtl 64-bit and verified MRC cache working. Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> --- M src/soc/intel/common/block/fast_spi/fast_spi_flash.c 1 file changed, 16 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/82079/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/82079?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420 Gerrit-Change-Number: 82079 Gerrit-PatchSet: 4 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[main]: block/fast_spi: Use read32p/write32p for spi rw
by Ashish Kumar Mishra (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Arthur Heymans, Ashish Kumar Mishra, Paul Menzel, Saurabh Mishra, Subrata Banik. Hello Saurabh Mishra, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82079?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: block/fast_spi: Use read32p/write32p for spi rw ...................................................................... block/fast_spi: Use read32p/write32p for spi rw The current fast_spi code uses memcpy for rw. The SPI flash read/write has 4 byte limit, due to which the current 64 bit memcpy doesn't work. Hence update rw ops to use read32p/write32p. BUG=b:242829490 TEST=Build and boot mtl 64-bit and verified MRC cache working. Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> --- M src/soc/intel/common/block/fast_spi/fast_spi_flash.c 1 file changed, 16 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/82079/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/82079?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420 Gerrit-Change-Number: 82079 Gerrit-PatchSet: 3 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[main]: mb/google/corsola/wugtrio: Add initialization of USB port0
by Wentao Qin (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Hung-Te Lin, Mingjin Ge, Paul Menzel, Xuxin Xiong, Yang Wu, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Mingjin Ge, Xuxin Xiong, Yang Wu, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82089?usp=email to look at the new patch set (#7). Change subject: mb/google/corsola/wugtrio: Add initialization of USB port0 ...................................................................... mb/google/corsola/wugtrio: Add initialization of USB port0 Initialize USB2 port0 to support the SD card and detachable keyboard functions mounted on port0 during the coreboot stage. BUG=b:335124437 TEST=boot to OS from USB-A boot to OS from SD Card BRANCH=corsola Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Signed-off-by: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/corsola/devicetree.cb M src/mainboard/google/corsola/mainboard.c M src/soc/mediatek/common/include/soc/usb_common.h M src/soc/mediatek/common/usb.c A src/soc/mediatek/common/usb_secondary.c M src/soc/mediatek/mt8186/Makefile.mk M src/soc/mediatek/mt8186/include/soc/addressmap.h 7 files changed, 34 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/82089/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/82089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Gerrit-Change-Number: 82089 Gerrit-PatchSet: 7 Gerrit-Owner: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[main]: mb/google/corsola/wugtrio: Add initialization of USB port0
by Wentao Qin (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Hung-Te Lin, Mingjin Ge, Paul Menzel, Xuxin Xiong, Yang Wu, Yidi Lin, Yu-Ping Wu. Wentao Qin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82089?usp=email ) Change subject: mb/google/corsola/wugtrio: Add initialization of USB port0 ...................................................................... Patch Set 6: (2 comments) File src/mainboard/google/corsola/devicetree.cb: https://review.coreboot.org/c/coreboot/+/82089/comment/93e01f64_fb8a5b40 : PS4, Line 4: USB2_PORT1 > Revise the naming. […] Done File src/soc/mediatek/common/usb.c: https://review.coreboot.org/c/coreboot/+/82089/comment/ebb24c84_ffd41e67 : PS4, Line 15: : #ifdef SOC_MEDIATEK_MT8186_USB_H : void switch_usb_port0_host(void) : { : ippc_regs = (void *)(SSUSB_IPPC_BASE_P0); : phy_ports = (void *)(SSUSB_SIF_BASE_P0); : } : #endif : > Please consider the following approach. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Gerrit-Change-Number: 82089 Gerrit-PatchSet: 6 Gerrit-Owner: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 29 Apr 2024 04:54:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: mb/google/corsola/wugtrio: Add initialization of USB port0
by Wentao Qin (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Hung-Te Lin, Mingjin Ge, Paul Menzel, Wentao Qin, Xuxin Xiong, Yang Wu, Yu-Ping Wu. Hello Hung-Te Lin, Mingjin Ge, Xuxin Xiong, Yang Wu, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82089?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/google/corsola/wugtrio: Add initialization of USB port0 ...................................................................... mb/google/corsola/wugtrio: Add initialization of USB port0 Initialize USB2 port0 to support the SD card and detachable keyboard functions mounted on port0 during the coreboot stage. BUG=b:335124437 TEST=boot to OS from USB-A boot to OS from SD Card BRANCH=corsola Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Signed-off-by: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/corsola/devicetree.cb M src/mainboard/google/corsola/mainboard.c M src/soc/mediatek/common/include/soc/usb_common.h M src/soc/mediatek/common/usb.c A src/soc/mediatek/common/usb_secondary.c M src/soc/mediatek/mt8186/Makefile.mk M src/soc/mediatek/mt8186/include/soc/addressmap.h 7 files changed, 34 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/82089/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/82089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Gerrit-Change-Number: 82089 Gerrit-PatchSet: 6 Gerrit-Owner: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[main]: mb/google/corsola/wugtrio: Add initialization of USB port0
by Wentao Qin (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Hung-Te Lin, Mingjin Ge, Paul Menzel, Wentao Qin, Xuxin Xiong, Yang Wu, Yu-Ping Wu. Hello Hung-Te Lin, Mingjin Ge, Xuxin Xiong, Yang Wu, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82089?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Code-Review+1 by Mingjin Ge, Code-Review+1 by Xuxin Xiong, Verified+1 by build bot (Jenkins) Change subject: mb/google/corsola/wugtrio: Add initialization of USB port0 ...................................................................... mb/google/corsola/wugtrio: Add initialization of USB port0 Initialize USB2 port0 to support the SD card and detachable keyboard functions mounted on port0 during the coreboot stage. BUG=b:335124437 TEST=boot to OS from USB-A boot to OS from SD Card BRANCH=corsola Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Signed-off-by: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/corsola/devicetree.cb M src/mainboard/google/corsola/mainboard.c M src/soc/mediatek/common/include/soc/usb_common.h M src/soc/mediatek/common/usb.c A src/soc/mediatek/common/usb_secondary.c M src/soc/mediatek/mt8186/Makefile.mk M src/soc/mediatek/mt8186/include/soc/addressmap.h 7 files changed, 32 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/82089/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/82089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Gerrit-Change-Number: 82089 Gerrit-PatchSet: 5 Gerrit-Owner: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[main]: Documentation/releases: Add coreboot-24.xx-relnotes
by Elyes Haouas (Code Review) 29 Apr '24

29 Apr '24

Elyes Haouas has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/81999?usp=email ) Change subject: Documentation/releases: Add coreboot-24.xx-relnotes ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/81999?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I35039bd0af8c6f199cd5ad10d13780376f371bd5 Gerrit-Change-Number: 81999 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

1 0

[XS] Change in coreboot[main]: mb/google/brya/var/xol: Add EC_IN_RW_OD config into early_gpio_table
by Eric Lai (Code Review) 29 Apr '24

29 Apr '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, SH Kim, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82099?usp=email ) Change subject: mb/google/brya/var/xol: Add EC_IN_RW_OD config into early_gpio_table ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/82099?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2179bb10b431547bc35f332c74915a63495b779d Gerrit-Change-Number: 82099 Gerrit-PatchSet: 2 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 29 Apr 2024 03:38:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2024