coreboot-gerrit April 2024

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[XS] Change in coreboot[main]: mb/hp/280_g2: Fix comment in `gma-mainboard.ads`
by Nico Huber (Code Review) 28 Apr '24

28 Apr '24

Attention is currently required from: Angel Pons. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82112?usp=email ) Change subject: mb/hp/280_g2: Fix comment in `gma-mainboard.ads` ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82112?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I74c1257efb67cfdff2ae04a42c163dd320c850a4 Gerrit-Change-Number: 82112 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 28 Apr 2024 20:47:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Disable FSP UPDs related to virtualization
by Angel Pons (Code Review) 28 Apr '24

28 Apr '24

Attention is currently required from: Subrata Banik. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67452?usp=email ) Change subject: soc/intel/meteorlake: Disable FSP UPDs related to virtualization ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/meteorlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/67452/comment/53f37efe_2e4b1bd5 : PS2, Line 241: if (cpuid == CPUID_METEORLAKE_A0_1 || cpuid == CPUID_METEORLAKE_A0_2) { Given this CPUID check, I guess this is a workaround for some early silicon bugs? -- To view, visit https://review.coreboot.org/c/coreboot/+/67452?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21e178a93e311889f2ab7d1a08230d21b051f45e Gerrit-Change-Number: 67452 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Sun, 28 Apr 2024 20:08:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: [WIP] mb/hp/280_g2: Make VGA port work
by Angel Pons (Code Review) 28 Apr '24

28 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82114?usp=email ) Change subject: [WIP] mb/hp/280_g2: Make VGA port work ...................................................................... [WIP] mb/hp/280_g2: Make VGA port work On this board, VGA comes from a RTD2168 DP-to-VGA chip, which is connected to the CPU's DDI-E output. Enable bifurcation (so that DDI-E gets 2 lanes) and correct the port in `gma-mainboard.ads`. INFORMATION IS ACCURATE, BUT THIS IS NOT YET TESTED. Change-Id: I747e770707748496ba1aa58062947b28573ca781 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/hp/280_g2/Kconfig M src/mainboard/hp/280_g2/gma-mainboard.ads 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/82114/1 diff --git a/src/mainboard/hp/280_g2/Kconfig b/src/mainboard/hp/280_g2/Kconfig index 0db753d..561c023 100644 --- a/src/mainboard/hp/280_g2/Kconfig +++ b/src/mainboard/hp/280_g2/Kconfig @@ -12,6 +12,7 @@ select MAINBOARD_HAS_LIBGFXINIT select SKYLAKE_SOC_PCH_H select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_GFX_ENABLE_DDI_E_BIFURCATION select SOC_INTEL_KABYLAKE select SPD_READ_BY_WORD select SUPERIO_ITE_COMMON_PRE_RAM diff --git a/src/mainboard/hp/280_g2/gma-mainboard.ads b/src/mainboard/hp/280_g2/gma-mainboard.ads index 0628211..cd5bcf2 100644 --- a/src/mainboard/hp/280_g2/gma-mainboard.ads +++ b/src/mainboard/hp/280_g2/gma-mainboard.ads @@ -10,7 +10,7 @@ ports : constant Port_List := (HDMI3, -- DVI-D - eDP, -- VGA + Analog, -- VGA (via RTD2168 DP-to-VGA chip) others => Disabled); end GMA.Mainboard; -- To view, visit https://review.coreboot.org/c/coreboot/+/82114?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I747e770707748496ba1aa58062947b28573ca781 Gerrit-Change-Number: 82114 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/intel/cmn/graphics: Make DDI-A 4 lanes configurable
by Angel Pons (Code Review) 28 Apr '24

28 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82113?usp=email ) Change subject: soc/intel/cmn/graphics: Make DDI-A 4 lanes configurable ...................................................................... soc/intel/cmn/graphics: Make DDI-A 4 lanes configurable As described in Intel document 336464 (8th gen S series datasheet volume 1), the CPU's 4 eDP lanes can be bifurcated, so that DDI-A (eDP) ends up with 2 lanes, and DDI-E (DP, typically used for VGA) has the remaining 2 lanes. This lets mainboards provide a VGA output without sacrificing one of the main 4-lane DDIs. Newer platforms seem to be lacking this. However, the way this is structured in coreboot does not allow boards to choose whether bifurcation should be enabled. Most boards in the tree do not use DDI-E (it doesn't exist on mobile platforms), but there are some boards (e.g. hp/280_g2) that use DDI-E and a DP-to-VGA converter chip to provide a VGA output. Replace `SOC_INTEL_CONFIGURE_DDI_A_4_LANES` with two new Kconfig options to allow boards to decide. Use `SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION` to specify whether a platform supports DDI-A bifurcation at all (do nothing otherwise, maintaining the original code's behaviour). If bifurcation is supported, the `SOC_INTEL_GFX_ENABLE_DDI_E_BIFURCATION` is used to clear or set the `DDI_A_4_LANES` bit in the `DDI_BUF_CTL_A` register. Change-Id: I516538db77509209d371f3f49c920476e06b052f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/graphics/Kconfig M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/skylake/Kconfig 4 files changed, 31 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/82113/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 7548e46..3aa06f4 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -64,7 +64,7 @@ select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET - select SOC_INTEL_CONFIGURE_DDI_A_4_LANES + select SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/common/block/graphics/Kconfig b/src/soc/intel/common/block/graphics/Kconfig index b5776b0..eaa429e 100644 --- a/src/soc/intel/common/block/graphics/Kconfig +++ b/src/soc/intel/common/block/graphics/Kconfig @@ -8,10 +8,20 @@ if SOC_INTEL_COMMON_BLOCK_GRAPHICS -config SOC_INTEL_CONFIGURE_DDI_A_4_LANES +config SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION bool help - Selected by platforms that require DDI-A bifurcation setup. + Skylake, Kaby Lake and Coffee Lake desktop CPUs support eDP + bifurcation, i.e. 4 eDP lanes get split between DDI-A (eDP) + and DDI-E (DP, used for VGA). Selected from SoC Kconfig, if + applicable. + +config SOC_INTEL_GFX_ENABLE_DDI_E_BIFURCATION + bool + depends on SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION + help + Selected by mainboards that use DDI-E, which is most commonly + used to drive a DP-to-VGA adapter to provide a VGA connector. config SOC_INTEL_DISABLE_IGD bool "Disable Integrated GFX Controller (0:2:0)" diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index eabcb9a..151d38b 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -124,6 +124,21 @@ return graphics_get_framebuffer_address() && get_external_display_status(); } +static void configure_ddi_a_bifurcation(void) +{ + u32 ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); + /* Only program if the buffer is not enabled yet. */ + if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) + return; + + if (CONFIG(SOC_INTEL_GFX_ENABLE_DDI_E_BIFURCATION)) + ddi_buf_ctl &= ~DDI_A_4_LANES; + else + ddi_buf_ctl |= DDI_A_4_LANES; + + graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); +} + static void gma_init(struct device *const dev) { intel_gma_init_igd_opregion(); @@ -135,12 +150,8 @@ if (!CONFIG(RUN_FSP_GOP)) graphics_soc_panel_init(dev); - if (CONFIG(SOC_INTEL_CONFIGURE_DDI_A_4_LANES) && !acpi_is_wakeup_s3()) { - const u32 ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); - /* Only program if the buffer is not enabled yet. */ - if (!(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) - graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl | DDI_A_4_LANES); - } + if (CONFIG(SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION) && !acpi_is_wakeup_s3()) + configure_ddi_a_bifurcation(); /* * GFX PEIM module inside FSP binary is taking care of graphics diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 0d38804..3ec84ab 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -62,7 +62,7 @@ select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT - select SOC_INTEL_CONFIGURE_DDI_A_4_LANES + select SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER -- To view, visit https://review.coreboot.org/c/coreboot/+/82113?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I516538db77509209d371f3f49c920476e06b052f Gerrit-Change-Number: 82113 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: mb/lenovo/*: Set VR12 PSI to fix crash
by Patrick Rudolph (Code Review) 28 Apr '24

28 Apr '24

Attention is currently required from: Alexander Couzens, Angel Pons, Felix Held. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82070?usp=email ) Change subject: mb/lenovo/*: Set VR12 PSI to fix crash ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82070/comment/65fd98a0_c2b82074 : PS1, Line 14: > > `Possible unwrapped commit description (prefer a maximum 72 chars per line)` […] Done https://review.coreboot.org/c/coreboot/+/82070/comment/10f3aaee_9c39d477 : PS1, Line 19: The X220 already has the correct PSI values configured and is now stable > Was this change tested on the other boards? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82070?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf8c3719f19f7bcdab30c543215c8abd2669cfd2 Gerrit-Change-Number: 82070 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 28 Apr 2024 19:34:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/lenovo/*: Set VR12 PSI to fix crash
by Patrick Rudolph (Code Review) 28 Apr '24

28 Apr '24

Attention is currently required from: Alexander Couzens, Felix Held, Patrick Rudolph. Hello Alexander Couzens, Angel Pons, Felix Held, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82070?usp=email to look at the new patch set (#2). Change subject: mb/lenovo/*: Set VR12 PSI to fix crash ...................................................................... mb/lenovo/*: Set VR12 PSI to fix crash When in Package C3 or deeper the PSI settings are used to switch the CPU VR into a low power state. It was found that the voltage regulator on the Sandy-Bridge series has non-default PSI settings, compared to Lenovo's Ivy-Bridge series. Apply the same PSI value for PSI2 and PSI3 as the vendor BIOS does to fix a hang when the package is idle. Since neither the vendor BIOS is open-source, nor datasheet exists for the used VR it's unclear why those PSI values must be used and how they influence the regulator. The X220 already has the correct PSI values configured and is now stable for more than 24h in Package C7 state. TEST: Not tested on the affected boards, only checked vendor firmware. Change-Id: Idf8c3719f19f7bcdab30c543215c8abd2669cfd2 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t520/devicetree.cb 4 files changed, 32 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/82070/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82070?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf8c3719f19f7bcdab30c543215c8abd2669cfd2 Gerrit-Change-Number: 82070 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/meteorlake: Disable FSP UPDs related to virtualization
by Felix Singer (Code Review) 28 Apr '24

28 Apr '24

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67452?usp=email ) Change subject: soc/intel/meteorlake: Disable FSP UPDs related to virtualization ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: The commit message does not give enough information on why these options were disabled. Could you please clarify? -- To view, visit https://review.coreboot.org/c/coreboot/+/67452?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21e178a93e311889f2ab7d1a08230d21b051f45e Gerrit-Change-Number: 67452 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Sun, 28 Apr 2024 19:29:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/hp/280_g2: Fix comment in `gma-mainboard.ads`
by Nicholas Chin (Code Review) 28 Apr '24

28 Apr '24

Attention is currently required from: Angel Pons. Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82112?usp=email ) Change subject: mb/hp/280_g2: Fix comment in `gma-mainboard.ads` ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82112?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I74c1257efb67cfdff2ae04a42c163dd320c850a4 Gerrit-Change-Number: 82112 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 28 Apr 2024 19:17:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/hp/280_g2: Fix comment in `gma-mainboard.ads`
by Angel Pons (Code Review) 28 Apr '24

28 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82112?usp=email ) Change subject: mb/hp/280_g2: Fix comment in `gma-mainboard.ads` ...................................................................... mb/hp/280_g2: Fix comment in `gma-mainboard.ads` The DVI connector on this board is DVI-D (digital only), not DVI-I. Change-Id: I74c1257efb67cfdff2ae04a42c163dd320c850a4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/hp/280_g2/gma-mainboard.ads 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/82112/1 diff --git a/src/mainboard/hp/280_g2/gma-mainboard.ads b/src/mainboard/hp/280_g2/gma-mainboard.ads index 735fe26..0628211 100644 --- a/src/mainboard/hp/280_g2/gma-mainboard.ads +++ b/src/mainboard/hp/280_g2/gma-mainboard.ads @@ -9,7 +9,7 @@ private package GMA.Mainboard is ports : constant Port_List := - (HDMI3, -- DVI-I + (HDMI3, -- DVI-D eDP, -- VGA others => Disabled); -- To view, visit https://review.coreboot.org/c/coreboot/+/82112?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I74c1257efb67cfdff2ae04a42c163dd320c850a4 Gerrit-Change-Number: 82112 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: [WIP] OptiPlex 3050 port
by Angel Pons (Code Review) 28 Apr '24

28 Apr '24

Attention is currently required from: Felix Singer, Máté Kukri. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82053?usp=email ) Change subject: [WIP] OptiPlex 3050 port ...................................................................... Patch Set 1: (1 comment) File src/mainboard/dell/optiplex_3050/gma-mainboard.ads: https://review.coreboot.org/c/coreboot/+/82053/comment/c34748dd_460953a5 : PS1, Line 15: eDP, -- eDP - VGA via RTD2168 (Doesn't seem to work) 1. Indent with 3 spaces please 2. Looks like the correct port list is `HDMI1, DP2, HDMI2, DP3`: https://i.imgur.com/9qSlkW7.png -- To view, visit https://review.coreboot.org/c/coreboot/+/82053?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2 Gerrit-Change-Number: 82053 Gerrit-PatchSet: 1 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Comment-Date: Sun, 28 Apr 2024 18:58:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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