coreboot-gerrit April 2024

coreboot-gerrit@coreboot.org

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[XL] Change in coreboot[main]: vc/intel/fsp/mtl: Update header files for 2364_00
by Felix Singer (Code Review) 28 Apr '24

28 Apr '24

Felix Singer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/68429?usp=email ) Change subject: vc/intel/fsp/mtl: Update header files for 2364_00 ...................................................................... Abandoned Abandoned in favor CB:68491 -- To view, visit https://review.coreboot.org/c/coreboot/+/68429?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4025fc8b533089719f8a06cdca7ddb422d64aab7 Gerrit-Change-Number: 68429 Gerrit-PatchSet: 1 Gerrit-Owner: Jyotsna Shridharan <jyotsna.shridharan(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jyotsna Shridharan <jyotsna.shridharan(a)intel.corp-partner.google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: abandon

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[XS] Change in coreboot[main]: acpi: Fix return value in acpi_device_write_dsd_gpio()
by Subrata Banik (Code Review) 28 Apr '24

28 Apr '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82088?usp=email ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: acpi: Fix return value in acpi_device_write_dsd_gpio() ...................................................................... acpi: Fix return value in acpi_device_write_dsd_gpio() Fix ++ as suffix and * precedence. After modification, the gpio index can be obtained correctly. The error was introduced in the commit making it public: commit 01344bce BUG=None TEST= Can get the correct index test on nissa. Change-Id: I7a3eb89633aaebebc8bd98ac6126c578fda23839 Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82088 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/acpi/device.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Kapil Porwal: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Dolan Liu: Looks good to me, but someone else must approve diff --git a/src/acpi/device.c b/src/acpi/device.c index 091a086..7313639 100644 --- a/src/acpi/device.c +++ b/src/acpi/device.c @@ -51,7 +51,7 @@ return ret; acpi_device_write_gpio(gpio); - ret = *curr_index++; + ret = (*curr_index)++; return ret; } -- To view, visit https://review.coreboot.org/c/coreboot/+/82088?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7a3eb89633aaebebc8bd98ac6126c578fda23839 Gerrit-Change-Number: 82088 Gerrit-PatchSet: 7 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: include/device/pci_ids.h, soc/intel/mtl: add new MTL-P iGPU DID
by Felix Singer (Code Review) 28 Apr '24

28 Apr '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Michał Kopeć, Subrata Banik, Tarun. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82071?usp=email ) Change subject: include/device/pci_ids.h, soc/intel/mtl: add new MTL-P iGPU DID ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82071?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f10808fd0e2d9c122743615fbce656c6d2447cc Gerrit-Change-Number: 82071 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Sun, 28 Apr 2024 18:11:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: include/device/pci_ids.h, soc/intel/mtl: add new MTL-P iGPU DID
by Michał Kopeć (Code Review) 28 Apr '24

28 Apr '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82071?usp=email to look at the new patch set (#2). Change subject: include/device/pci_ids.h, soc/intel/mtl: add new MTL-P iGPU DID ...................................................................... include/device/pci_ids.h, soc/intel/mtl: add new MTL-P iGPU DID Found in a Clevo V560TU with Intel Core Ultra 155H Change-Id: I0f10808fd0e2d9c122743615fbce656c6d2447cc Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/meteorlake/bootblock/report_platform.c 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/82071/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82071?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f10808fd0e2d9c122743615fbce656c6d2447cc Gerrit-Change-Number: 82071 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: include/device/pci_ids.h, soc/intel/mtl: add new MTL-P iPU DID
by Michał Kopeć (Code Review) 28 Apr '24

28 Apr '24

Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82071?usp=email ) Change subject: include/device/pci_ids.h, soc/intel/mtl: add new MTL-P iPU DID ...................................................................... include/device/pci_ids.h, soc/intel/mtl: add new MTL-P iPU DID Found in a Clevo V560TU with Intel Core Ultra 155H Change-Id: I0f10808fd0e2d9c122743615fbce656c6d2447cc Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/meteorlake/bootblock/report_platform.c 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/82071/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index d3ba149..d6f8dd3 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4128,6 +4128,7 @@ #define PCI_DID_INTEL_MTL_P_GT2_2 0x7d50 #define PCI_DID_INTEL_MTL_P_GT2_3 0x7d55 #define PCI_DID_INTEL_MTL_P_GT2_4 0x7d60 +#define PCI_DID_INTEL_MTL_P_GT2_5 0x7dd5 #define PCI_DID_INTEL_RPL_HX_GT1 0xa788 #define PCI_DID_INTEL_RPL_HX_GT2 0xa78b #define PCI_DID_INTEL_RPL_HX_GT3 0x4688 diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index eabcb9a..c38b30f 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -348,6 +348,7 @@ PCI_DID_INTEL_MTL_P_GT2_2, PCI_DID_INTEL_MTL_P_GT2_3, PCI_DID_INTEL_MTL_P_GT2_4, + PCI_DID_INTEL_MTL_P_GT2_5, PCI_DID_INTEL_APL_IGD_HD_505, PCI_DID_INTEL_APL_IGD_HD_500, PCI_DID_INTEL_CNL_GT2_ULX_1, diff --git a/src/soc/intel/meteorlake/bootblock/report_platform.c b/src/soc/intel/meteorlake/bootblock/report_platform.c index 49d0661..bc8ae92 100644 --- a/src/soc/intel/meteorlake/bootblock/report_platform.c +++ b/src/soc/intel/meteorlake/bootblock/report_platform.c @@ -58,6 +58,7 @@ { PCI_DID_INTEL_MTL_P_GT2_2, "MeteorLake-P GT2" }, { PCI_DID_INTEL_MTL_P_GT2_3, "MeteorLake-P GT2" }, { PCI_DID_INTEL_MTL_P_GT2_4, "Meteorlake-P GT2" }, + { PCI_DID_INTEL_MTL_P_GT2_5, "Meteorlake-P GT2" }, }; static inline uint8_t get_dev_revision(pci_devfn_t dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/82071?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f10808fd0e2d9c122743615fbce656c6d2447cc Gerrit-Change-Number: 82071 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/intel/meteorlake: Update Touch Controller UDP params
by Angel Pons (Code Review) 28 Apr '24

28 Apr '24

Attention is currently required from: Arthur Heymans, Cliff Huang, Dinesh Gehlot, Eran Mitrani, Eric Lai, Jakub Czapiga, Jingyuan Liang, Kapil Porwal, Kyoung Il Kim, Paul Menzel, Subrata Banik, Tarun. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81332?usp=email ) Change subject: soc/intel/meteorlake: Update Touch Controller UDP params ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81332/comment/946ae2a9_5b29c143 : PS4, Line 7: UDP typo? UPD -- To view, visit https://review.coreboot.org/c/coreboot/+/81332?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I19edbcad705e889166d7d340b2caa74ab3bf15a1 Gerrit-Change-Number: 81332 Gerrit-PatchSet: 4 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Henry Barnor <hbarnor(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Sun, 28 Apr 2024 11:58:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/meteorlake: Update Touch Controller UDP params
by Angel Pons (Code Review) 28 Apr '24

28 Apr '24

Attention is currently required from: Arthur Heymans, Cliff Huang, Dinesh Gehlot, Eran Mitrani, Eric Lai, Jakub Czapiga, Jingyuan Liang, Kapil Porwal, Kyoung Il Kim, Paul Menzel, Subrata Banik, Tarun. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81332?usp=email ) Change subject: soc/intel/meteorlake: Update Touch Controller UDP params ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/meteorlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/81332/comment/fdfc6075_5aa9290c : PS2, Line 639: s_cfg->ThcAssignment[0] = THC_NONE; > fill_fsps_thc_params function is inserted only when SOC_INTEL_TOUCH is enabled. […] Using `#if` and `#endif` should be a last-resort measure as it prevents code from being build-tested. I would advise against using it to micro-optimise things, as the maintainability impact is non-negligible. -- To view, visit https://review.coreboot.org/c/coreboot/+/81332?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I19edbcad705e889166d7d340b2caa74ab3bf15a1 Gerrit-Change-Number: 81332 Gerrit-PatchSet: 4 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Henry Barnor <hbarnor(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Sun, 28 Apr 2024 11:58:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: include/device/pci_ids.h: Add DIDs for MTL Touch controller
by Angel Pons (Code Review) 28 Apr '24

28 Apr '24

Attention is currently required from: Cliff Huang. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81330?usp=email ) Change subject: include/device/pci_ids.h: Add DIDs for MTL Touch controller ...................................................................... Patch Set 4: (1 comment) File src/include/device/pci_ids.h: https://review.coreboot.org/c/coreboot/+/81330/comment/b7f5bc9d_a34d6a77 : PS4, Line 4726: PCI_DID_INTEL_MTL_THC0_2 If this is THC0 in SPI mode, it would've been nice to name this `PCI_DID_INTEL_MTL_THC0_SPI` -- To view, visit https://review.coreboot.org/c/coreboot/+/81330?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1b98fdbd8d8588492bcafa0f3998818dc83ff1d9 Gerrit-Change-Number: 81330 Gerrit-PatchSet: 4 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Henry Barnor <hbarnor(a)chromium.org> Gerrit-CC: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Comment-Date: Sun, 28 Apr 2024 11:57:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/rex: Add Intel Touch for controller 1 for Rex
by Angel Pons (Code Review) 28 Apr '24

28 Apr '24

Attention is currently required from: Cliff Huang, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jingyuan Liang, Kapil Porwal, Kyoung Il Kim, Paul Menzel, Subrata Banik, Tarun. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81333?usp=email ) Change subject: mb/google/rex: Add Intel Touch for controller 1 for Rex ...................................................................... Patch Set 4: (3 comments) File src/mainboard/google/rex/variants/rex0/fw_config.c: https://review.coreboot.org/c/coreboot/+/81333/comment/e236a133_2e14ab9a : PS4, Line 10: #if CONFIG(SOC_INTEL_TOUCH) > Why is the preprocessor magic needed? I'd say it would make much more sense to put the "touch" stuff in some `touch.c` file, which would be conditionally built. File src/mainboard/google/rex/variants/rex0/overridetree.cb: https://review.coreboot.org/c/coreboot/+/81333/comment/cbc20a30_18041c5e : PS2, Line 33: THC NOTE for P1 and P2:reworked > Please add a space after the colon. Done https://review.coreboot.org/c/coreboot/+/81333/comment/19da916c_3a90bfb5 : PS2, Line 84: register "thc_configuration" = "THC_CONFIG_DOUBLE_CONTROLLER" > First, the name 'thc_configuration' is chosen instead of thc_config since 'config' has been used for […] Looks like the requirement for THC 0 to always be enabled is because of PCI: function 0 of a multi-function device always needs to exist. https://github.com/coreboot/coreboot/blob/fce08d78837431a3309d2b8705555fd81… shows that THC 0 is function 0, whereas THC 1 is function 1; as I expected. Given that the THCs (Touch Host Controllers?) have corresponding PCI devices, one could use the PCI devices themselves to know if a given controller is enabled. This would only require mapping ports to controllers (one port maps to only one controller). Something like this should work: ``` // In chip.h enum touch_port_to_ctrlr { TO_THC_DISABLED = 0, TO_THC_0, TO_THC_1, }; // In chip config enum touch_port_to_ctrlr port_to_thc_map[2]; ``` This would allow mapping any port to any THC, and should directly map to FSP UPDs as on TGL (UPD names may differ): https://github.com/coreboot/coreboot/blob/fce08d78837431a3309d2b8705555fd81… Now I wonder, would this work for Rex use-case, or do any enabled THCs require having at least one port assigned? ``` device ref thc_0 on register "port_to_thc_map[0]" = "TO_THC_DISABLED" end device ref thc_1 on register "port_to_thc_map[1]" = "TO_THC_1" end ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/81333?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id89b5b46d67b90491410d3d08c1a3ae9549b4da5 Gerrit-Change-Number: 81333 Gerrit-PatchSet: 4 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Henry Barnor <hbarnor(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Sun, 28 Apr 2024 11:56:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: arch/io.h: Add port I/O functions to other architectures
by Nico Huber (Code Review) 28 Apr '24

28 Apr '24

Attention is currently required from: Alper Nebi Yasak, Arthur Heymans, Julius Werner, ron minnich. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80372?usp=email ) Change subject: arch/io.h: Add port I/O functions to other architectures ...................................................................... Patch Set 5: (1 comment) File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/80372/comment/402fac2e_77cae546 : PS5, Line 532: CPU communicate with peripheral devices over PCI I/O space. > > Port I/O is a concept completely specific to the x86 architecture, it doesn't make sense on Arm. […] There's definitely PCI hardware in the world that would need it. However, I couldn't tell if coreboot would ever see such real hardware, or only emulated one (and then we could just choose to emulate something else?). Maybe we should make this a broader discussion about how much PCI we want to support on non-x86? AFAICT, qemu-aarch64, qcom and mtk already partially implement PCI i/o support. Should we move ahead or back? IMHO, it wouldn't be much of a burden to go ahead. Julius, about the API, maybe you could try to see it more abstract like this: there's something that requires special instructions on x86, but can be done with MMIO on reasonable platforms. With this in mind would any- thing be wrong with the current API? -- To view, visit https://review.coreboot.org/c/coreboot/+/80372?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7d9177283e8c692088ba8e30d6dfe52623c8cb9 Gerrit-Change-Number: 80372 Gerrit-PatchSet: 5 Gerrit-Owner: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Sun, 28 Apr 2024 11:51:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-MessageType: comment

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