coreboot-gerrit April 2024

coreboot-gerrit@coreboot.org

1 participants
3293 discussions

[L] Change in coreboot[main]: [for test] upgrade crossgcc
by Elyes Haouas (Code Review) 28 Apr '24

28 Apr '24

Attention is currently required from: Martin L Roth. Hello Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81419?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: [for test] upgrade crossgcc ...................................................................... [for test] upgrade crossgcc Change-Id: I463c303694c304bb3bf664bc1d914462e7af5dbb Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix-20240321_iasl.patch R util/crossgcc/patches/gcc-14-20240427_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-14-20240427_gnat.patch R util/crossgcc/patches/gcc-14-20240427_libcpp.patch R util/crossgcc/patches/gcc-14-20240427_libgcc.patch R util/crossgcc/patches/gcc-14-20240427_musl_poisoned_calloc.patch R util/crossgcc/patches/gcc-14-20240427_rv32iafc.patch D util/crossgcc/patches/nasm-2.16.01_handle_warning_files_while_building_in_a_directory.patch D util/crossgcc/sum/acpica-unix-20230628.tar.gz.cksum A util/crossgcc/sum/acpica-unix-20240321.tar.gz.cksum D util/crossgcc/sum/clang-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/clang-18.1.4.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-18.1.4.src.tar.xz.cksum D util/crossgcc/sum/cmake-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/cmake-18.1.4.src.tar.xz.cksum D util/crossgcc/sum/cmake-3.28.3.tar.gz.cksum A util/crossgcc/sum/cmake-3.29.2.tar.gz.cksum D util/crossgcc/sum/compiler-rt-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-18.1.4.src.tar.xz.cksum D util/crossgcc/sum/gcc-13.2.0.tar.xz.cksum A util/crossgcc/sum/gcc-14-20240427.tar.xz.cksum D util/crossgcc/sum/libunwind-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/libunwind-18.1.4.src.tar.xz.cksum D util/crossgcc/sum/lld-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/lld-18.1.4.src.tar.xz.cksum D util/crossgcc/sum/llvm-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/llvm-18.1.4.src.tar.xz.cksum D util/crossgcc/sum/nasm-2.16.01.tar.bz2.cksum A util/crossgcc/sum/nasm-2.16.03.tar.bz2.cksum 31 files changed, 54 insertions(+), 286 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/81419/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/81419?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I463c303694c304bb3bf664bc1d914462e7af5dbb Gerrit-Change-Number: 81419 Gerrit-PatchSet: 11 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/google/corsola/wugtrio: Add initialization of USB port0
by Mingjin Ge (Code Review) 28 Apr '24

28 Apr '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Wentao Qin, Yidi Lin, Yu-Ping Wu. Mingjin Ge has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82089?usp=email ) Change subject: mb/google/corsola/wugtrio: Add initialization of USB port0 ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/82089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Gerrit-Change-Number: 82089 Gerrit-PatchSet: 3 Gerrit-Owner: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Sun, 28 Apr 2024 07:23:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/corsola/wugtrio: Add initialization of USB port0
by Wentao Qin (Code Review) 28 Apr '24

28 Apr '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Wentao Qin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82089?usp=email ) Change subject: mb/google/corsola/wugtrio: Add initialization of USB port0 ...................................................................... Patch Set 3: (1 comment) Patchset: PS1: > We are offline discussions with MTK. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Gerrit-Change-Number: 82089 Gerrit-PatchSet: 3 Gerrit-Owner: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Sun, 28 Apr 2024 07:18:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/corsola/wugtrio: Add initialization of USB port0
by Wentao Qin (Code Review) 28 Apr '24

28 Apr '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Wentao Qin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82089?usp=email ) Change subject: mb/google/corsola/wugtrio: Add initialization of USB port0 ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/82089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Gerrit-Change-Number: 82089 Gerrit-PatchSet: 3 Gerrit-Owner: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Sun, 28 Apr 2024 07:17:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: drivers/crb,pc80/tpm: Add crb and pc80 prefixes to chip configs
by Sergii Dmytruk (Code Review) 27 Apr '24

27 Apr '24

Attention is currently required from: Christian Walter, Felix Held, Jérémy Compostella, Michał Żygowski. Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82057?usp=email ) Change subject: drivers/crb,pc80/tpm: Add crb and pc80 prefixes to chip configs ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > would probably be good to use the struct without hiding it behind a typedef and remove the typedef Good point, struct names are already unique, not sure why typedef is even there. -- To view, visit https://review.coreboot.org/c/coreboot/+/82057?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id41717e265362303a17745303a907c9c8f4f4e12 Gerrit-Change-Number: 82057 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 27 Apr 2024 15:40:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: arch/x86: Enable long mode entry into payload for x86_64 support
by Nico Huber (Code Review) 27 Apr '24

27 Apr '24

Attention is currently required from: Arthur Heymans, Julius Werner, Jérémy Compostella, Kapil Porwal, Patrick Rudolph, Subrata Banik, Werner Zeh. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81960?usp=email ) Change subject: arch/x86: Enable long mode entry into payload for x86_64 support ...................................................................... Patch Set 14: (1 comment) Patchset: PS14: Thanks for your thoughts, Julius. > > Can you give an example where something like this hit x86 payloads in general? > > Well, okay, most of these are probably somewhat platform- or payload-specific due to the simple fact that libpayload doesn't really do that much on its own. The most recent one I can find that would break something universal is the FMAP cache in CBMEM from 2019 (which is nowadays required by libcbfs). But I don't think people think about that direction of compatibility much when they add code (at least I don't, to be honest). That particular example is good know. I'm not sure but I might actually hit that incompatibility soon. > > Anyway, I'm not trying to invalidate your use case if you say you have one. But I still think there's a practical problem here in terms of getting this supported in a truly backwards-compatible manner. We need to have a purely 64-bit handoff flow for X86S eventually (so might as well design that right now rather than kicking that can down the road), Absolutely, yes. Hence my email. > but in order to make that compatible with old 32-bit coreboot the payload would need two entry points. It's impossible to do that cleanly with the existing SELF segment structures because old coreboots will reject any segment type they don't recognize. We could say "take the 32-bit entry point + 0x200" but that's pretty hacky and then we still need to be able to mark the payload as 64-bit supporting somehow. We can't use a CBFS type for that either without breaking backwards-compatibility, so the only options I see would be using a CBFS attribute (which seems much less suitable than the type for this) or putting some kind of parseable header into the payload. Yeah, I trust you when you say it would be too messy, you're definitely more experienced with this CBFS than I am. I thought about the dual-entry solution more as a nice to have anyway, to increase compatibility. And assumed that we could leave most of the added complexity to the payload. e.g. with an attribute ``` if (has 64-bit attribute) jump where the attribute says else die ``` for X86S. And for AMD64 just keep the current code. That was my naive idea without considering the overall payload loading. IIUC, you are saying that it would be cleaner if we had a separate type that we would check anyway before loading? And you are in favor of a new CBFS type (not a new segment type), is that correct? Dual entry aside, do we already have code in coreboot that considers archi- tecture-specific types or would we have to add code? > > Both of them (and the "second entry point at hardcoded offset" thing) seem like really hacky and roundabout solutions for things that our data structures could represent in a much cleaner and more natural way (e.g. 64-bit payload as different CBFS type, or second entry point as SELF segment), that we'd only pick in the name of backwards-compatibility. I'd really prefer if we didn't need to make our handoff API so weird and unintuitive forever after only to avoid this one break in old-coreboot-new-libpayload compatibility (like we had FMAP cache in 2019, or boot_media_params in 2015). I'd rather we do another one clean break now, pick the most natural and intuitive option to represent things, try to anticipate future needs (e.g. X86S) in that decision as best as possible, and maybe think about what else we can change in order to allow future API additions to go over smoother (e.g. rethink the decision to make selfload() abort on every segment it doesn't recognize). We definitely can agree on the clean break, however not when it should happen, now vs. the first X86S platform. I don't want to repeat my whole email here, my basic thought was how we could do it with minimal (or no) additional com- plexity in coreboot. And preferably the least `if`s in coreboot and payload build systems. If we do the long-mode handover now before X86S, we have to answer more questions, e.g. * What should a 64-bit coreboot on AMD64 do when it encounters a 32-bit payload? On X86S that combination fails by definition, so less questions to answer. I thought the simplest possible solution is to treat X86S like a seperate architecture. Then we would simply imply to do a 64-bit handover on X86S just like we imply to do things the ARMv8 way on ARMv8 etc. On AMD64 we could keep the 32-bit handover because we already chose that in the past. Would that need a new CBFS type? -- To view, visit https://review.coreboot.org/c/coreboot/+/81960?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5e6f0af11c05e8b075b8c20880c012747a1df9b Gerrit-Change-Number: 81960 Gerrit-PatchSet: 14 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Sat, 27 Apr 2024 12:30:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/rex: Add Intel Touch for controller 1 for Rex
by Paul Menzel (Code Review) 27 Apr '24

27 Apr '24

Attention is currently required from: Cliff Huang, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jingyuan Liang, Kapil Porwal, Kyoung Il Kim, Subrata Banik, Tarun. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81333?usp=email ) Change subject: mb/google/rex: Add Intel Touch for controller 1 for Rex ...................................................................... Patch Set 4: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81333/comment/d4789f77_307bf89c : PS4, Line 13: minor Rework Minor rework … https://review.coreboot.org/c/coreboot/+/81333/comment/6b6e4b32_bea522b1 : PS4, Line 13: Major rework is required for Rex P1 and P2. Why? What is the problem with the current implementation? https://review.coreboot.org/c/coreboot/+/81333/comment/3aa0c008_5e528e05 : PS4, Line 9: GPIO pad configuration for THC1 according to CBI fw_config. : ACPI entries in SSDT for ELAN according to CBI fw_config. : : THC0 must be enabled when THC1 is enabled. : Major rework is required for Rex P1 and P2. minor Rework is needed for : EVT. Rex with THC rework won't be able to support UWB and FPCMU. : The touch device must be converted to SPI interface. : When THC is enabled and the THC rework is in place, the UWB and FPMCU : are not supported and need to be disable from the CBI. : THC0 will also be provided with ACPI entries when THC1 is enabled. : THC1 GPIO pins will be configured for THC according to the CBI : TOUCHSCREEN fw_config field. : The resistor on the THC-SPI MISO pin should be 100 Ohm. For me this reads very heard, as you break the line after every sentence, and often it’s also just a note, and it’s hard to know if these are related, and what problem is addressed exactly. File src/mainboard/google/rex/variants/rex0/fw_config.c: https://review.coreboot.org/c/coreboot/+/81333/comment/5f260231_0f00036d : PS4, Line 10: #if CONFIG(SOC_INTEL_TOUCH) Why is the preprocessor magic needed? -- To view, visit https://review.coreboot.org/c/coreboot/+/81333?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id89b5b46d67b90491410d3d08c1a3ae9549b4da5 Gerrit-Change-Number: 81333 Gerrit-PatchSet: 4 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Henry Barnor <hbarnor(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Sat, 27 Apr 2024 06:40:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brox: Add 20K pulldown to GPP_D14
by Paul Menzel (Code Review) 27 Apr '24

27 Apr '24

Attention is currently required from: Karthik Ramasubramanian, Nick Vaccaro, Shelley Chen. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82096?usp=email ) Change subject: mb/google/brox: Add 20K pulldown to GPP_D14 ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82096/comment/e4743b77_9e2cfa52 : PS1, Line 16: HW validates that power usage is lower HW team? Please add the numbers. -- To view, visit https://review.coreboot.org/c/coreboot/+/82096?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e19e98fa31022ece66a47402a2a4461b430ef70 Gerrit-Change-Number: 82096 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Sat, 27 Apr 2024 06:34:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: drivers/intel/mipi_camera: Add CSI2 Data Stream Interface GUID
by Paul Menzel (Code Review) 27 Apr '24

27 Apr '24

Attention is currently required from: CoolStar, Felix Singer, Matt Delco, Sugnan Prabhu S. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82068?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: drivers/intel/mipi_camera: Add CSI2 Data Stream Interface GUID ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82068/comment/cc44f351_4febcbd2 : PS1, Line 9: Tested on google/brya (kano) : > Didn't show up as a webcam to Windows at all. […] Thank you for the clarification. “Tested on google/brya (kano)” sounds to me like it works with your change. It’d be great if you could clarify that in the commit message, what the situation before and after the change-set is. -- To view, visit https://review.coreboot.org/c/coreboot/+/82068?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id6089f6bd841333882e28de9307fe5e48e368d02 Gerrit-Change-Number: 82068 Gerrit-PatchSet: 2 Gerrit-Owner: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Matt Delco <delco(a)chromium.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Comment-Date: Sat, 27 Apr 2024 06:34:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: CoolStar <coolstarorganization(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: cpu/x86: Link page tables in stage if possible
by Patrick Rudolph (Code Review) 27 Apr '24

27 Apr '24

Attention is currently required from: Arthur Heymans. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80337?usp=email ) Change subject: cpu/x86: Link page tables in stage if possible ...................................................................... Patch Set 22: (1 comment) Patchset: PS22: This change breaks systems that use PLATFORM_USES_FSP2_X86_32 and HAVE_MRC due to romstage not being aligned to 4096 and thus the page tables are also not aligned. -- To view, visit https://review.coreboot.org/c/coreboot/+/80337?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562 Gerrit-Change-Number: 80337 Gerrit-PatchSet: 22 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 27 Apr 2024 05:36:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2024