coreboot-gerrit April 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: inteltool: improve support for Elkhart Lake
by Angel Pons (Code Review) 28 Apr '24

28 Apr '24

Attention is currently required from: Alexander Couzens, Pratikkumar V Prajapati. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75214?usp=email ) Change subject: inteltool: improve support for Elkhart Lake ...................................................................... Patch Set 5: (2 comments) File util/inteltool/spi.c: https://review.coreboot.org/c/coreboot/+/75214/comment/51e96010_3538bd82 : PS5, Line 426: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: : case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: : case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: : case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL: : case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL: : case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL: : case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL: : case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: : case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: : case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: These also have a dedicated SPI device, code should be updated. But not in this patch https://review.coreboot.org/c/coreboot/+/75214/comment/225eb1a6_88841088 : PS5, Line 450: !rcba_size Isn't this check a bit redundant? -- To view, visit https://review.coreboot.org/c/coreboot/+/75214?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida852f3c991cdd036d9c282f9cabceb23c765e25 Gerrit-Change-Number: 75214 Gerrit-PatchSet: 5 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Sun, 28 Apr 2024 09:45:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: inteltool: memory: log PCI id of unknown devices
by Angel Pons (Code Review) 28 Apr '24

28 Apr '24

Attention is currently required from: Alexander Couzens. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79363?usp=email ) Change subject: inteltool: memory: log PCI id of unknown devices ...................................................................... Patch Set 3: (1 comment) File util/inteltool/memory.c: https://review.coreboot.org/c/coreboot/+/79363/comment/bf7ef6dc_1809356b : PS3, Line 240: %08x/%08x Aren't PCI IDs 16-bit? -- To view, visit https://review.coreboot.org/c/coreboot/+/79363?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I25396e5480c45729710b16345f997c78e8bcbccb Gerrit-Change-Number: 79363 Gerrit-PatchSet: 3 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Sun, 28 Apr 2024 09:40:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in blobs[main]: intel: update microcode: fix most of the shellsheck warning
by Angel Pons (Code Review) 28 Apr '24

28 Apr '24

Attention is currently required from: Alexander Couzens. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/blobs/+/35660?usp=email ) Change subject: intel: update microcode: fix most of the shellsheck warning ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/blobs/+/35660?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Iff7484695557f8d6e5f9beb0887d1c81ea1ec131 Gerrit-Change-Number: 35660 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Sun, 28 Apr 2024 09:39:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/lenovo/*: Set VR12 PSI to fix crash
by Angel Pons (Code Review) 28 Apr '24

28 Apr '24

Attention is currently required from: Alexander Couzens, Felix Held, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82070?usp=email ) Change subject: mb/lenovo/*: Set VR12 PSI to fix crash ...................................................................... Patch Set 1: Code-Review+1 (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82070/comment/a36d2a8b_7998b666 : PS1, Line 13: as the vendor BIOS does to fix a hang when the package is idle. IIRC from CB:81597 review, you want boards to always specify these values. If so, then you should highly consider extending `util/autoport` to automatically read the relevant registers and write the values into the devicetree. https://review.coreboot.org/c/coreboot/+/82070/comment/39b2843c_e6f2e9d0 : PS1, Line 14: > `Possible unwrapped commit description (prefer a maximum 72 chars per line)` Please fix. https://review.coreboot.org/c/coreboot/+/82070/comment/a381ffea_a54b873b : PS1, Line 19: The X220 already has the correct PSI values configured and is now stable Was this change tested on the other boards? File src/mainboard/lenovo/l520/devicetree.cb: https://review.coreboot.org/c/coreboot/+/82070/comment/f5075e8d_2e4d679d : PS1, Line 17: register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" : register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" : register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" : register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" If I get bored I will refactor this to use a 2D array: ``` register "pp_psi" = "{ [0] = { [VR12_PSI2] = {VR12_ALL_PHASES, 5}, [VR12_PSI3] = {VR12_ALL_PHASES, 1}, }, [1] = { [VR12_PSI2] = {VR12_ALL_PHASES, 5}, [VR12_PSI3] = {VR12_ALL_PHASES, 1}, }, }" ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/82070?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf8c3719f19f7bcdab30c543215c8abd2669cfd2 Gerrit-Change-Number: 82070 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 28 Apr 2024 09:38:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/lenovo/*: Set VR12 PSI to fix crash
by Patrick Rudolph (Code Review) 28 Apr '24

28 Apr '24

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82070?usp=email ) Change subject: mb/lenovo/*: Set VR12 PSI to fix crash ...................................................................... mb/lenovo/*: Set VR12 PSI to fix crash When in Package C3 or deeper the PSI settings are used to switch the CPU VR into a low power state. It was found that the voltage regulator on the Sandy-Bridge series has non-default PSI settings, compared to Lenovo's Ivy-Bridge series. Apply the same PSI value for PSI2 and PSI3 as the vendor BIOS does to fix a hang when the package is idle. Since neither the vendor BIOS is open-source, nor datasheet exists for the used VR it's unclear why those PSI values must be used and how they influence the regulator. The X220 already has the correct PSI values configured and is now stable for more than 24h in Package C7 state. Change-Id: Idf8c3719f19f7bcdab30c543215c8abd2669cfd2 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t520/devicetree.cb 4 files changed, 32 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/82070/1 diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index ead7e0b..a4fbe11 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -12,7 +12,14 @@ register "gpu_panel_power_up_delay" = "0" register "gpu_pch_backlight" = "0x00000000" register "spd_addresses" = "{0x50, 0, 0x52, 0}" - + chip cpu/intel/model_206ax + # Values obtained from vendor BIOS + register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + device cpu_cluster 0 on end + end device domain 0 on subsystemid 0x17aa 0x21dd inherit diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index d4b31af..d469da6 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -16,7 +16,14 @@ register "gpu_pch_backlight" = "0x06100610" register "spd_addresses" = "{0x50, 0, 0x51, 0}" - + chip cpu/intel/model_206ax + # Values obtained from vendor BIOS + register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + device cpu_cluster 0 on end + end device domain 0 on subsystemid 0x17aa 0x21ce inherit diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index fb30917..4ce9077 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -16,7 +16,14 @@ register "gpu_pch_backlight" = "0x06100610" register "spd_addresses" = "{0x50, 0, 0x51, 0}" - + chip cpu/intel/model_206ax + # Values obtained from vendor BIOS + register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + device cpu_cluster 0 on end + end device domain 0 on subsystemid 0x17aa 0x21d2 inherit diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index a2e12c3..5edb63e 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -15,6 +15,14 @@ register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" + chip cpu/intel/model_206ax + # Values obtained from vendor BIOS + register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + device cpu_cluster 0 on end + end device domain 0 on subsystemid 0x17aa 0x21cf inherit -- To view, visit https://review.coreboot.org/c/coreboot/+/82070?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf8c3719f19f7bcdab30c543215c8abd2669cfd2 Gerrit-Change-Number: 82070 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: mb/google/corsola/wugtrio: Add initialization of USB port0
by Mingjin Ge (Code Review) 28 Apr '24

28 Apr '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Wentao Qin, Yang Wu, Yidi Lin, Yu-Ping Wu. Mingjin Ge has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82089?usp=email ) Change subject: mb/google/corsola/wugtrio: Add initialization of USB port0 ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/82089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Gerrit-Change-Number: 82089 Gerrit-PatchSet: 4 Gerrit-Owner: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Sun, 28 Apr 2024 08:58:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/corsola/wugtrio: Add initialization of USB port0
by Xuxin Xiong (Code Review) 28 Apr '24

28 Apr '24

Attention is currently required from: Hung-Te Lin, Mingjin Ge, Paul Menzel, Wentao Qin, Yang Wu, Yidi Lin, Yu-Ping Wu. Xuxin Xiong has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82089?usp=email ) Change subject: mb/google/corsola/wugtrio: Add initialization of USB port0 ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/82089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Gerrit-Change-Number: 82089 Gerrit-PatchSet: 4 Gerrit-Owner: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Sun, 28 Apr 2024 08:50:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/corsola/wugtrio: Add initialization of USB port0
by Wentao Qin (Code Review) 28 Apr '24

28 Apr '24

Attention is currently required from: Hung-Te Lin, Mingjin Ge, Paul Menzel, Wentao Qin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Mingjin Ge, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82089?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Mingjin Ge, Verified+1 by build bot (Jenkins) Change subject: mb/google/corsola/wugtrio: Add initialization of USB port0 ...................................................................... mb/google/corsola/wugtrio: Add initialization of USB port0 Initialize USB2 port0 to support the SD card and detachable keyboard functions mounted on port0 during the coreboot stage. BUG=b:335124437 TEST=boot to OS from USB-A boot to OS from SD Card BRANCH=corsola Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Signed-off-by: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/corsola/devicetree.cb M src/mainboard/google/corsola/mainboard.c M src/soc/mediatek/common/include/soc/usb_common.h M src/soc/mediatek/common/usb.c M src/soc/mediatek/mt8186/include/soc/addressmap.h 5 files changed, 26 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/82089/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/82089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Gerrit-Change-Number: 82089 Gerrit-PatchSet: 4 Gerrit-Owner: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mingjin Ge <mingjin.ge(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: cpu/intel/model_206ax: Allow to configure VR settings
by Paul Menzel (Code Review) 28 Apr '24

28 Apr '24

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81597?usp=email ) Change subject: cpu/intel/model_206ax: Allow to configure VR settings ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Also see issue tracker comment https://ticket.coreboot.org/issues/121#change-1815. -- To view, visit https://review.coreboot.org/c/coreboot/+/81597?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I59edab47fc4fbe0240e1dd7d25647f7549b4def2 Gerrit-Change-Number: 81597 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sun, 28 Apr 2024 08:18:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: [for test] upgrade crossgcc
by Elyes Haouas (Code Review) 28 Apr '24

28 Apr '24

Attention is currently required from: Martin L Roth. Hello Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81419?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: [for test] upgrade crossgcc ...................................................................... [for test] upgrade crossgcc Change-Id: I463c303694c304bb3bf664bc1d914462e7af5dbb Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix-20240321_iasl.patch R util/crossgcc/patches/gcc-14-20240427_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-14-20240427_gnat.patch R util/crossgcc/patches/gcc-14-20240427_libcpp.patch R util/crossgcc/patches/gcc-14-20240427_libgcc.patch R util/crossgcc/patches/gcc-14-20240427_musl_poisoned_calloc.patch R util/crossgcc/patches/gcc-14-20240427_rv32iafc.patch D util/crossgcc/patches/nasm-2.16.01_handle_warning_files_while_building_in_a_directory.patch D util/crossgcc/sum/acpica-unix-20230628.tar.gz.cksum A util/crossgcc/sum/acpica-unix-20240321.tar.gz.cksum D util/crossgcc/sum/clang-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/clang-18.1.4.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-18.1.4.src.tar.xz.cksum D util/crossgcc/sum/cmake-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/cmake-18.1.4.src.tar.xz.cksum D util/crossgcc/sum/cmake-3.28.3.tar.gz.cksum A util/crossgcc/sum/cmake-3.29.2.tar.gz.cksum D util/crossgcc/sum/compiler-rt-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-18.1.4.src.tar.xz.cksum D util/crossgcc/sum/gcc-13.2.0.tar.xz.cksum A util/crossgcc/sum/gcc-14-20240427.tar.xz.cksum D util/crossgcc/sum/libunwind-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/libunwind-18.1.4.src.tar.xz.cksum D util/crossgcc/sum/lld-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/lld-18.1.4.src.tar.xz.cksum D util/crossgcc/sum/llvm-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/llvm-18.1.4.src.tar.xz.cksum D util/crossgcc/sum/nasm-2.16.01.tar.bz2.cksum A util/crossgcc/sum/nasm-2.16.03.tar.bz2.cksum 31 files changed, 54 insertions(+), 286 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/81419/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/81419?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I463c303694c304bb3bf664bc1d914462e7af5dbb Gerrit-Change-Number: 81419 Gerrit-PatchSet: 11 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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