coreboot-gerrit April 2024

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: acpi: Move acpigen_write_OSC_pci_domain to Xeon-SP
by Shuo Liu (Code Review) 06 Apr '24

06 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Felix Held, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu, Tim Wawrzynczak. Hello Arthur Heymans, Christian Walter, Cliff Huang, Felix Held, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81652?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Nico Huber, Code-Review+2 by Felix Held, Verified+1 by build bot (Jenkins) Change subject: acpi: Move acpigen_write_OSC_pci_domain to Xeon-SP ...................................................................... acpi: Move acpigen_write_OSC_pci_domain to Xeon-SP Besides code movement, improvements are made, 1. Firmware granted features are passed as parameters. 2. Rename to acpigen_write_OSC_pci_domain_fixed_caps to reflect that runtime change firmware setting is not supported. 3. Aligned to Linux 5.19.rc8 that CXL UUID call will handle PCIe bits as well. 4. Add TODO for control bits suppression based on OS supports. TEST=Build on intel/archercity CRB Change-Id: Ia297e0a828f25b751032f18de04ec76f10131076 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/acpi/acpigen_pci.c M src/include/acpi/acpigen_pci.h M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/include/soc/acpi.h 4 files changed, 315 insertions(+), 316 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/81652/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81652?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia297e0a828f25b751032f18de04ec76f10131076 Gerrit-Change-Number: 81652 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: acpi: Move acpigen_write_OSC_pci_domain to Xeon-SP
by Shuo Liu (Code Review) 06 Apr '24

06 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Felix Held, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu, Tim Wawrzynczak. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81652?usp=email ) Change subject: acpi: Move acpigen_write_OSC_pci_domain to Xeon-SP ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > This patch makes changes in 2 aspects, […] Revisited the comments from Nico and Felix, and checking through Linux kernel 5.19.rc8 and CXL spec rev 3.1 - 9.18.2.1.4, 1. For CXL root with CXL UUID call, the _OSC should cover PCI bits and CXL bit both, instead of expecting OS to call PCI setting under another PCI UUID call. This seems not so clear however is the way how Linux implements, and not conflict with example provided in CXL spec rev 3.1 as well. 2. About query and non-query setting. This call doesn't support non-query setting, where the firmware changes its settings in runtime to fit OS calls. The non-query setting is rather trivial and is related to many register settings, which is not suitable for dynamic generated _OSC in this case. However in server Linux, only the query setting is used, hence this implementation is adequate to the server case. 3. About the sanity checks on the returned control bits in query setting, where specific control bits should be further unset according to OS's support flag (imagine a case where the OS has quite limited support capabilities which cannot fully manage the firmware granted feature list, the firmware needs to take back the unsupported ones), this call doesn't support yet. However, in server Linux, the OS will calculate the control quest based on its support capability, a.k.e. to generate reasonable inputs so that _OSC sanity check is not a must. Due to this reason, we have to admit that, this version, though validated on server Linux, is not 100% compatible to a full spec point of view. If we take the criteria that acpigen codes should be fully conformed to specs (all aspects), we should put it to Xeon-SP as of now. However, improvements could be made in this codes to increase its compatibility. Point 1 - Could be fixed soon. Point 2 - Cannot be supported by design, we could clarify this by rename the call, e.g. acpigen_write_OSC_pci_domain -> acpigen_write_OSC_pci_domain_fixed_caps Point 3 - Could be added later on demand, e.g. add a sanity check subroutine to check the support flags and to suppress certain control flags, which is quite feature specific. Or we can leave a empty call placeholder for this as of now. -- To view, visit https://review.coreboot.org/c/coreboot/+/81652?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia297e0a828f25b751032f18de04ec76f10131076 Gerrit-Change-Number: 81652 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sat, 06 Apr 2024 03:16:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: lib/device_tree: Add some FDT helper functions
by Julius Werner (Code Review) 06 Apr '24

06 Apr '24

Attention is currently required from: Jakub Czapiga, Martin L Roth, Maximilian Brune. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81081?usp=email ) Change subject: lib/device_tree: Add some FDT helper functions ...................................................................... Patch Set 18: (1 comment) File src/lib/device_tree.c: https://review.coreboot.org/c/coreboot/+/81081/comment/f3346b30_885b27fb : PS18, Line 175: "" > `dt_find_node` and `fdt_find_node` work inherently different. […] Okay, sorry, I see your point now. I didn't realize that the offset passed here was the start of the child node array instead of the parent node. (BTW it would be good to add `@offset` to the parameter documentation here, because that's really the most confusing one.) In that case, how about just making the function take both offsets (`parent_node_offset` and `child_array_offset`) as parameters instead? It's a bit redundant but I think it has a number of advantages: 1. It allows you to use NULL-termination instead of a separate count (so still the same amount of total parameters) without having to awkwardly "read-ahead" to check for termination. 2. It removes the need of special-casing the root node, which means you could just rely on `strtok_r()` to automatically split the path string the right way in `fdt_find_node_by_path()`. 3. It keeps the way this works as consistent as possible with `dt_find_node()`, making the whole file easier to follow. -- To view, visit https://review.coreboot.org/c/coreboot/+/81081?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2fb1d93c5b3e1cb2f7d9584db52bbce3767b63d8 Gerrit-Change-Number: 81081 Gerrit-PatchSet: 18 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Sat, 06 Apr 2024 01:05:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: arch/arm64: Use -mno-implicit-float with clang
by Julius Werner (Code Review) 06 Apr '24

06 Apr '24

Attention is currently required from: Arthur Heymans, Martin L Roth. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81658?usp=email ) Change subject: arch/arm64: Use -mno-implicit-float with clang ...................................................................... Patch Set 3: (2 comments) File toolchain.mk: https://review.coreboot.org/c/coreboot/+/81658/comment/7b0cb1c8_a1558bee : PS1, Line 103: endif > Wouldn't it make more sense to do this in xcompile? Done File util/xcompile/xcompile: https://review.coreboot.org/c/coreboot/+/81658/comment/3683aa6a_76da9a5d : PS3, Line 212: && Doesn't this chain it to the previous statement? Which only adds the `--fix-cortex-a53-843419` flag if it is supported (which it didn't use to be on old compilers). It think these should just be two separate standalone lines, without any `&&`. -- To view, visit https://review.coreboot.org/c/coreboot/+/81658?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24fa9d9f81430ea3ecd40de4304a10c6e235fece Gerrit-Change-Number: 81658 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 06 Apr 2024 00:42:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/qualcomm/sc7{1,2}80: Increase early stages size for clang
by Julius Werner (Code Review) 06 Apr '24

06 Apr '24

Attention is currently required from: Arthur Heymans. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80639?usp=email ) Change subject: soc/qualcomm/sc7{1,2}80: Increase early stages size for clang ...................................................................... Patch Set 7: (1 comment) File src/soc/qualcomm/sc7180/memlayout.ld: https://review.coreboot.org/c/coreboot/+/80639/comment/c5ac64fc_709e607b : PS7, Line 36: 46K I think you're dropping 10K on the floor here? -- To view, visit https://review.coreboot.org/c/coreboot/+/80639?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide01233f209613678c5408f1afab19415c1071be Gerrit-Change-Number: 80639 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 06 Apr 2024 00:38:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: lib/program.ld: Account for large code model sections
by Julius Werner (Code Review) 06 Apr '24

06 Apr '24

Attention is currently required from: Arthur Heymans, Jérémy Compostella. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81675?usp=email ) Change subject: lib/program.ld: Account for large code model sections ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81675?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib755673dfa9e71172bbef0a5aec075154c89a97b Gerrit-Change-Number: 81675 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 06 Apr 2024 00:29:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: riscv/opensbi: make the opensbi payload a flat binary
by ron minnich (Code Review) 05 Apr '24

05 Apr '24

Attention is currently required from: Arthur Heymans, Arthur Heymans, Jonathan Neuschäfer, Maximilian Brune, Philipp Hug. Hello Arthur Heymans, Jonathan Neuschäfer, Maximilian Brune, Philipp Hug, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81632?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: riscv/opensbi: make the opensbi payload a flat binary ...................................................................... riscv/opensbi: make the opensbi payload a flat binary opensbi is now self-relocating and, further, has strict requirements on the alignment of the data segment -- it has to be power of 2. As opposed to trying to play too many games with ELF files and ldscripts, taking them beyond what's possible, it is simplest just to unpack the opensbi elf into a flat binary and specify its location in cbfs. Works on the sifive unmatched. Still tracking down a failure on qemu. oh well, oops, the built-in relocate stuff appears not to work at all. This rework will need some rework. Change-Id: I31525125e87ff5925ca82f4e48fe1191ba6326fd Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/Makefile.mk M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/memlayout.ld 3 files changed, 9 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/81632/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/81632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31525125e87ff5925ca82f4e48fe1191ba6326fd Gerrit-Change-Number: 81632 Gerrit-PatchSet: 7 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Add dedicated caller function for ap procedure ...
by Appukuttan V K (Code Review) 05 Apr '24

05 Apr '24

Attention is currently required from: Andrey Petrov, Appukuttan V K, Ronak Kanabar, Subrata Banik. Hello Andrey Petrov, Ronak Kanabar, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81663?usp=email to look at the new patch set (#2). Change subject: drivers/intel/fsp2_0: Add dedicated caller function for ap procedure calls ...................................................................... drivers/intel/fsp2_0: Add dedicated caller function for ap procedure calls Add FSP 2 Multi Processor Platform Initialization module a function indirection to ensure that efi_ap_procedure functions are called with the appropriate C calling convention. Change-Id: I64e65b2941207375d5e27c84aa26061e7e72a7f6 Signed-off-by: Appukuttan V K <appukuttan.vk(a)intel.com> --- M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c 1 file changed, 32 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/81663/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81663?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64e65b2941207375d5e27c84aa26061e7e72a7f6 Gerrit-Change-Number: 81663 Gerrit-PatchSet: 2 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Remove x64-specific assertion from fsp_header
by Appukuttan V K (Code Review) 05 Apr '24

05 Apr '24

Attention is currently required from: Andrey Petrov, Appukuttan V K, Ronak Kanabar, Subrata Banik. Hello Andrey Petrov, Ronak Kanabar, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81662?usp=email to look at the new patch set (#2). Change subject: drivers/intel/fsp2_0: Remove x64-specific assertion from fsp_header ...................................................................... drivers/intel/fsp2_0: Remove x64-specific assertion from fsp_header Same fsp_header struture is being used for x64 and x32 modes and hence dropping the x64 assertion. Change-Id: I6013af342670e6377a3fe7641d7d9b52c9b6f57c Signed-off-by: Appukuttan V K <appukuttan.vk(a)intel.com> --- M src/drivers/intel/fsp2_0/include/fsp/info_header.h 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/81662/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81662?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6013af342670e6377a3fe7641d7d9b52c9b6f57c Gerrit-Change-Number: 81662 Gerrit-PatchSet: 2 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned
by Appukuttan V K (Code Review) 05 Apr '24

05 Apr '24

Attention is currently required from: Andrey Petrov, Appukuttan V K, Ronak Kanabar, Subrata Banik. Hello Andrey Petrov, Ronak Kanabar, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81661?usp=email to look at the new patch set (#3). Change subject: drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned ...................................................................... drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned - Stack alignment: 1. FSP functions must be called with the stack 16-bytes aligned. This is already setup properly with the default value of the `mpreferred-stack-boundary' compiler option (4). 2. The FSP stack buffer supplied by coreboot through the `StackBase' UPD must be 16-bytes aligned. Change-Id: I86048c5d3623a29f17a5e492cd67568e4844589c Signed-off-by: Appukuttan V K <appukuttan.vk(a)intel.com> --- M src/drivers/intel/fsp2_0/memory_init.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/81661/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81661?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86048c5d3623a29f17a5e492cd67568e4844589c Gerrit-Change-Number: 81661 Gerrit-PatchSet: 3 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2024