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Change subject: cpu/x86: Link page tables in stage if possible
......................................................................
Patch Set 22:
(1 comment)
Patchset:
PS22:
> > Hi Arthur, […]
Thankyou @arthur. Above mentioned patch was not part of the build as it is not yet mirrored to the chromium repo. Tried adding it still failed. Then added a fixed number as suggested then it is building. https://review.coreboot.org/c/coreboot/+/81680
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Change subject: arch/arm64: Add Clang as supported target
......................................................................
arch/arm64: Add Clang as supported target
QEMU aarch64 boots to payload when compiled with clang.
Change-Id: I940a1ccf5cc4ec7bed5b6c8be92fc47922e1e747
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/arm64/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/74501/28
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Hello Julius Werner, build bot (Jenkins),
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Change subject: arch/arm64: Use -mno-implicit-float with clang
......................................................................
arch/arm64: Use -mno-implicit-float with clang
This fixes building inline assembly that uses SIMD registers. This is
for instance the case in the vboot library.
Change-Id: I24fa9d9f81430ea3ecd40de4304a10c6e235fece
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M toolchain.mk
M util/xcompile/xcompile
2 files changed, 7 insertions(+), 2 deletions(-)
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Change subject: soc/qualcomm/sc7{1,2}80: Increase early stages size for clang
......................................................................
soc/qualcomm/sc7{1,2}80: Increase early stages size for clang
Clang builds slightly larger binaries so increase the section.
The qcsdi is used for an external blob that is currently not in use so
reducing the size is fine for now.
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---
M src/soc/qualcomm/sc7180/memlayout.ld
M src/soc/qualcomm/sc7280/memlayout.ld
2 files changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/80639/7
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Change subject: acpi: Move acpigen_write_OSC_pci_domain to Xeon-SP
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> I still dont understand why this is a good idea to move to Intel Xeon specific code base as : […]
We could discuss on what needs to be improved instead?
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Change subject: acpi: Move acpigen_write_OSC_pci_domain to Xeon-SP
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> good point
I still dont understand why this is a good idea to move to Intel Xeon specific code base as :
- it is not Xeon specific
- it should be maintained in core code for consistency
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Change subject: mb/google/brya: Sort Kconfig option alphabetically
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/brya/Kconfig:
https://review.coreboot.org/c/coreboot/+/81631/comment/4755e22b_b4ffe686 :
PS3, Line 574: config DRIVER_TPM_I2C_BUS
> i don't have a super strong opinion on this, but i'd keep using one line per board here, since that […]
also having one line per board and have it sorted by the board name makes it a bit easier to find the setting for a board
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Change subject: mb/google/brya: Sort Kconfig option alphabetically
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/brya/Kconfig:
https://review.coreboot.org/c/coreboot/+/81631/comment/b81b57b8_adaab108 :
PS3, Line 574: config DRIVER_TPM_I2C_BUS
> Lines can be continued with backslashes. I feel this way it's much better structured and readable. […]
i don't have a super strong opinion on this, but i'd keep using one line per board here, since that minimizes the possible merge conflicts when additional boards are added. it will probably also make it easier to do that via the script that adds a new variant; never looked into how that works exactly though
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Change subject: acpi: Move acpigen_write_OSC_pci_domain to Xeon-SP
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> will this also be used for AMD or arm server in the future? this is not Intel specific right?
For CXL support, not quite sure at the moment. Maybe someone could move this to some common layer after actual reuses and retests. But now I think it should be okay to put it in xeon-sp only.
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