coreboot-gerrit April 2024

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Use default soc_get_ioapic_info
by Shuo Liu (Code Review) 05 Apr '24

05 Apr '24

Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81628?usp=email ) Change subject: soc/intel/xeon_sp: Use default soc_get_ioapic_info ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/xeon_sp/acpi.c: https://review.coreboot.org/c/coreboot/+/81628/comment/a12db3a7_44e9c116 : PS3, Line 93: #if CONFIG(XEON_SP_HAVE_IIO_IOAPIC) > i'd say that moving the code inside the #if block into a separate c file and conditionally add that […] https://review.coreboot.org/c/coreboot/+/81681 is raised for this. Let us review and discuss. -- To view, visit https://review.coreboot.org/c/coreboot/+/81628?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1ecfba49cd9b4dfbb3f11d58d04d07ea1752a131 Gerrit-Change-Number: 81628 Gerrit-PatchSet: 3 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 05 Apr 2024 13:35:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add iio_ioapic.c
by Shuo Liu (Code Review) 05 Apr '24

05 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81681?usp=email ) Change subject: soc/intel/xeon_sp: Add iio_ioapic.c ...................................................................... soc/intel/xeon_sp: Add iio_ioapic.c Move the soc_get_ioapic_info for platforms with IIO IO-APICs to a separate file from src/soc/intel/xeon_sp/acpi.c. TEST=Build intel/archerticy CRB Change-Id: I59022b7685539491604724ef3b550da1cfd53f13 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/Makefile.mk M src/soc/intel/xeon_sp/acpi.c A src/soc/intel/xeon_sp/iio_ioapic.c 3 files changed, 46 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/81681/1 diff --git a/src/soc/intel/xeon_sp/Makefile.mk b/src/soc/intel/xeon_sp/Makefile.mk index ed8f89f..a9dd33d 100644 --- a/src/soc/intel/xeon_sp/Makefile.mk +++ b/src/soc/intel/xeon_sp/Makefile.mk @@ -17,6 +17,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += uncore_acpi.c acpi.c ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c numa.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c +ramstage-$(CONFIG_XEON_SP_HAVE_IIO_IOAPIC) += iio_ioapic.c smm-y += smihandler.c pmutil.c postcar-y += spi.c diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 9ee8d6a..0d66aec 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -90,45 +90,6 @@ return map; } -#if CONFIG(XEON_SP_HAVE_IIO_IOAPIC) -static uintptr_t xeonsp_ioapic_bases[CONFIG(XEON_SP_HAVE_IIO_IOAPIC) * 8 + 1]; - -size_t soc_get_ioapic_info(const uintptr_t *ioapic_bases[]) -{ - int index = 0; - const IIO_UDS *hob = get_iio_uds(); - - *ioapic_bases = xeonsp_ioapic_bases; - - for (int socket = 0; socket < CONFIG_MAX_SOCKET; socket++) { - if (!soc_cpu_is_enabled(socket)) - continue; - for (int stack = 0; stack < MAX_IIO_STACK; ++stack) { - const STACK_RES *ri = - &hob->PlatformData.IIO_resource[socket].StackRes[stack]; - uint32_t ioapic_base = ri->IoApicBase; - if (ioapic_base == 0 || ioapic_base == 0xFFFFFFFF) - continue; - assert(index < ARRAY_SIZE(xeonsp_ioapic_bases)); - xeonsp_ioapic_bases[index++] = ioapic_base; - if (!CONFIG(XEON_SP_HAVE_IIO_IOAPIC)) - return index; - /* - * Stack 0 has non-PCH IOAPIC and PCH IOAPIC. - * The IIO IOAPIC is placed at 0x1000 from the reported base. - */ - if (socket == 0 && stack == 0) { - ioapic_base += 0x1000; - assert(index < ARRAY_SIZE(xeonsp_ioapic_bases)); - xeonsp_ioapic_bases[index++] = ioapic_base; - } - } - } - - return index; -} -#endif - void iio_domain_set_acpi_name(struct device *dev, const char *prefix) { const union xeon_domain_path dn = { diff --git a/src/soc/intel/xeon_sp/iio_ioapic.c b/src/soc/intel/xeon_sp/iio_ioapic.c new file mode 100644 index 0000000..4fa64b8 --- /dev/null +++ b/src/soc/intel/xeon_sp/iio_ioapic.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <assert.h> +#include <intelblocks/acpi.h> +#include <soc/chip_common.h> +#include <soc/util.h> +#include <stdint.h> +#include <stdlib.h> + +static uintptr_t xeonsp_ioapic_bases[CONFIG(XEON_SP_HAVE_IIO_IOAPIC) * 8 + 1]; + +size_t soc_get_ioapic_info(const uintptr_t *ioapic_bases[]) +{ + int index = 0; + const IIO_UDS *hob = get_iio_uds(); + + *ioapic_bases = xeonsp_ioapic_bases; + + for (int socket = 0; socket < CONFIG_MAX_SOCKET; socket++) { + if (!soc_cpu_is_enabled(socket)) + continue; + for (int stack = 0; stack < MAX_IIO_STACK; ++stack) { + const STACK_RES *ri = + &hob->PlatformData.IIO_resource[socket].StackRes[stack]; + uint32_t ioapic_base = ri->IoApicBase; + if (ioapic_base == 0 || ioapic_base == 0xFFFFFFFF) + continue; + assert(index < ARRAY_SIZE(xeonsp_ioapic_bases)); + xeonsp_ioapic_bases[index++] = ioapic_base; + if (!CONFIG(XEON_SP_HAVE_IIO_IOAPIC)) + return index; + /* + * Stack 0 has non-PCH IOAPIC and PCH IOAPIC. + * The IIO IOAPIC is placed at 0x1000 from the reported base. + */ + if (socket == 0 && stack == 0) { + ioapic_base += 0x1000; + assert(index < ARRAY_SIZE(xeonsp_ioapic_bases)); + xeonsp_ioapic_bases[index++] = ioapic_base; + } + } + } + + return index; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/81681?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I59022b7685539491604724ef3b550da1cfd53f13 Gerrit-Change-Number: 81681 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Granite Rapids initial codes
by Shuo Liu (Code Review) 05 Apr '24

05 Apr '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Singer, Jincheng Li, Johnny Lin, Jonathan Zhang, Nico Huber, Patrick Rudolph, Paul Menzel, Shuo Liu, TangYiwei, Tim Chu. Hello Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81316?usp=email to look at the new patch set (#37). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes ...................................................................... soc/intel/xeon_sp: Add Granite Rapids initial codes coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single IO-APIC Xeon-SP platform. The same set of codes is also used for SRF (Sierra Forest) SoC. This patch initially sets the code set up. 1. All register definitions are forked from SPR (Sapphire Rapids) and EBG (Emmisburg PCH)'s codes are reused. 2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later. TEST=Build and boot on intel/archercity CRB Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M MAINTAINERS M src/soc/intel/xeon_sp/Makefile.mk M src/soc/intel/xeon_sp/chip_gen1.c A src/soc/intel/xeon_sp/chip_gen6.c A src/soc/intel/xeon_sp/gnr/Kconfig A src/soc/intel/xeon_sp/gnr/Makefile.inc A src/soc/intel/xeon_sp/gnr/acpi/gpe.asl A src/soc/intel/xeon_sp/gnr/chip.c A src/soc/intel/xeon_sp/gnr/chip.h A src/soc/intel/xeon_sp/gnr/cpu.c A src/soc/intel/xeon_sp/gnr/include/soc/cpu.h A src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h A src/soc/intel/xeon_sp/gnr/include/soc/soc_msr.h A src/soc/intel/xeon_sp/gnr/include/soc/soc_util.h A src/soc/intel/xeon_sp/gnr/include/soc/vpd.h A src/soc/intel/xeon_sp/gnr/ramstage.c A src/soc/intel/xeon_sp/gnr/romstage.c A src/soc/intel/xeon_sp/gnr/soc_acpi.c A src/soc/intel/xeon_sp/gnr/soc_util.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/include/soc/fsp_upd.h M src/soc/intel/xeon_sp/lockdown.c M src/soc/intel/xeon_sp/uncore.c 23 files changed, 1,311 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/81316/37 -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 37 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: arch/arm64: Use -mno-implicit-float with clang
by Arthur Heymans (Code Review) 05 Apr '24

05 Apr '24

Attention is currently required from: Martin L Roth. Hello Julius Werner, Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81658?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: arch/arm64: Use -mno-implicit-float with clang ...................................................................... arch/arm64: Use -mno-implicit-float with clang This fixes building inline assembly that uses SIMD registers. This is for instance the case in the vboot library. Change-Id: I24fa9d9f81430ea3ecd40de4304a10c6e235fece Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M toolchain.mk M util/xcompile/xcompile 2 files changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/81658/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81658?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24fa9d9f81430ea3ecd40de4304a10c6e235fece Gerrit-Change-Number: 81658 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: Makefile: Enable Warray-bounds command option
by Elyes Haouas (Code Review) 05 Apr '24

05 Apr '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81640?usp=email ) Change subject: Makefile: Enable Warray-bounds command option ...................................................................... Makefile: Enable Warray-bounds command option Change-Id: I827c23dd08fb42348d1b5eadba360561662fc330 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M Makefile.mk 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/81640/1 diff --git a/Makefile.mk b/Makefile.mk index d7110a9..0bbc43c 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -500,7 +500,7 @@ CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie CFLAGS_common += -Wstring-compare ifeq ($(CONFIG_COMPILER_GCC),y) -CFLAGS_common += -Wold-style-declaration +CFLAGS_common += -Wold-style-declaration -Warray-bounds # Don't add these GCC specific flags when running scan-build ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) CFLAGS_common += -Wno-packed-not-aligned -- To view, visit https://review.coreboot.org/c/coreboot/+/81640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I827c23dd08fb42348d1b5eadba360561662fc330 Gerrit-Change-Number: 81640 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: [test tree] add Wduplicated-{branches,cond}
by Elyes Haouas (Code Review) 05 Apr '24

05 Apr '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81639?usp=email ) Change subject: [test tree] add Wduplicated-{branches,cond} ...................................................................... [test tree] add Wduplicated-{branches,cond} Change-Id: Ice560c8e87e50940aff207a67bda6a597bd74c68 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M Makefile.mk 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/81639/1 diff --git a/Makefile.mk b/Makefile.mk index d7110a9..81707c8 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -495,18 +495,18 @@ CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough CFLAGS_common += -Wshadow -Wdate-time -Wtype-limits -Wvla -Wold-style-definition -CFLAGS_common += -Wdangling-else -Wmissing-include-dirs +CFLAGS_common += -Wdangling-else -Wmissing-include-dirs -Wflex-array-member-not-at-end CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie CFLAGS_common += -Wstring-compare ifeq ($(CONFIG_COMPILER_GCC),y) -CFLAGS_common += -Wold-style-declaration +CFLAGS_common += -Wold-style-declaration -Wduplicated-branches Wduplicated-cond # Don't add these GCC specific flags when running scan-build ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) CFLAGS_common += -Wno-packed-not-aligned CFLAGS_common += -fconserve-stack CFLAGS_common += -Wnull-dereference -CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wno-array-compare +CFLAGS_common += -Wlogical-op -Wno-array-compare endif endif -- To view, visit https://review.coreboot.org/c/coreboot/+/81639?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ice560c8e87e50940aff207a67bda6a597bd74c68 Gerrit-Change-Number: 81639 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: device/device_util: Add and use is_pci_bridge()
by Shuo Liu (Code Review) 05 Apr '24

05 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Felix Singer, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Paul Menzel, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81566?usp=email ) Change subject: device/device_util: Add and use is_pci_bridge() ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: maybe we could move ahead to merge this? -- To view, visit https://review.coreboot.org/c/coreboot/+/81566?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied4921f7dc7e144e580d05d4f2262777aa59d895 Gerrit-Change-Number: 81566 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 05 Apr 2024 13:12:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in libgfxinit[main]: gma: Support ADL-P CDClk clock crawl
by Dinesh Gehlot (Code Review) 05 Apr '24

05 Apr '24

Attention is currently required from: Angel Pons, Nick Vaccaro, Nico Huber, Tarun Tuli, Tim Wawrzynczak. Dinesh Gehlot has uploaded a new patch set (#41) to the change originally created by Tim Wawrzynczak. ( https://review.coreboot.org/c/libgfxinit/+/67801?usp=email ) Change subject: gma: Support ADL-P CDClk clock crawl ...................................................................... gma: Support ADL-P CDClk clock crawl Setting up CDCLK is a little different for ADL-P, i915 calls it adlp_cdclk_pll_crawl. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Id01752a41e4e401a5f759453c12f368395eebdf2 --- M common/hw-gfx-gma-config.ads.template M common/tigerlake/Makefile.inc M common/tigerlake/hw-gfx-gma-connectors-tc.adb M common/tigerlake/hw-gfx-gma-port_detect.adb A common/tigerlake/hw-gfx-gma-power_and_clocks-tgl.adb A common/tigerlake/hw-gfx-gma-power_and_clocks-tgl.ads A common/tigerlake/hw-gfx-gma-power_and_clocks-xelpd.adb A common/tigerlake/hw-gfx-gma-power_and_clocks-xelpd.ads M common/tigerlake/hw-gfx-gma-power_and_clocks.adb M common/tigerlake/hw-gfx-gma-power_and_clocks.ads 10 files changed, 1,293 insertions(+), 485 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/01/67801/41 -- To view, visit https://review.coreboot.org/c/libgfxinit/+/67801?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: main Gerrit-Change-Id: Id01752a41e4e401a5f759453c12f368395eebdf2 Gerrit-Change-Number: 67801 Gerrit-PatchSet: 41 Gerrit-Owner: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config
by Arthur Heymans (Code Review) 05 Apr '24

05 Apr '24

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75756?usp=email ) Change subject: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config ...................................................................... Patch Set 15: (1 comment) Patchset: PS15: Printing debug stuff should be in the 'Debuggin' part of the menu, not chipset. -- To view, visit https://review.coreboot.org/c/coreboot/+/75756?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b5ca1f4a59598531a6cba500672c2717f2a7b00 Gerrit-Change-Number: 75756 Gerrit-PatchSet: 15 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Fri, 05 Apr 2024 13:10:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: arch/x86/bootblock.ld: Avoid the overlap between .text and .init
by Arthur Heymans (Code Review) 05 Apr '24

05 Apr '24

Attention is currently required from: Appukuttan V K, Jérémy Compostella, Subrata Banik. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81680?usp=email ) Change subject: arch/x86/bootblock.ld: Avoid the overlap between .text and .init ...................................................................... Patch Set 1: (2 comments) Patchset: PS1: It's probably worth investigating why that region is overflowing, rather than adding random numbers till it works. It's a good method of diagnosing the problem though. Do you have a patch train that I could try out to reproduce your issue? File src/arch/x86/bootblock.ld: https://review.coreboot.org/c/coreboot/+/81680/comment/a7ca42e3_f499a1ca : PS1, Line 29: SIZEOF(.data) don't remove this. -- To view, visit https://review.coreboot.org/c/coreboot/+/81680?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic6877f7d64487cd893e86525fd5c41582507ec7a Gerrit-Change-Number: 81680 Gerrit-PatchSet: 1 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Fri, 05 Apr 2024 13:07:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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