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[S] Change in coreboot[main]: util/crossgcc: Update GCC from 13.2 to 14-20240331
by Felix Singer (Code Review) 06 Apr '24

06 Apr '24

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81683?usp=email ) Change subject: util/crossgcc: Update GCC from 13.2 to 14-20240331 ...................................................................... util/crossgcc: Update GCC from 13.2 to 14-20240331 Change-Id: Idf5912d1fcdfabab7fe006b7e0cd4ebd25c07d09 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-14-20240331_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-14-20240331_gnat.patch R util/crossgcc/patches/gcc-14-20240331_libcpp.patch R util/crossgcc/patches/gcc-14-20240331_libgcc.patch R util/crossgcc/patches/gcc-14-20240331_musl_poisoned_calloc.patch R util/crossgcc/patches/gcc-14-20240331_rv32iafc.patch D util/crossgcc/sum/gcc-13.2.0.tar.xz.cksum A util/crossgcc/sum/gcc-14-20240331.tar.xz.cksum 9 files changed, 11 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/81683/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 0a0462e..0e22805 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -38,7 +38,7 @@ GMP_VERSION=6.3.0 MPFR_VERSION=4.2.1 MPC_VERSION=1.3.1 -GCC_VERSION=13.2.0 +GCC_VERSION=14-20240331 BINUTILS_VERSION=2.42 IASL_VERSION="R06_28_23" # CLANG version number @@ -72,7 +72,7 @@ GMP_BASE_URL="https://ftpmirror.gnu.org/gmp" MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr" MPC_BASE_URL="https://ftpmirror.gnu.org/mpc" -GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}" +GCC_BASE_URL="https://gcc.gnu.org/pub/gcc/snapshots/${GCC_VERSION}" BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils" IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags" # CLANG toolchain archive locations diff --git a/util/crossgcc/patches/gcc-13.2.0_asan_shadow_offset_callback.patch b/util/crossgcc/patches/gcc-14-20240331_asan_shadow_offset_callback.patch similarity index 100% rename from util/crossgcc/patches/gcc-13.2.0_asan_shadow_offset_callback.patch rename to util/crossgcc/patches/gcc-14-20240331_asan_shadow_offset_callback.patch diff --git a/util/crossgcc/patches/gcc-13.2.0_gnat.patch b/util/crossgcc/patches/gcc-14-20240331_gnat.patch similarity index 100% rename from util/crossgcc/patches/gcc-13.2.0_gnat.patch rename to util/crossgcc/patches/gcc-14-20240331_gnat.patch diff --git a/util/crossgcc/patches/gcc-13.2.0_libcpp.patch b/util/crossgcc/patches/gcc-14-20240331_libcpp.patch similarity index 100% rename from util/crossgcc/patches/gcc-13.2.0_libcpp.patch rename to util/crossgcc/patches/gcc-14-20240331_libcpp.patch diff --git a/util/crossgcc/patches/gcc-13.2.0_libgcc.patch b/util/crossgcc/patches/gcc-14-20240331_libgcc.patch similarity index 100% rename from util/crossgcc/patches/gcc-13.2.0_libgcc.patch rename to util/crossgcc/patches/gcc-14-20240331_libgcc.patch diff --git a/util/crossgcc/patches/gcc-13.2.0_musl_poisoned_calloc.patch b/util/crossgcc/patches/gcc-14-20240331_musl_poisoned_calloc.patch similarity index 87% rename from util/crossgcc/patches/gcc-13.2.0_musl_poisoned_calloc.patch rename to util/crossgcc/patches/gcc-14-20240331_musl_poisoned_calloc.patch index 552a7e7..b66380d 100644 --- a/util/crossgcc/patches/gcc-13.2.0_musl_poisoned_calloc.patch +++ b/util/crossgcc/patches/gcc-14-20240331_musl_poisoned_calloc.patch @@ -23,26 +23,19 @@ /* glibc versions earlier than 2.7 do not define the routines to handle dynamically allocated CPU sets. For these targets, we use the static ---- gcc-13.2.0/gcc/ada/argv.c -+++ gcc-13.2.0.musl/gcc/ada/argv.c -@@ -42,6 +42,8 @@ - main program, and these routines are accessed from the - Ada.Command_Line.Environment package. */ - -+#include "adaint.h" -+ - #ifdef IN_RTS - #include "runtime.h" - #include <stdlib.h> -@@ -50,8 +52,6 @@ - #include "config.h" +--- gcc-14-20240211/gcc/ada/argv.c ++++ gcc-14-20240211.musl/gcc/ada/argv.c +@@ -51,10 +51,6 @@ #include "system.h" #endif -- --#include "adaint.h" +-#ifndef LIGHT_RUNTIME +-#include "adaint.h" +-#endif +- #ifdef __cplusplus extern "C" { + #endif --- gcc-13.2.0/gcc/ada/cio.c +++ gcc-13.2.0.musl/gcc/ada/cio.c @@ -29,6 +29,8 @@ diff --git a/util/crossgcc/patches/gcc-13.2.0_rv32iafc.patch b/util/crossgcc/patches/gcc-14-20240331_rv32iafc.patch similarity index 100% rename from util/crossgcc/patches/gcc-13.2.0_rv32iafc.patch rename to util/crossgcc/patches/gcc-14-20240331_rv32iafc.patch diff --git a/util/crossgcc/sum/gcc-13.2.0.tar.xz.cksum b/util/crossgcc/sum/gcc-13.2.0.tar.xz.cksum deleted file mode 100644 index dcf9d41..0000000 --- a/util/crossgcc/sum/gcc-13.2.0.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -5f95b6d042fb37d45c6cbebfc91decfbc4fb493c tarballs/gcc-13.2.0.tar.xz diff --git a/util/crossgcc/sum/gcc-14-20240331.tar.xz.cksum b/util/crossgcc/sum/gcc-14-20240331.tar.xz.cksum new file mode 100644 index 0000000..c5da7ba --- /dev/null +++ b/util/crossgcc/sum/gcc-14-20240331.tar.xz.cksum @@ -0,0 +1 @@ +9c3bb5d8c97d169aa41e82d06930f64503740917 tarballs/gcc-14-20240331.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/81683?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf5912d1fcdfabab7fe006b7e0cd4ebd25c07d09 Gerrit-Change-Number: 81683 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: util/crossgcc: Update GCC from 13.2 to 14-20240331
by Felix Singer (Code Review) 06 Apr '24

06 Apr '24

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81682?usp=email ) Change subject: util/crossgcc: Update GCC from 13.2 to 14-20240331 ...................................................................... util/crossgcc: Update GCC from 13.2 to 14-20240331 Change-Id: I91f0a5ab1d44cbf1b6346b08d1d36ddf135d0275 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-14-20240331_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-14-20240331_gnat.patch R util/crossgcc/patches/gcc-14-20240331_libcpp.patch R util/crossgcc/patches/gcc-14-20240331_libgcc.patch R util/crossgcc/patches/gcc-14-20240331_musl_poisoned_calloc.patch R util/crossgcc/patches/gcc-14-20240331_rv32iafc.patch D util/crossgcc/sum/gcc-13.2.0.tar.xz.cksum A util/crossgcc/sum/gcc-14-20240303.tar.xz.cksum 9 files changed, 11 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/81682/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 0a0462e..0e22805 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -38,7 +38,7 @@ GMP_VERSION=6.3.0 MPFR_VERSION=4.2.1 MPC_VERSION=1.3.1 -GCC_VERSION=13.2.0 +GCC_VERSION=14-20240331 BINUTILS_VERSION=2.42 IASL_VERSION="R06_28_23" # CLANG version number @@ -72,7 +72,7 @@ GMP_BASE_URL="https://ftpmirror.gnu.org/gmp" MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr" MPC_BASE_URL="https://ftpmirror.gnu.org/mpc" -GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}" +GCC_BASE_URL="https://gcc.gnu.org/pub/gcc/snapshots/${GCC_VERSION}" BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils" IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags" # CLANG toolchain archive locations diff --git a/util/crossgcc/patches/gcc-13.2.0_asan_shadow_offset_callback.patch b/util/crossgcc/patches/gcc-14-20240331_asan_shadow_offset_callback.patch similarity index 100% rename from util/crossgcc/patches/gcc-13.2.0_asan_shadow_offset_callback.patch rename to util/crossgcc/patches/gcc-14-20240331_asan_shadow_offset_callback.patch diff --git a/util/crossgcc/patches/gcc-13.2.0_gnat.patch b/util/crossgcc/patches/gcc-14-20240331_gnat.patch similarity index 100% rename from util/crossgcc/patches/gcc-13.2.0_gnat.patch rename to util/crossgcc/patches/gcc-14-20240331_gnat.patch diff --git a/util/crossgcc/patches/gcc-13.2.0_libcpp.patch b/util/crossgcc/patches/gcc-14-20240331_libcpp.patch similarity index 100% rename from util/crossgcc/patches/gcc-13.2.0_libcpp.patch rename to util/crossgcc/patches/gcc-14-20240331_libcpp.patch diff --git a/util/crossgcc/patches/gcc-13.2.0_libgcc.patch b/util/crossgcc/patches/gcc-14-20240331_libgcc.patch similarity index 100% rename from util/crossgcc/patches/gcc-13.2.0_libgcc.patch rename to util/crossgcc/patches/gcc-14-20240331_libgcc.patch diff --git a/util/crossgcc/patches/gcc-13.2.0_musl_poisoned_calloc.patch b/util/crossgcc/patches/gcc-14-20240331_musl_poisoned_calloc.patch similarity index 87% rename from util/crossgcc/patches/gcc-13.2.0_musl_poisoned_calloc.patch rename to util/crossgcc/patches/gcc-14-20240331_musl_poisoned_calloc.patch index 552a7e7..b66380d 100644 --- a/util/crossgcc/patches/gcc-13.2.0_musl_poisoned_calloc.patch +++ b/util/crossgcc/patches/gcc-14-20240331_musl_poisoned_calloc.patch @@ -23,26 +23,19 @@ /* glibc versions earlier than 2.7 do not define the routines to handle dynamically allocated CPU sets. For these targets, we use the static ---- gcc-13.2.0/gcc/ada/argv.c -+++ gcc-13.2.0.musl/gcc/ada/argv.c -@@ -42,6 +42,8 @@ - main program, and these routines are accessed from the - Ada.Command_Line.Environment package. */ - -+#include "adaint.h" -+ - #ifdef IN_RTS - #include "runtime.h" - #include <stdlib.h> -@@ -50,8 +52,6 @@ - #include "config.h" +--- gcc-14-20240211/gcc/ada/argv.c ++++ gcc-14-20240211.musl/gcc/ada/argv.c +@@ -51,10 +51,6 @@ #include "system.h" #endif -- --#include "adaint.h" +-#ifndef LIGHT_RUNTIME +-#include "adaint.h" +-#endif +- #ifdef __cplusplus extern "C" { + #endif --- gcc-13.2.0/gcc/ada/cio.c +++ gcc-13.2.0.musl/gcc/ada/cio.c @@ -29,6 +29,8 @@ diff --git a/util/crossgcc/patches/gcc-13.2.0_rv32iafc.patch b/util/crossgcc/patches/gcc-14-20240331_rv32iafc.patch similarity index 100% rename from util/crossgcc/patches/gcc-13.2.0_rv32iafc.patch rename to util/crossgcc/patches/gcc-14-20240331_rv32iafc.patch diff --git a/util/crossgcc/sum/gcc-13.2.0.tar.xz.cksum b/util/crossgcc/sum/gcc-13.2.0.tar.xz.cksum deleted file mode 100644 index dcf9d41..0000000 --- a/util/crossgcc/sum/gcc-13.2.0.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -5f95b6d042fb37d45c6cbebfc91decfbc4fb493c tarballs/gcc-13.2.0.tar.xz diff --git a/util/crossgcc/sum/gcc-14-20240303.tar.xz.cksum b/util/crossgcc/sum/gcc-14-20240303.tar.xz.cksum new file mode 100644 index 0000000..c3bfce8 --- /dev/null +++ b/util/crossgcc/sum/gcc-14-20240303.tar.xz.cksum @@ -0,0 +1 @@ +031981472a00e4331e1d55d3264985a906811c5e tarballs/gcc-14-20240303.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/81682?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I91f0a5ab1d44cbf1b6346b08d1d36ddf135d0275 Gerrit-Change-Number: 81682 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: util/crossgcc: Update LLVM from 17.0.6 to 18.1.3
by Felix Singer (Code Review) 06 Apr '24

06 Apr '24

Attention is currently required from: Arthur Heymans, Martin L Roth, Zebreus. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80314?usp=email ) Change subject: util/crossgcc: Update LLVM from 17.0.6 to 18.1.3 ...................................................................... Patch Set 12: (1 comment) Patchset: PS10: > > Great. Thanks for looking into it. I've rebased the patch. Let's see. […] Looks like all previous issues were fixed. One new issue related to the 64bit build of Prodrive Hermes appeared. https://qa.coreboot.org/job/coreboot-toolchain/1602/testReport/(root)/clang… -- To view, visit https://review.coreboot.org/c/coreboot/+/80314?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03a44e0c23a925396f614f282882405dc886ba58 Gerrit-Change-Number: 80314 Gerrit-PatchSet: 12 Gerrit-Owner: Zebreus <lennarteichhorn(a)googlemail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Zebreus <lennarteichhorn(a)googlemail.com> Gerrit-Comment-Date: Sat, 06 Apr 2024 05:22:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/brya: Remove baseboard-specific FMD names
by Dinesh Gehlot (Code Review) 06 Apr '24

06 Apr '24

Attention is currently required from: Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, Sumeet R Pawnikar. Hello Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, Sumeet R Pawnikar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81676?usp=email to look at the new patch set (#2). Change subject: mb/google/brya: Remove baseboard-specific FMD names ...................................................................... mb/google/brya: Remove baseboard-specific FMD names This patch renames the 16MB FMD file to remove the baseboard-specific name 'Nissa'. This allows other supported baseboards to utilize the 16MB SPI flash. Additionally, this patch removes the Nissa-specific 32MB FMD file, as the Nissa board only uses a 16MB SPI flash. Other Brya boards are using the existing generic 32MB chromeos.fmd file. TEST=Build and boot Nivviks. Change-Id: I9151a4bcbe9cc084cc19b1a3e91c0321fe4dcc37 Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/mainboard/google/brya/Kconfig R src/mainboard/google/brya/chromeos-16MiB-debugfsp.fmd R src/mainboard/google/brya/chromeos-16MiB.fmd D src/mainboard/google/brya/chromeos-nissa-32MiB.fmd M src/mainboard/google/brya/chromeos.fmd 5 files changed, 5 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/81676/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81676?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9151a4bcbe9cc084cc19b1a3e91c0321fe4dcc37 Gerrit-Change-Number: 81676 Gerrit-PatchSet: 2 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: acpi: Move acpigen_write_OSC_pci_domain to Xeon-SP
by Shuo Liu (Code Review) 06 Apr '24

06 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Felix Held, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu, Tim Wawrzynczak. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81652?usp=email ) Change subject: acpi: Move acpigen_write_OSC_pci_domain to Xeon-SP ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > Revisited the comments from Nico and Felix, and checking through Linux kernel 5.19. […] As to Point 1, below is a code segment of drivers/acpi/pci_root.c of Linux 5.19.rc8, with below characterstics, 1. one UUID for one PCI root, determined by its role 2. PCI control and CXL control will be handled by one _OSC call instead of 2 separate calls. static acpi_status acpi_pci_run_osc(struct acpi_pci_root *root, const u32 *capbuf, u32 *pci_control, u32 *cxl_control) { struct acpi_osc_context context = { .uuid_str = to_uuid(root), .rev = 1, .cap.length = cap_length(root), .cap.pointer = (void *)capbuf, }; acpi_status status; status = acpi_run_osc(root->device->handle, &context); if (ACPI_SUCCESS(status)) { *pci_control = acpi_osc_ctx_get_pci_control(&context); if (is_cxl(root)) *cxl_control = acpi_osc_ctx_get_cxl_control(&context); kfree(context.ret.pointer); } return status; } -- To view, visit https://review.coreboot.org/c/coreboot/+/81652?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia297e0a828f25b751032f18de04ec76f10131076 Gerrit-Change-Number: 81652 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sat, 06 Apr 2024 04:49:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Enhance portability with uintptr_t/size_t
by Subrata Banik (Code Review) 06 Apr '24

06 Apr '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81615?usp=email ) Change subject: drivers/intel/fsp2_0: Enhance portability with uintptr_t/size_t ...................................................................... drivers/intel/fsp2_0: Enhance portability with uintptr_t/size_t Replace fixed-width integers for pointers and sizes with uintptr_t and size_t, promoting portability across 32-bit and 64-bit architectures. For FSP-API specific UPD assignments, rely on `efi_uintn_t` rather fixed size datatype uint32_t/uint64_t. BUG=b:242829490 TEST=Firmware splash screen visible on google/rex0 w/ both 32-bit and 64-bit compilation. Change-Id: Iab5c612e0640441a2a10e77949416de2afdb8985 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81615 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/drivers/intel/fsp2_0/fsp_gop_blt.c M src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h 2 files changed, 8 insertions(+), 8 deletions(-) Approvals: Elyes Haouas: Looks good to me, approved Matt DeVillier: Looks good to me, but someone else must approve Julius Werner: Looks good to me, approved build bot (Jenkins): Verified Dinesh Gehlot: Looks good to me, approved Ronak Kanabar: Looks good to me, but someone else must approve diff --git a/src/drivers/intel/fsp2_0/fsp_gop_blt.c b/src/drivers/intel/fsp2_0/fsp_gop_blt.c index f59bb86..8292b3b 100644 --- a/src/drivers/intel/fsp2_0/fsp_gop_blt.c +++ b/src/drivers/intel/fsp2_0/fsp_gop_blt.c @@ -133,7 +133,7 @@ /* Fill BMP image into BLT buffer format */ static void *fill_blt_buffer(efi_bmp_image_header *header, - uint32_t logo_ptr, uint32_t blt_buffer_size) + uintptr_t logo_ptr, size_t blt_buffer_size) { efi_graphics_output_blt_pixel *gop_blt_buffer; efi_graphics_output_blt_pixel *gop_blt_ptr; @@ -233,18 +233,18 @@ } /* Convert a *.BMP graphics image to a GOP blt buffer */ -void fsp_convert_bmp_to_gop_blt(uint32_t *logo, uint32_t *logo_size, - uint32_t *blt_ptr, uint32_t *blt_size, +void fsp_convert_bmp_to_gop_blt(efi_uintn_t *logo, uint32_t *logo_size, + efi_uintn_t *blt_ptr, efi_uintn_t *blt_size, uint32_t *pixel_height, uint32_t *pixel_width) { - uint32_t logo_ptr; + uintptr_t logo_ptr; size_t logo_ptr_size, blt_buffer_size; efi_bmp_image_header *bmp_header; if (!logo || !logo_size || !blt_ptr || !blt_size || !pixel_height || !pixel_width) return; - logo_ptr = (uint32_t)(uintptr_t)bmp_load_logo(&logo_ptr_size); + logo_ptr = (uintptr_t)bmp_load_logo(&logo_ptr_size); if (!logo_ptr || logo_ptr_size < sizeof(efi_bmp_image_header)) { printk(BIOS_ERR, "%s: BMP Image size is too small.\n", __func__); @@ -267,5 +267,5 @@ *blt_size = blt_buffer_size; *pixel_height = bmp_header->PixelHeight; *pixel_width = bmp_header->PixelWidth; - *blt_ptr = (uint32_t)fill_blt_buffer(bmp_header, logo_ptr, blt_buffer_size); + *blt_ptr = (uintptr_t)fill_blt_buffer(bmp_header, logo_ptr, blt_buffer_size); } diff --git a/src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h b/src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h index 7ffb54c..ff15483 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h +++ b/src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h @@ -7,8 +7,8 @@ #include <types.h> /* Convert a *.BMP graphics image to a GOP blt buffer */ -void fsp_convert_bmp_to_gop_blt(uint32_t *logo, uint32_t *logo_size, - uint32_t *blt_ptr, uint32_t *blt_size, +void fsp_convert_bmp_to_gop_blt(efi_uintn_t *logo, uint32_t *logo_size, + efi_uintn_t *blt_ptr, efi_uintn_t *blt_size, uint32_t *pixel_height, uint32_t *pixel_width); #endif /* FSP_GOP_BLT_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81615?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab5c612e0640441a2a10e77949416de2afdb8985 Gerrit-Change-Number: 81615 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: lib: Refactor bmp_load_logo() implementation
by Subrata Banik (Code Review) 06 Apr '24

06 Apr '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81618?usp=email ) Change subject: lib: Refactor bmp_load_logo() implementation ...................................................................... lib: Refactor bmp_load_logo() implementation This refactoring ensures bmp_load_logo() takes logo_size as an argument, returning a valid logo_ptr only if logo_size is non-zero. This prevents potential errors from mismatched size assumption. BUG=b:242829490 TEST=google/rex0 builds successfully. Change-Id: I14bc54670a67980ec93bc366b274832d1f959e50 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81618 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/drivers/intel/fsp1_1/ramstage.c M src/drivers/intel/fsp2_0/fsp_gop_blt.c M src/include/bootsplash.h M src/lib/bmp_logo.c M src/soc/amd/mendocino/fsp_s_params.c M src/soc/intel/apollolake/chip.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/skylake/chip.c 8 files changed, 29 insertions(+), 17 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Matt DeVillier: Looks good to me, but someone else must approve Dinesh Gehlot: Looks good to me, approved diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 5c40966..713770a 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -76,9 +76,11 @@ load_vbt(&silicon_init_params); mainboard_silicon_init_params(&silicon_init_params); - if (CONFIG(BMP_LOGO)) - bmp_load_logo(&silicon_init_params.PcdLogoPtr, - &silicon_init_params.PcdLogoSize); + if (CONFIG(BMP_LOGO)) { + size_t logo_size; + silicon_init_params.PcdLogoPtr = (uint32_t)(uintptr_t)bmp_load_logo(&logo_size); + silicon_init_params.PcdLogoSize = (uint32_t)logo_size; + } /* Display the UPD data */ if (CONFIG(DISPLAY_UPD_DATA)) diff --git a/src/drivers/intel/fsp2_0/fsp_gop_blt.c b/src/drivers/intel/fsp2_0/fsp_gop_blt.c index 8b64502..f59bb86 100644 --- a/src/drivers/intel/fsp2_0/fsp_gop_blt.c +++ b/src/drivers/intel/fsp2_0/fsp_gop_blt.c @@ -237,13 +237,15 @@ uint32_t *blt_ptr, uint32_t *blt_size, uint32_t *pixel_height, uint32_t *pixel_width) { - uint32_t logo_ptr, logo_ptr_size, blt_buffer_size; + uint32_t logo_ptr; + size_t logo_ptr_size, blt_buffer_size; efi_bmp_image_header *bmp_header; if (!logo || !logo_size || !blt_ptr || !blt_size || !pixel_height || !pixel_width) return; - bmp_load_logo(&logo_ptr, &logo_ptr_size); + logo_ptr = (uint32_t)(uintptr_t)bmp_load_logo(&logo_ptr_size); + if (!logo_ptr || logo_ptr_size < sizeof(efi_bmp_image_header)) { printk(BIOS_ERR, "%s: BMP Image size is too small.\n", __func__); return; diff --git a/src/include/bootsplash.h b/src/include/bootsplash.h index 86048a4..372e8c2 100644 --- a/src/include/bootsplash.h +++ b/src/include/bootsplash.h @@ -20,7 +20,7 @@ * For example: Introduce configurable BMP logo for customization on platforms like ChromeOS */ const char *bmp_logo_filename(void); -void bmp_load_logo(uint32_t *logo_ptr, uint32_t *logo_size); +void *bmp_load_logo(size_t *logo_size); void bmp_release_logo(void); #endif diff --git a/src/lib/bmp_logo.c b/src/lib/bmp_logo.c index 2888777..becb605 100644 --- a/src/lib/bmp_logo.c +++ b/src/lib/bmp_logo.c @@ -16,25 +16,27 @@ } #endif -void bmp_load_logo(uint32_t *logo_ptr, uint32_t *logo_size) +void *bmp_load_logo(size_t *logo_size) { void *logo_buffer; /* CBMEM is locked for S3 resume path. */ if (acpi_is_wakeup_s3()) - return; + return NULL; logo_entry = cbmem_entry_add(CBMEM_ID_FSP_LOGO, 1 * MiB); if (!logo_entry) - return; + return NULL; logo_buffer = cbmem_entry_start(logo_entry); if (!logo_buffer) - return; + return NULL; *logo_size = cbfs_load(bmp_logo_filename(), logo_buffer, 1 * MiB); - if (*logo_size) - *logo_ptr = (uintptr_t)logo_buffer; + if (*logo_size == 0) + return NULL; + + return logo_buffer; } void bmp_release_logo(void) diff --git a/src/soc/amd/mendocino/fsp_s_params.c b/src/soc/amd/mendocino/fsp_s_params.c index 8374fb3..50923e9 100644 --- a/src/soc/amd/mendocino/fsp_s_params.c +++ b/src/soc/amd/mendocino/fsp_s_params.c @@ -55,6 +55,6 @@ void soc_load_logo(FSPS_UPD *supd) { - uint32_t logo_size; - bmp_load_logo(&supd->FspsConfig.logo_bmp_buffer, &logo_size); + size_t logo_size; + supd->FspsConfig.logo_bmp_buffer = (uint32_t)(uintptr_t)bmp_load_logo(&logo_size); } diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 91e39c9..1d15eec 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -915,7 +915,9 @@ /* Handle FSP logo params */ void soc_load_logo(FSPS_UPD *supd) { - bmp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize); + size_t logo_size; + supd->FspsConfig.LogoPtr = (uint32_t)(uintptr_t)bmp_load_logo(&logo_size); + supd->FspsConfig.LogoSize = (uint32_t)logo_size; } BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL); diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index c9ef548..e1eede2 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -754,5 +754,7 @@ /* Handle FSP logo params */ void soc_load_logo(FSPS_UPD *supd) { - bmp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize); + size_t logo_size; + supd->FspsConfig.LogoPtr = (uintptr_t)bmp_load_logo(&logo_size); + supd->FspsConfig.LogoSize = (uint32_t)logo_size; } diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index ea091ce..050a272 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -529,5 +529,7 @@ /* Handle FSP logo params */ void soc_load_logo(FSPS_UPD *supd) { - bmp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize); + size_t logo_size; + supd->FspsConfig.LogoPtr = (uint32_t)(uintptr_t)bmp_load_logo(&logo_size); + supd->FspsConfig.LogoSize = (uint32_t)logo_size; } -- To view, visit https://review.coreboot.org/c/coreboot/+/81618?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I14bc54670a67980ec93bc366b274832d1f959e50 Gerrit-Change-Number: 81618 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/google/brya: Add new baseboard trulo
by Dinesh Gehlot (Code Review) 06 Apr '24

06 Apr '24

Attention is currently required from: Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, Sumeet R Pawnikar, Varshit Pandya. Dinesh Gehlot has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81626?usp=email ) Change subject: mb/google/brya: Add new baseboard trulo ...................................................................... Patch Set 12: (1 comment) File src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb: https://review.coreboot.org/c/coreboot/+/81626/comment/46e95d49_d0956a7d : PS12, Line 1: alderlake > Please confirm on this alderlake or twinlake ? […] Device tree should align with alderlake as trulo is ADL-N based design, same as nissa. -- To view, visit https://review.coreboot.org/c/coreboot/+/81626?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iad6230064c6b8359698d37c3e0440614cc7b073d Gerrit-Change-Number: 81626 Gerrit-PatchSet: 12 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 06 Apr 2024 04:01:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: util/intelp2m: Avoid adding blank line after '{'
by Nicholas Sudsgaard (Code Review) 06 Apr '24

06 Apr '24

Attention is currently required from: Elyes Haouas, Maxim. Nicholas Sudsgaard has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81547?usp=email ) Change subject: util/intelp2m: Avoid adding blank line after '{' ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81547?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8105734b1b4776d0eb01b13c80e21e130719fe83 Gerrit-Change-Number: 81547 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 06 Apr 2024 03:59:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: acpi: Move acpigen_write_OSC_pci_domain to Xeon-SP
by Shuo Liu (Code Review) 06 Apr '24

06 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Felix Held, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu, Tim Wawrzynczak. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81652?usp=email ) Change subject: acpi: Move acpigen_write_OSC_pci_domain to Xeon-SP ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: An improved version is updated. After direction is confirmed, I will redo tests. -- To view, visit https://review.coreboot.org/c/coreboot/+/81652?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia297e0a828f25b751032f18de04ec76f10131076 Gerrit-Change-Number: 81652 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sat, 06 Apr 2024 03:40:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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