coreboot-gerrit April 2024

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[XS] Change in coreboot[main]: superio/nuvoton/nct6779d: Allow swapping PS/2 keyboard/mouse ports
by Keith Hui (Code Review) 13 Apr '24

13 Apr '24

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81884?usp=email ) Change subject: superio/nuvoton/nct6779d: Allow swapping PS/2 keyboard/mouse ports ...................................................................... superio/nuvoton/nct6779d: Allow swapping PS/2 keyboard/mouse ports Add nvram option to allow user to manually swap PS/2 keyboard and mouse ports (i.e. keyboard port serves the mouse instead). This is intended for mainboards with only one PS/2 port for either keyboard or mouse. Until coreboot gets improved keyboard and mouse detection and initialization and can decide on its own when to swap, this option allows PS/2 mouse connected to this one port a chance to work in the OS. Without this support, the one PS/2 port works with keyboards only. TEST=With nvram option added to asus/p8x7x-series/v/p8z77-m and turned on, PS/2 mouse works. Change-Id: I2d58719c207da973ad049cb9151d92f31ff6cd92 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/superio/nuvoton/nct6779d/superio.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/81884/1 diff --git a/src/superio/nuvoton/nct6779d/superio.c b/src/superio/nuvoton/nct6779d/superio.c index e908c9c..09942d6 100644 --- a/src/superio/nuvoton/nct6779d/superio.c +++ b/src/superio/nuvoton/nct6779d/superio.c @@ -12,6 +12,7 @@ { uint8_t byte; uint8_t power_status; + uint8_t swap_kbd_mouse; if (!dev->enabled) return; @@ -38,12 +39,20 @@ power_status = get_uint_option("power_on_after_fail", CONFIG_MAINBOARD_POWER_FAILURE_STATE) & 0x03; + swap_kbd_mouse = get_uint_option("swap_keyboard_and_mouse", 0) & 0x1; pnp_enter_conf_mode(dev); pnp_set_logical_device(dev); byte = pnp_read_config(dev, 0xe4); byte &= ~0x60; byte |= (power_status << 5); pnp_write_config(dev, 0xe4, byte); + /* Swap keyboard and mouse port if requested */ + byte = pnp_read_config(dev, 0xe0); + if (swap_kbd_mouse) + byte |= (1 << 2); + else + byte &= ~(1 << 2); + pnp_write_config(dev, 0xe0, byte); pnp_exit_conf_mode(dev); break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/81884?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d58719c207da973ad049cb9151d92f31ff6cd92 Gerrit-Change-Number: 81884 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: superio/nuvoton/nct6779d: Add power_on_after_fail support
by Keith Hui (Code Review) 13 Apr '24

13 Apr '24

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81883?usp=email ) Change subject: superio/nuvoton/nct6779d: Add power_on_after_fail support ...................................................................... superio/nuvoton/nct6779d: Add power_on_after_fail support Using code from superio/nuvoton/nct5572d (which has the same registers as '6779), add support for configuring power state after power failure using power_on_after_fail nvram option. TEST=Set nvram option to "enable" on mainboard/asus/p8z77-m, pulled power plug, board powers on after restoring power. Board remains off after power restore with nvram option set to "keep". Super I/O configured correctly per datasheet and superiotool -d. Change-Id: Ia08cf8daac971397e832996ed364d41e9e7b1c5d Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/superio/nuvoton/nct6779d/Kconfig M src/superio/nuvoton/nct6779d/superio.c 2 files changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/81883/1 diff --git a/src/superio/nuvoton/nct6779d/Kconfig b/src/superio/nuvoton/nct6779d/Kconfig index ce2af16..f60cf1c 100644 --- a/src/superio/nuvoton/nct6779d/Kconfig +++ b/src/superio/nuvoton/nct6779d/Kconfig @@ -3,3 +3,5 @@ config SUPERIO_NUVOTON_NCT6779D bool select SUPERIO_NUVOTON_COMMON_PRE_RAM + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE diff --git a/src/superio/nuvoton/nct6779d/superio.c b/src/superio/nuvoton/nct6779d/superio.c index 1360476..e908c9c 100644 --- a/src/superio/nuvoton/nct6779d/superio.c +++ b/src/superio/nuvoton/nct6779d/superio.c @@ -3,12 +3,16 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> +#include <option.h> #include <superio/conf_mode.h> #include "nct6779d.h" static void nct6779d_init(struct device *dev) { + uint8_t byte; + uint8_t power_status; + if (!dev->enabled) return; @@ -17,6 +21,31 @@ case NCT6779D_KBC: pc_keyboard_init(NO_AUX_DEVICE); break; + case NCT6779D_ACPI: + /* Set power state after power fail. + * NOTE: This depends on CONFIG_MAINBOARD_POWER_FAILURE_STATE to be defined as: + * + * config MAINBOARD_POWER_FAILURE_STATE + * int + * default 2 if POWER_STATE_PREVIOUS_AFTER_FAILURE + * default 1 if POWER_STATE_ON_AFTER_FAILURE + * default 0 + * + * ... matching this hardware. + * If this definition changes, this code has to be adapted similar to + * NCT5572D. + */ + + power_status = get_uint_option("power_on_after_fail", + CONFIG_MAINBOARD_POWER_FAILURE_STATE) & 0x03; + pnp_enter_conf_mode(dev); + pnp_set_logical_device(dev); + byte = pnp_read_config(dev, 0xe4); + byte &= ~0x60; + byte |= (power_status << 5); + pnp_write_config(dev, 0xe4, byte); + pnp_exit_conf_mode(dev); + break; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/81883?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia08cf8daac971397e832996ed364d41e9e7b1c5d Gerrit-Change-Number: 81883 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: SNB/BD82x6x boards: Remove old USB configurations
by Keith Hui (Code Review) 13 Apr '24

13 Apr '24

Attention is currently required from: Alexander Couzens, Angel Pons, Evgeny Zinoviev, Kevin Keijzer. Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81882?usp=email ) Change subject: SNB/BD82x6x boards: Remove old USB configurations ...................................................................... SNB/BD82x6x boards: Remove old USB configurations Remove USB configurations and data structures from northbridge devicetree (SNB+MRC boards) and bootblock/romstage C code (native-only SNB boards). All USB configurations are drawn from southbridge devicetree going forward. Change-Id: Ie1cd21077136998a6e90050c95263f2efed68a67 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/apple/macbookair4_2/early_init.c M src/mainboard/asrock/b75m-itx/Makefile.mk D src/mainboard/asrock/b75m-itx/early_init.c M src/mainboard/asrock/b75pro3-m/early_init.c M src/mainboard/asrock/h77pro4-m/early_init.c M src/mainboard/asus/h61-series/variants/h61m-cs/early_init.c M src/mainboard/asus/h61-series/variants/p8h61-m_lx/early_init.c M src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/early_init.c M src/mainboard/asus/h61-series/variants/p8h61-m_pro/early_init.c M src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/early_init.c M src/mainboard/asus/maximus_iv_gene-z/early_init.c M src/mainboard/asus/p8x7x-series/devicetree.cb M src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c M src/mainboard/biostar/th61-itx/Makefile.mk M src/mainboard/compulab/intense_pc/early_init.c M src/mainboard/dell/snb_ivb_workstations/early_init.c M src/mainboard/gigabyte/ga-b75m-d3h/early_init.c M src/mainboard/gigabyte/ga-h61m-series/early_init.c M src/mainboard/google/butterfly/devicetree.cb M src/mainboard/google/butterfly/early_init.c M src/mainboard/google/link/devicetree.cb M src/mainboard/google/link/early_init.c M src/mainboard/google/parrot/devicetree.cb M src/mainboard/google/parrot/early_init.c M src/mainboard/google/stout/devicetree.cb M src/mainboard/google/stout/early_init.c M src/mainboard/intel/dcp847ske/devicetree.cb M src/mainboard/intel/dcp847ske/early_southbridge.c D src/mainboard/intel/dcp847ske/usb.h M src/mainboard/intel/dq67sw/early_init.c M src/mainboard/intel/emeraldlake2/devicetree.cb M src/mainboard/intel/emeraldlake2/early_init.c M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/kontron/ktqm77/early_init.c M src/mainboard/lenovo/l520/Makefile.mk D src/mainboard/lenovo/l520/early_init.c M src/mainboard/lenovo/s230u/early_init.c M src/mainboard/lenovo/t420/early_init.c M src/mainboard/lenovo/t420s/early_init.c M src/mainboard/lenovo/t430/early_init.c M src/mainboard/lenovo/x220/Makefile.mk M src/mainboard/lenovo/x220/devicetree.cb D src/mainboard/lenovo/x220/variants/x1/romstage.c D src/mainboard/lenovo/x220/variants/x220/romstage.c M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rv11/early_init.c M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/early_init.c M src/mainboard/samsung/lumpy/devicetree.cb M src/mainboard/samsung/lumpy/early_init.c M src/mainboard/samsung/stumpy/devicetree.cb M src/mainboard/samsung/stumpy/early_init.c M src/mainboard/sapphire/pureplatinumh61/early_init.c M src/northbridge/intel/sandybridge/chip.h M src/southbridge/intel/bd82x6x/pch.h 62 files changed, 0 insertions(+), 941 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/81882/1 diff --git a/src/mainboard/apple/macbookair4_2/early_init.c b/src/mainboard/apple/macbookair4_2/early_init.c index fc4b215..8eeb482 100644 --- a/src/mainboard/apple/macbookair4_2/early_init.c +++ b/src/mainboard/apple/macbookair4_2/early_init.c @@ -1,24 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <northbridge/intel/sandybridge/raminit.h> -#include <southbridge/intel/bd82x6x/pch.h> - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, -1 }, /* USB HUB 1 */ - { 0, 0, -1 }, /* Unused */ - { 0, 0, -1 }, /* Unused */ - { 0, 0, -1 }, /* Unused */ - { 0, 0, -1 }, /* Unused */ - { 0, 0, -1 }, /* Unused */ - { 0, 0, -1 }, /* Unused */ - { 0, 0, -1 }, /* Unused */ - { 1, 0, -1 }, /* USB HUB 2 */ - { 1, 0, -1 }, /* Camera */ - { 0, 0, -1 }, /* Unused */ - { 0, 0, -1 }, /* Unused */ - { 0, 0, -1 }, /* Unused */ - { 0, 0, -1 }, /* Unused */ -}; void mb_get_spd_map(struct spd_info *spdi) { diff --git a/src/mainboard/asrock/b75m-itx/Makefile.mk b/src/mainboard/asrock/b75m-itx/Makefile.mk index d1b484d..ae57dab 100644 --- a/src/mainboard/asrock/b75m-itx/Makefile.mk +++ b/src/mainboard/asrock/b75m-itx/Makefile.mk @@ -3,6 +3,4 @@ bootblock-y += gpio.c romstage-y += gpio.c -bootblock-y += early_init.c -romstage-y += early_init.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/b75m-itx/early_init.c b/src/mainboard/asrock/b75m-itx/early_init.c deleted file mode 100644 index b70794a..0000000 --- a/src/mainboard/asrock/b75m-itx/early_init.c +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <bootblock_common.h> -#include <southbridge/intel/bd82x6x/pch.h> - -const struct southbridge_usb_port mainboard_usb_ports[] = { - {1, 0, 0}, {1, 0, 0}, {1, 1, 1}, {1, 1, 1}, {1, 1, 2}, {1, 1, 2}, {1, 0, 3}, - {1, 0, 3}, {1, 0, 4}, {1, 0, 4}, {1, 0, 6}, {1, 1, 5}, {1, 1, 5}, {1, 0, 6}, -}; diff --git a/src/mainboard/asrock/b75pro3-m/early_init.c b/src/mainboard/asrock/b75pro3-m/early_init.c index 4052b6f..1ffd896 100644 --- a/src/mainboard/asrock/b75pro3-m/early_init.c +++ b/src/mainboard/asrock/b75pro3-m/early_init.c @@ -8,23 +8,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 1, 1 }, - { 1, 1, 1 }, - { 1, 1, 2 }, - { 1, 1, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 1, 5 }, - { 1, 1, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { /* Set GPIOs on superio, enable UART */ diff --git a/src/mainboard/asrock/h77pro4-m/early_init.c b/src/mainboard/asrock/h77pro4-m/early_init.c index 4637378..df8f043 100644 --- a/src/mainboard/asrock/h77pro4-m/early_init.c +++ b/src/mainboard/asrock/h77pro4-m/early_init.c @@ -21,23 +21,6 @@ CPU_FAN_HEADER_BOTH }; -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 1, 1 }, - { 1, 1, 1 }, - { 1, 1, 2 }, - { 1, 1, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 1, 5 }, - { 1, 1, 5 }, - { 1, 0, 6 }, -}; - /* * The tachometer signal that goes to CPUFANIN of the Super I/O is set via * GPIOs. diff --git a/src/mainboard/asus/h61-series/variants/h61m-cs/early_init.c b/src/mainboard/asus/h61-series/variants/h61m-cs/early_init.c index 50e225a..bec2f6d 100644 --- a/src/mainboard/asus/h61-series/variants/h61m-cs/early_init.c +++ b/src/mainboard/asus/h61-series/variants/h61m-cs/early_init.c @@ -10,23 +10,6 @@ #define SIO_DEV PNP_DEV(SIO_PORT, 0) #define ACPI_DEV PNP_DEV(SIO_PORT, NCT6779D_ACPI) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { nuvoton_pnp_enter_conf_state(SIO_DEV); diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/early_init.c b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/early_init.c index 5f5c684..2217a6c 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/early_init.c +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/early_init.c @@ -7,23 +7,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/early_init.c b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/early_init.c index 404a850..8f716da 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/early_init.c +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/early_init.c @@ -9,23 +9,6 @@ #define GLOBAL_DEV PNP_DEV(0x2e, 0) #define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { nuvoton_pnp_enter_conf_state(GLOBAL_DEV); diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/early_init.c b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/early_init.c index 1c8d844..d7cd486 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/early_init.c +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/early_init.c @@ -10,23 +10,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) #define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { /* Enable UART */ diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/early_init.c b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/early_init.c index e76e109..dc00ec3 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/early_init.c +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/early_init.c @@ -10,23 +10,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) #define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { nuvoton_pnp_enter_conf_state(GLOBAL_DEV); diff --git a/src/mainboard/asus/maximus_iv_gene-z/early_init.c b/src/mainboard/asus/maximus_iv_gene-z/early_init.c index ed593f6..bd741c3 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/early_init.c +++ b/src/mainboard/asus/maximus_iv_gene-z/early_init.c @@ -6,23 +6,6 @@ #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h> -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { static const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); diff --git a/src/mainboard/asus/p8x7x-series/devicetree.cb b/src/mainboard/asus/p8x7x-series/devicetree.cb index 4052cf4..e9b97bc 100644 --- a/src/mainboard/asus/p8x7x-series/devicetree.cb +++ b/src/mainboard/asus/p8x7x-series/devicetree.cb @@ -7,11 +7,6 @@ register "max_mem_clock_mhz" = "800" register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" - register "usb_port_config" = "{ - {1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080}, - {1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080}, - {1, 6, 0x0080}, {1, 5, 0x0080}, {1, 5, 0x0080}, {1, 6, 0x0080} - }" # 4 bit switch mask. 0=not switchable, 1=switchable # Means once it's loaded the OS, it can swap ports # from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c index 79b67f0..1e21f20 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c @@ -10,23 +10,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) #define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { nuvoton_pnp_enter_conf_state(GLOBAL_DEV); diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c index 89f9eee..056dfd4 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c @@ -10,23 +10,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) #define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { nuvoton_pnp_enter_conf_state(GLOBAL_DEV); diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c index 47c5cb3..6897658 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c @@ -12,24 +12,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* {enable, current, oc_pin} */ - {1, 2, 0}, /* Port 0: USB3 front internal header, top */ - {1, 2, 0}, /* Port 1: USB3 front internal header, bottom */ - {1, 2, 1}, /* Port 2: USB3 rear, top */ - {1, 2, 1}, /* Port 3: USB3 rear, bottom */ - {1, 2, 2}, /* Port 4: USB2 rear, PS2 top */ - {1, 2, 2}, /* Port 5: USB2 rear, PS2 bottom */ - {1, 2, 3}, /* Port 6: USB2 rear, ETH, top */ - {1, 2, 3}, /* Port 7: USB2 rear, ETH, bottom */ - {1, 2, 4}, /* Port 8: USB2 internal header USB910, top */ - {1, 2, 4}, /* Port 9: USB2 internal header USB910, bottom */ - {1, 2, 6}, /* Port 10: USB2 internal header USB1112, top */ - {1, 2, 5}, /* Port 11: USB2 internal header USB1112, bottom */ - {1, 2, 5}, /* Port 12: USB2 internal header USB1314, top */ - {1, 2, 6} /* Port 13: USB2 internal header USB1314, bottom */ -}; - void bootblock_mainboard_early_init(void) { nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb index c15767b..25e098d4d 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb @@ -1,11 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/sandybridge - register "usb_port_config" = "{ - {1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080}, - {1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080}, - {1, 6, 0x0080}, {1, 5, 0x0080}, {1, 5, 0x0080}, {1, 6, 0x0080} - }" device domain 0 on subsystemid 0x1043 0x84ca inherit chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c index cec5070..4940b54 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c @@ -14,24 +14,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP2) -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* {enable, current, oc_pin} */ - { 1, 2, 0 }, /* Port 0: USB3 front internal header, top */ - { 1, 2, 0 }, /* Port 1: USB3 front internal header, bottom */ - { 1, 2, 1 }, /* Port 2: USB3 rear, ETH top */ - { 1, 2, 1 }, /* Port 3: USB3 rear, ETH bottom */ - { 1, 2, 2 }, /* Port 4: USB2 rear, PS2 top */ - { 1, 2, 2 }, /* Port 5: USB2 rear, PS2 bottom */ - { 1, 2, 3 }, /* Port 6: USB2 internal header USB78, top */ - { 1, 2, 3 }, /* Port 7: USB2 internal header USB78, bottom */ - { 1, 2, 4 }, /* Port 8: USB2 internal header USB910, top */ - { 1, 2, 4 }, /* Port 9: USB2 internal header USB910, bottom */ - { 1, 2, 6 }, /* Port 10: USB2 internal header USB1112, top */ - { 1, 2, 5 }, /* Port 11: USB2 internal header USB1112, bottom */ - { 0, 2, 5 }, /* Port 12: Unused. Asus proprietary DEBUG_PORT ??? */ - { 0, 2, 6 } /* Port 13: Unused. Asus proprietary DEBUG_PORT ??? */ -}; - void bootblock_mainboard_early_init(void) { nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb index 1a011c3..265bada 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb @@ -1,11 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/sandybridge - register "usb_port_config" = "{ - {1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080}, - {1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080}, - {1, 6, 0x0080}, {1, 5, 0x0080}, {0, 5, 0x0080}, {0, 6, 0x0080} - }" device domain 0 on subsystemid 0x1043 0x84ca inherit chip southbridge/intel/bd82x6x diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c index c16b055..290523f 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c @@ -11,23 +11,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) #define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 2, 0 }, - { 1, 2, 0 }, - { 1, 2, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 2, 2 }, - { 1, 2, 3 }, - { 1, 2, 3 }, - { 1, 2, 4 }, - { 1, 0, 4 }, - { 1, 2, 6 }, - { 1, 2, 5 }, - { 1, 2, 5 }, - { 1, 2, 6 }, -}; - void bootblock_mainboard_early_init(void) { nuvoton_pnp_enter_conf_state(GLOBAL_DEV); diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c index 89f9eee..056dfd4 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c @@ -10,23 +10,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) #define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { nuvoton_pnp_enter_conf_state(GLOBAL_DEV); diff --git a/src/mainboard/biostar/th61-itx/Makefile.mk b/src/mainboard/biostar/th61-itx/Makefile.mk index 33b55d2..51125d3 100644 --- a/src/mainboard/biostar/th61-itx/Makefile.mk +++ b/src/mainboard/biostar/th61-itx/Makefile.mk @@ -5,5 +5,3 @@ ramstage-y += hda_verb.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -bootblock-y += early_init.c -romstage-y += early_init.c diff --git a/src/mainboard/compulab/intense_pc/early_init.c b/src/mainboard/compulab/intense_pc/early_init.c index f5859e9..4a4308e 100644 --- a/src/mainboard/compulab/intense_pc/early_init.c +++ b/src/mainboard/compulab/intense_pc/early_init.c @@ -8,23 +8,6 @@ #define SIO_PORT 0x164e -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, - { 1, 1, 0 }, - { 1, 1, 1 }, - { 1, 1, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 1, 4 }, - { 1, 1, 4 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { const u16 port = SIO_PORT; diff --git a/src/mainboard/dell/snb_ivb_workstations/early_init.c b/src/mainboard/dell/snb_ivb_workstations/early_init.c index 4a381df..9ddbaf9 100644 --- a/src/mainboard/dell/snb_ivb_workstations/early_init.c +++ b/src/mainboard/dell/snb_ivb_workstations/early_init.c @@ -9,23 +9,6 @@ #include <baseboard/sch5545_ec.h> -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 6, 0 }, - { 1, 6, 0 }, - { 1, 1, 1 }, - { 1, 1, 1 }, - { 1, 1, 2 }, - { 1, 1, 2 }, - { 1, 6, 3 }, - { 1, 6, 3 }, - { 1, 6, 4 }, - { 1, 6, 4 }, - { 1, 6, 5 }, - { 1, 1, 5 }, - { 1, 1, 6 }, - { 1, 6, 6 }, -}; - void bootblock_mainboard_early_init(void) { /* diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c index 8fd6f98..eea5b20 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c @@ -39,20 +39,3 @@ ite_reg_write(IT8728F_EC, 0x63, 0x20); ite_reg_write(IT8728F_EC, 0x30, 0x01); } - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 5, 0 }, - { 1, 5, 0 }, - { 1, 5, 1 }, - { 1, 5, 1 }, - { 1, 5, 2 }, - { 1, 5, 2 }, - { 1, 5, 3 }, - { 1, 5, 3 }, - { 1, 5, 4 }, - { 1, 5, 4 }, - { 1, 5, 6 }, - { 1, 5, 5 }, - { 1, 5, 5 }, - { 1, 5, 6 }, -}; diff --git a/src/mainboard/gigabyte/ga-h61m-series/early_init.c b/src/mainboard/gigabyte/ga-h61m-series/early_init.c index 6f9109a..80a3f0f 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/early_init.c +++ b/src/mainboard/gigabyte/ga-h61m-series/early_init.c @@ -9,23 +9,6 @@ #define SUPERIO_GPIO PNP_DEV(0x2e, IT8728F_GPIO) #define SERIAL_DEV PNP_DEV(0x2e, 0x01) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { if (!CONFIG(NO_UART_ON_SUPERIO)) { diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index a001f73..3a386c6 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -25,22 +25,6 @@ # Force double refresh rate register "ddr_refresh_rate_config" = "DDR_REFRESH_RATE_DOUBLE" - register "usb_port_config" = "{ - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 4, 0x0000 }, - { 1, 4, 0x0080 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 },}" - device domain 0 on device ref host_bridge on end # host bridge device ref peg10 off end # PCIe Bridge for discrete graphics diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index f63d3c3..8d07a38 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -44,24 +44,6 @@ DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); } -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power USB oc pin */ - { 1, 0, -1 }, /* P0: Right USB 3.0 #1 (no OC) */ - { 1, 0, -1 }, /* P1: Right USB 3.0 #2 (no OC) */ - { 1, 0, -1 }, /* P2: Camera (no OC) */ - { 0, 0, -1 }, /* P3: Empty */ - { 0, 0, -1 }, /* P4: Empty */ - { 0, 0, -1 }, /* P5: Empty */ - { 0, 0, -1 }, /* P6: Empty */ - { 0, 0, -1 }, /* P7: Empty */ - { 0, 0, -1 }, /* P8: Empty */ - { 1, 1, -1 }, /* P9: Left USB 1 (no OC) */ - { 1, 0, -1 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ - { 0, 0, -1 }, /* P11: Empty */ - { 0, 0, -1 }, /* P12: Empty */ - { 0, 0, -1 }, /* P13: Empty */ -}; - void mainboard_fill_pei_data(struct pei_data *pei_data) { /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 39b8452..ed49d16 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -22,22 +22,6 @@ # FIXME: Native raminit requires reduced max clock register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800" - register "usb_port_config" = "{ - { 0, 3, 0x0000 }, - { 1, 0, 0x0040 }, - { 1, 1, 0x0040 }, - { 1, 3, 0x0040 }, - { 0, 3, 0x0000 }, - { 1, 3, 0x0040 }, - { 0, 3, 0x0000 }, - { 0, 3, 0x0000 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 },}" - device domain 0 on subsystemid 0x1ae0 0xc000 inherit device ref host_bridge on end # host bridge diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index e40531d..2d20ac0 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -63,24 +63,6 @@ /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ } -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power USB oc pin */ - { 0, 0, -1 }, /* P0: Empty */ - { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ - { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ - { 1, 0, -1 }, /* P3: SDCARD (no OC) */ - { 0, 0, -1 }, /* P4: Empty */ - { 1, 0, -1 }, /* P5: WWAN (no OC) */ - { 0, 0, -1 }, /* P6: Empty */ - { 0, 0, -1 }, /* P7: Empty */ - { 1, 0, -1 }, /* P8: Camera (no OC) */ - { 1, 0, -1 }, /* P9: Bluetooth (no OC) */ - { 0, 0, -1 }, /* P10: Empty */ - { 0, 0, -1 }, /* P11: Empty */ - { 0, 0, -1 }, /* P12: Empty */ - { 0, 0, -1 }, /* P13: Empty */ -}; - void mb_get_spd_map(struct spd_info *spdi) { /* LINK has 2 channels of memory down */ diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index da7c388..ea36b9e 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -22,22 +22,6 @@ # FIXME: Native raminit requires reduced max clock register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800" - register "usb_port_config" = "{ - { 0, 3, 0x0000 }, - { 1, 0, 0x0040 }, - { 1, 1, 0x0040 }, - { 1, 1, 0x0040 }, - { 0, 3, 0x0000 }, - { 0, 3, 0x0000 }, - { 0, 3, 0x0000 }, - { 0, 3, 0x0000 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 },}" - device domain 0 on device ref host_bridge on end # host bridge device ref igd on end # vga controller diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index f91b7d9..077cb64 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -50,22 +50,3 @@ { /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ } - -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power USB oc pin */ - { 0, 0, -1 }, /* P0: Empty */ - { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ - { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ - { 1, 0, 1 }, /* P3: Left USB 3 (OC1) */ - { 0, 0, -1 }, /* P4: Empty */ - { 0, 0, -1 }, /* P5: Empty */ - { 0, 0, -1 }, /* P6: Empty */ - { 0, 0, -1 }, /* P7: Empty */ - /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ - { 1, 0, -1 }, /* P8: MiniPCIe (WLAN) (no OC) */ - { 0, 0, -1 }, /* P9: Empty */ - { 1, 0, -1 }, /* P10: Camera (no OC) */ - { 0, 0, -1 }, /* P11: Empty */ - { 0, 0, -1 }, /* P12: Empty */ - { 0, 0, -1 }, /* P13: Empty */ -}; diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 0c029fa..ccbfa31 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -22,22 +22,6 @@ # FIXME: Native raminit requires reduced max clock register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800" - register "usb_port_config" = "{ - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 0, 1, 0x0000 }, - { 1, 1, 0x0040 }, - { 1, 1, 0x0040 }, - { 1, 1, 0x0040 }, - { 0, 1, 0x0000 }, - { 0, 1, 0x0000 }, - { 0, 5, 0x0000 }, - { 1, 4, 0x0040 }, - { 0, 5, 0x0000 }, - { 0, 5, 0x0000 }, - { 0, 5, 0x0000 }, - { 1, 5, 0x0040 },}" - register "usb3.mode" = "2" # Auto register "usb3.hs_port_switch_mask" = "3" # Ports 0 & 1 register "usb3.preboot_support" = "0" # No PreOS boot support diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index e6e6227..178d270 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -90,21 +90,3 @@ early_ec_init(); } } - -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled USB oc pin length */ - {1, 0, 0}, /* P0: USB 3.0 1 (OC0) */ - {1, 0, 0}, /* P1: USB 3.0 2 (OC0) */ - {0, 0, 0}, /* P2: Empty */ - {1, 0, -1}, /* P3: Camera (no OC) */ - {1, 0, -1}, /* P4: WLAN (no OC) */ - {1, 0, -1}, /* P5: WWAN (no OC) */ - {0, 0, 0}, /* P6: Empty */ - {0, 0, 0}, /* P7: Empty */ - {0, 0, 0}, /* P8: Empty */ - {1, 0, 4}, /* P9: USB 2.0 (AUO4) (OC4) */ - {0, 0, 0}, /* P10: Empty */ - {0, 0, 0}, /* P11: Empty */ - {0, 0, 0}, /* P12: Empty */ - {1, 0, -1}, /* P13: Bluetooth (no OC) */ -}; diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb index 46624fb..617cca6 100644 --- a/src/mainboard/intel/dcp847ske/devicetree.cb +++ b/src/mainboard/intel/dcp847ske/devicetree.cb @@ -15,22 +15,6 @@ register "max_mem_clock_mhz" = "666" register "spd_addresses" = "{0x50, 0, 0x51, 0}" - register "usb_port_config" = "{ - {1, 0, 0x0040}, - {1, 0, 0x0040}, - {1, 1, 0x0040}, - {1, 1, 0x0040}, - {1, 2, 0x0040}, - {1, 2, 0x0040}, - {1, 3, 0x0040}, - {0, 3, 0x0040}, - {0, 4, 0x0040}, - {0, 4, 0x0040}, - {0, 5, 0x0040}, - {0, 5, 0x0040}, - {0, 6, 0x0040}, - {0, 6, 0x0040}, }" - device domain 0 on device ref host_bridge on end # Host bridge device ref peg10 off end # PCIe Bridge for discrete graphics diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index e0f27ba..a137e35 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -124,8 +124,3 @@ superio_init(); hwm_init(); } - -const struct southbridge_usb_port mainboard_usb_ports[] = { -#define USB_CONFIG(enabled, current, ocpin) { enabled, current, ocpin } -#include "usb.h" -}; diff --git a/src/mainboard/intel/dcp847ske/usb.h b/src/mainboard/intel/dcp847ske/usb.h deleted file mode 100644 index 2469309..0000000 --- a/src/mainboard/intel/dcp847ske/usb.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef DCP847SKE_USB_H -#define DCP847SKE_USB_H - -USB_CONFIG(1, 1, 0), /* back, towards HDMI plugs */ -USB_CONFIG(1, 1, 0), /* back, towards power plug */ -USB_CONFIG(1, 1, 1), /* half-width miniPCIe */ -USB_CONFIG(1, 1, 1), /* full-width miniPCIe */ -USB_CONFIG(1, 1, 2), /* front-panel header */ -USB_CONFIG(1, 1, 2), /* front-panel header */ -USB_CONFIG(1, 1, 3), /* front connector */ -USB_CONFIG(0, 1, 3), /* not available */ -USB_CONFIG(0, 1, 4), /* not available */ -USB_CONFIG(0, 1, 4), /* not available */ -USB_CONFIG(0, 1, 5), /* not available */ -USB_CONFIG(0, 1, 5), /* not available */ -USB_CONFIG(0, 1, 6), /* not available */ -USB_CONFIG(0, 1, 6), /* not available */ - -#endif diff --git a/src/mainboard/intel/dq67sw/early_init.c b/src/mainboard/intel/dq67sw/early_init.c index 14317a6..f7515a5 100644 --- a/src/mainboard/intel/dq67sw/early_init.c +++ b/src/mainboard/intel/dq67sw/early_init.c @@ -1,29 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <southbridge/intel/bd82x6x/pch.h> #include <superio/winbond/w83667hg-a/w83667hg-a.h> #include <superio/winbond/common/winbond.h> #define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, - { 1, 1, 0 }, - { 1, 1, 1 }, - { 1, 1, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 1, 4 }, - { 1, 1, 4 }, - { 0, 0, 5 }, - { 0, 0, 5 }, - { 1, 0, 6 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 32bab2c..59e91b2 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -14,22 +14,6 @@ register "max_mem_clock_mhz" = "800" register "spd_addresses" = "{0x50, 0, 0x52, 0}" - register "usb_port_config" = "{ - { 1, 0, 0x0040 }, - { 1, 1, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 2, 0x0040 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 1, 6, 0x0040 }, - { 1, 5, 0x0040 }, }" - chip cpu/intel/model_206ax device cpu_cluster 0 on end diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c index 1974713..329f13d 100644 --- a/src/mainboard/intel/emeraldlake2/early_init.c +++ b/src/mainboard/intel/emeraldlake2/early_init.c @@ -47,21 +47,3 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { } - -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power USB oc pin */ - { 1, 0, 0 }, /* P0: Front port (OC0) */ - { 1, 0, 1 }, /* P1: Back port (OC1) */ - { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ - { 1, 0, -1 }, /* P3: MMC (no OC) */ - { 1, 0, 2 }, /* P4: Front port (OC2) */ - { 0, 0, -1 }, /* P5: Empty */ - { 0, 0, -1 }, /* P6: Empty */ - { 0, 0, -1 }, /* P7: Empty */ - { 1, 0, 4 }, /* P8: Back port (OC4) */ - { 1, 0, -1 }, /* P9: MINIPCIE3 (no OC) */ - { 1, 0, -1 }, /* P10: BLUETOOTH (no OC) */ - { 0, 0, -1 }, /* P11: Empty */ - { 1, 0, 6 }, /* P12: Back port (OC6) */ - { 1, 0, 5 }, /* P13: Back port (OC5) */ -}; diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index 0fc75e9..b5001fb 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -10,21 +10,6 @@ register "usb3.mode" = "3" register "usb3.preboot_support" = "1" register "usb3.xhci_streams" = "1" - register "usb_port_config" = "{ - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, }" chip cpu/intel/model_206ax device cpu_cluster 0 on end diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index e514f102..7a23765 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -54,24 +54,6 @@ { } -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power USB oc pin */ - { 1, 0, 0 }, /* P0: lower left USB 3.0 (OC0) */ - { 1, 0, 0 }, /* P1: upper left USB 3.0 (OC0) */ - { 1, 0, 0 }, /* P2: lower right USB 3.0 (OC0) */ - { 1, 0, 0 }, /* P3: upper right USB 3.0 (OC0) */ - { 1, 0, 0 }, /* P4: lower USB 2.0 (OC0) */ - { 1, 0, 0 }, /* P5: upper USB 2.0 (OC0) */ - { 1, 0, 0 }, /* P6: front panel USB 2.0 (OC0) */ - { 1, 0, 0 }, /* P7: front panel USB 2.0 (OC0) */ - { 1, 0, 4 }, /* P8: internal USB 2.0 (OC4) */ - { 1, 0, 4 }, /* P9: internal USB 2.0 (OC4) */ - { 1, 0, 4 }, /* P10: internal USB 2.0 (OC4) */ - { 1, 0, 4 }, /* P11: internal USB 2.0 (OC4) */ - { 1, 0, 4 }, /* P12: internal USB 2.0 (OC4) */ - { 1, 0, 4 }, /* P13: internal USB 2.0 (OC4) */ -}; - void mainboard_early_init(int s3resume) { /* Enable PEG10 (1x16) */ diff --git a/src/mainboard/lenovo/l520/Makefile.mk b/src/mainboard/lenovo/l520/Makefile.mk index e4b6fbf..7611194 100644 --- a/src/mainboard/lenovo/l520/Makefile.mk +++ b/src/mainboard/lenovo/l520/Makefile.mk @@ -4,5 +4,3 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -bootblock-y += early_init.c -romstage-y += early_init.c diff --git a/src/mainboard/lenovo/l520/early_init.c b/src/mainboard/lenovo/l520/early_init.c deleted file mode 100644 index ebcd639..0000000 --- a/src/mainboard/lenovo/l520/early_init.c +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/common/gpio.h> - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, -}; diff --git a/src/mainboard/lenovo/s230u/early_init.c b/src/mainboard/lenovo/s230u/early_init.c index 58e9593..f4396cb6 100644 --- a/src/mainboard/lenovo/s230u/early_init.c +++ b/src/mainboard/lenovo/s230u/early_init.c @@ -20,23 +20,6 @@ ec_mm_set_bit(0x3b, 4); } -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, - { 1, 0, 0 }, - { 1, 1, 1 }, - { 1, 0, 1 }, - { 1, 1, 2 }, - { 1, 0, 2 }, - { 0, 0, 3 }, - { 0, 1, 3 }, - { 1, 0, 4 }, - { 1, 1, 4 }, - { 1, 1, 5 }, - { 1, 1, 5 }, - { 1, 1, 6 }, - { 1, 1, 6 }, -}; - static const char *mainboard_spd_names[9] = { "ELPIDA 4GB", "SAMSUNG 4GB", diff --git a/src/mainboard/lenovo/t420/early_init.c b/src/mainboard/lenovo/t420/early_init.c index c90221e..79e3cf7 100644 --- a/src/mainboard/lenovo/t420/early_init.c +++ b/src/mainboard/lenovo/t420/early_init.c @@ -31,24 +31,6 @@ pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -// OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13 -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, /* P0: system port 4, OC0 */ - { 1, 1, 1 }, /* P1: system port 2 (EHCI debug), OC 1 */ - { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ - { 1, 0, -1 }, /* P3: WWAN, no OC */ - { 1, 0, -1 }, /* P4: smartcard, no OC */ - { 1, 1, -1 }, /* P5: ExpressCard, no OC */ - { 0, 0, -1 }, /* P6: empty */ - { 0, 0, -1 }, /* P7: empty */ - { 1, 1, 4 }, /* P8: system port 3, OC4*/ - { 1, 1, 5 }, /* P9: system port 1 (EHCI debug), OC 5 */ - { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ - { 1, 0, -1 }, /* P11: bluetooth, no OC. */ - { 1, 1, -1 }, /* P12: docking, no OC */ - { 1, 1, -1 }, /* P13: camera (LCD), no OC */ -}; - void mainboard_early_init(int s3resume) { hybrid_graphics_init(); diff --git a/src/mainboard/lenovo/t420s/early_init.c b/src/mainboard/lenovo/t420s/early_init.c index e5e95b2..79e3cf7 100644 --- a/src/mainboard/lenovo/t420s/early_init.c +++ b/src/mainboard/lenovo/t420s/early_init.c @@ -31,23 +31,6 @@ pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 0, 1, -1 }, /* P0: empty */ - { 1, 1, 1 }, /* P1: system port 2 (To system port) (EHCI debug), OC 1 */ - { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ - { 1, 0, -1 }, /* P3: WWAN, no OC */ - { 1, 1, -1 }, /* P4: smartcard, no OC */ - { 1, 1, -1 }, /* P5: ExpressCard, no OC */ - { 0, 0, -1 }, /* P6: empty */ - { 0, 0, -1 }, /* P7: empty */ - { 0, 1, -1 }, /* P8: empty (touch panel) */ - { 1, 0, 5 }, /* P9: system port 1 (To USBAO) (EHCI debug), OC 5 */ - { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ - { 1, 1, -1 }, /* P11: bluetooth, no OC. */ - { 1, 1, -1 }, /* P12: docking, no OC */ - { 1, 1, -1 }, /* P13: camera (LCD), no OC */ -}; - void mainboard_early_init(int s3resume) { hybrid_graphics_init(); diff --git a/src/mainboard/lenovo/t430/early_init.c b/src/mainboard/lenovo/t430/early_init.c index 5e397ab..86fcda8 100644 --- a/src/mainboard/lenovo/t430/early_init.c +++ b/src/mainboard/lenovo/t430/early_init.c @@ -33,24 +33,6 @@ pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -/* FIXME: used T530 values here */ -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, - { 1, 1, 1 }, - { 1, 2, 3 }, - { 1, 1, -1 }, - { 1, 1, 2 }, - { 1, 0, -1 }, - { 0, 0, -1 }, - { 1, 2, -1 }, - { 1, 0, -1 }, - { 1, 1, 5 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 3, -1 }, - { 1, 1, -1 }, -}; - void mainboard_early_init(int s3resume) { hybrid_graphics_init(); diff --git a/src/mainboard/lenovo/x220/Makefile.mk b/src/mainboard/lenovo/x220/Makefile.mk index b104bb5..7e59707 100644 --- a/src/mainboard/lenovo/x220/Makefile.mk +++ b/src/mainboard/lenovo/x220/Makefile.mk @@ -2,7 +2,6 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c -romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads bootblock-y += early_init.c diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 233f690..927d31a 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -19,22 +19,6 @@ register "ec_present" = "1" # I have an embedded controller register "max_mem_clock_mhz" = "666" # So DDR3 freq = 1333 - register "usb_port_config" = "{ - { 1, 0, 0x0040 }, - { 1, 1, 0x0080 }, - { 1, 3, 0x0080 }, - { 1, 3, 0x0080 }, - { 1, 0, 0x0080 }, - { 1, 0, 0x0080 }, - { 1, 2, 0x0040 }, - { 1, 2, 0x0040 }, - { 1, 6, 0x0080 }, - { 1, 5, 0x0080 }, - { 1, 6, 0x0080 }, - { 1, 6, 0x0080 }, - { 1, 7, 0x0080 }, - { 1, 6, 0x0080 },}" - device domain 0 on subsystemid 0x17aa 0x21db inherit diff --git a/src/mainboard/lenovo/x220/variants/x1/romstage.c b/src/mainboard/lenovo/x220/variants/x1/romstage.c deleted file mode 100644 index 593b7b2..0000000 --- a/src/mainboard/lenovo/x220/variants/x1/romstage.c +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <southbridge/intel/bd82x6x/pch.h> - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, - { 1, 1, 1 }, - { 1, 1, 3 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 1, 3 }, - { 0, 0, 3 }, - { 0, 0, 3 }, - { 1, 1, 4 }, - { 1, 1, 5 }, - { 1, 0, 7 }, - { 1, 1, 7 }, - { 1, 1, 7 }, - { 1, 0, 7 }, -}; diff --git a/src/mainboard/lenovo/x220/variants/x220/romstage.c b/src/mainboard/lenovo/x220/variants/x220/romstage.c deleted file mode 100644 index bd33cef..0000000 --- a/src/mainboard/lenovo/x220/variants/x220/romstage.c +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <southbridge/intel/bd82x6x/pch.h> - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 1, 1 }, - { 1, 1, 3 }, - { 1, 1, 3 }, - { 1, 1, -1 }, - { 1, 1, -1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 1, 6 }, - { 1, 1, 5 }, - { 1, 1, 6 }, - { 1, 1, 6 }, - { 1, 1, 7 }, - { 1, 1, 6 }, -}; diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index 4a89282..5c26670 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -26,22 +26,6 @@ register "ec_present" = "1" register "max_mem_clock_mhz" = "800" - register "usb_port_config" = "{ - { 1, 0, 0x0040 }, - { 1, 4, 0x0040 }, - { 1, 1, 0x0080 }, - { 1, 2, 0x0080 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 3, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 5, 0x0040 }, }" - chip cpu/intel/model_206ax device cpu_cluster 0 on end diff --git a/src/mainboard/roda/rv11/variants/rv11/early_init.c b/src/mainboard/roda/rv11/variants/rv11/early_init.c index 5de8f56..66e3e52 100644 --- a/src/mainboard/roda/rv11/variants/rv11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rv11/early_init.c @@ -8,21 +8,3 @@ /* TODO: Confirm if need to enable peg10 in devicetree */ pei_data->pcie_init = 1; } - -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* Enabled / Power / OC PIN */ - { 1, 0, 0 }, /* P00: 1st USB3 (OC #0) */ - { 1, 0, 4 }, /* P01: 2nd USB3 (OC #4) */ - { 1, 1, 1 }, /* P02: 1st Multibay USB3 (OC #1) */ - { 1, 1, 2 }, /* P03: 2nd Multibay USB3 (OC #2) */ - { 1, 0, 8 }, /* P04: MiniPCIe 1 USB2 (no OC) */ - { 1, 0, 8 }, /* P05: MiniPCIe 2 USB2 (no OC) */ - { 1, 0, 8 }, /* P06: MiniPCIe 3 USB2 (no OC) */ - { 1, 0, 8 }, /* P07: GPS USB2 (no OC) */ - { 1, 0, 8 }, /* P08: MiniPCIe 4 USB2 (no OC) */ - { 1, 0, 3 }, /* P09: Express Card USB2 (OC #3) */ - { 1, 0, 8 }, /* P10: SD card reader USB2 (no OC) */ - { 1, 0, 8 }, /* P11: Sensors Hub? USB2 (no OC) */ - { 1, 0, 8 }, /* P12: Touch Screen USB2 (no OC) */ - { 1, 0, 5 }, /* P13: reserved? USB2 (OC #5) */ -}; diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index 67773bb..e9f1a46 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -25,21 +25,6 @@ register "usb3.hs_port_switch_mask" = "0xf" register "usb3.preboot_support" = "1" register "usb3.xhci_streams" = "1" - register "usb_port_config" = "{ - { 1, 0, 0x0080 }, - { 1, 0, 0x0080 }, - { 1, 1, 0x0080 }, - { 1, 1, 0x0080 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0080 }, - { 1, 4, 0x0080 }, - { 1, 5, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0080 }, - { 1, 6, 0x0080 }, }" chip cpu/intel/model_206ax device cpu_cluster 0 on end diff --git a/src/mainboard/roda/rv11/variants/rw11/early_init.c b/src/mainboard/roda/rv11/variants/rw11/early_init.c index 451c4b7..b791cbc 100644 --- a/src/mainboard/roda/rv11/variants/rw11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rw11/early_init.c @@ -40,21 +40,3 @@ /* TODO: Confirm if need to enable peg10 in devicetree */ pei_data->pcie_init = 1; } - -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* Enabled / Power / OC PIN */ - { 1, 1, 0 }, /* P00: 1st (left) USB3 (OC #0) */ - { 1, 1, 0 }, /* P01: 2nd (left) USB3 (OC #0) */ - { 1, 1, 1 }, /* P02: 1st Multibay USB3 (OC #1) */ - { 1, 1, 1 }, /* P03: 2nd Multibay USB3 (OC #1) */ - { 1, 0, 8 }, /* P04: MiniPCIe 1 USB2 (no OC) */ - { 1, 0, 8 }, /* P05: MiniPCIe 2 USB2 (no OC) */ - { 1, 0, 8 }, /* P06: USB Hub x4 USB2 (no OC) */ - { 1, 0, 8 }, /* P07: MiniPCIe 4 USB2 (no OC) */ - { 1, 1, 8 }, /* P08: SD card reader USB2 (no OC) */ - { 1, 1, 4 }, /* P09: 3rd (right) USB2 (OC #4) */ - { 1, 0, 5 }, /* P10: 4th (right) USB2 (OC #5) */ - { 1, 0, 8 }, /* P11: 3rd Multibay USB2 (no OC) */ - { 1, 1, 8 }, /* P12: misc internal USB2 (no OC) */ - { 1, 1, 6 }, /* P13: misc internal USB2 (OC #6) */ -}; diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 5bc15e7..d9ee4b7 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -20,22 +20,6 @@ register "ec_present" = "1" register "max_mem_clock_mhz" = "666" - register "usb_port_config" = "{ - { 1, 0, 0x0080 }, - { 1, 1, 0x0080 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 },}" - device domain 0 on subsystemid 0x1ae0 0xc000 inherit device ref host_bridge on end # host bridge diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c index 5b355a2..b82d4d3 100644 --- a/src/mainboard/samsung/lumpy/early_init.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -108,24 +108,6 @@ memcpy(pei_data->ts_addresses, &tsaddr, sizeof(pei_data->ts_addresses)); } -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power USB oc pin */ - { 1, 1, 0 }, /* P0: Port 0 (OC0) */ - { 1, 1, 1 }, /* P1: Port 1 (OC1) */ - { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ - { 1, 0, -1 }, /* P3: MMC (no OC) */ - { 0, 0, -1 }, /* P4: Empty */ - { 0, 0, -1 }, /* P5: Empty */ - { 0, 0, -1 }, /* P6: Empty */ - { 0, 0, -1 }, /* P7: Empty */ - { 1, 0, -1 }, /* P8: MINIPCIE2 (no OC) */ - { 0, 0, -1 }, /* P9: Empty */ - { 0, 0, -1 }, /* P10: Empty */ - { 1, 0, -1 }, /* P11: Camera (no OC) */ - { 0, 0, -1 }, /* P12: Empty */ - { 0, 0, -1 }, /* P13: Empty */ -}; - void mb_get_spd_map(struct spd_info *spdi) { spdi->addresses[0] = 0x50; diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index f9f6ef9..721fd88 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -12,22 +12,6 @@ register "spd_addresses" = "{0x50, 0, 0x52, 0}" register "max_mem_clock_mhz" = "666" - register "usb_port_config" = "{ - { 1, 0, 0x0080 }, - { 1, 1, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 2, 0x0080 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 1, 6, 0x0040 }, - { 1, 5, 0x0040 }, }" - chip cpu/intel/model_206ax device cpu_cluster 0 on end diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index 681373c..1310c48 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -91,24 +91,6 @@ /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ } -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power USB oc pin */ - { 1, 1, 0 }, /* P0: Front port (OC0) */ - { 1, 0, 1 }, /* P1: Back port (OC1) */ - { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ - { 1, 0, -1 }, /* P3: MMC (no OC) */ - { 1, 1, 2 }, /* P4: Front port (OC2) */ - { 0, 0, -1 }, /* P5: Empty */ - { 0, 0, -1 }, /* P6: Empty */ - { 0, 0, -1 }, /* P7: Empty */ - { 1, 0, 4 }, /* P8: Back port (OC4) */ - { 1, 0, -1 }, /* P9: MINIPCIE3 (no OC) */ - { 1, 0, -1 }, /* P10: BLUETOOTH (no OC) */ - { 0, 0, -1 }, /* P11: Empty */ - { 1, 0, 6 }, /* P12: Back port (OC6) */ - { 1, 0, 5 }, /* P13: Back port (OC5) */ -}; - void bootblock_mainboard_early_init(void) { if (CONFIG(DRIVERS_UART_8250IO)) diff --git a/src/mainboard/sapphire/pureplatinumh61/early_init.c b/src/mainboard/sapphire/pureplatinumh61/early_init.c index 8749e49..b4bc111 100644 --- a/src/mainboard/sapphire/pureplatinumh61/early_init.c +++ b/src/mainboard/sapphire/pureplatinumh61/early_init.c @@ -8,20 +8,3 @@ { pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000); } - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index 82e58f6..35e4cf7 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -80,26 +80,6 @@ DDR_REFRESH_RATE_DOUBLE, } ddr_refresh_rate_config; - /* - * USB Port Configuration: - * [0] = enable - * [1] = overcurrent pin - * [2] = length - * - * Ports 0-7 can be mapped to OC0-OC3 - * Ports 8-13 can be mapped to OC4-OC7 - * - * Port Length - * MOBILE: - * < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude) - * < 0x140 = Setting 2 (back panel, 5-14in, highest tx amplitude) - * DESKTOP: - * < 0x080 = Setting 1 (front/back panel, <8in, lowest tx amplitude) - * < 0x130 = Setting 2 (back panel, 8-13in, higher tx amplitude) - * < 0x150 = Setting 3 (back panel, 13-15in, highest tx amplitude) - */ - u16 usb_port_config[16][3]; - struct { /* 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto */ u8 mode : 2; diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 17ee4b0..8ceadf2 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -62,7 +62,6 @@ }; void pch_enable(struct device *dev); -extern const struct southbridge_usb_port mainboard_usb_ports[14]; void early_usb_init(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/81882?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie1cd21077136998a6e90050c95263f2efed68a67 Gerrit-Change-Number: 81882 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Attention: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: nb/sandybridge,sb/bd82x6x: Configure USB from southbridge
by Keith Hui (Code Review) 13 Apr '24

13 Apr '24

Attention is currently required from: Angel Pons. Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81881?usp=email ) Change subject: nb/sandybridge,sb/bd82x6x: Configure USB from southbridge ...................................................................... nb/sandybridge,sb/bd82x6x: Configure USB from southbridge Transfer all USB responsibilities to southbridge/intel/bd82x6x, using one set of USB port configurations supplied by mainboards in the southbridge section of their devicetree. For MRC raminit, export southbridge_fill_pei_data() as a hook for southbridge code to implement. With new code via this hook, bd82x6x fills pei_data based on the one set of USB port config. For native raminit, early_usb_init() now goes directly to the devicetree for USB port config and no longer get passed an address to it. TEST=abuild passes for all affected boards. All USB ports still work on asus/p8x7x-series/v/p8z77-m. Change-Id: I38378c7ee0701abc434b030dd97873f2af63e6b0 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/northbridge/intel/sandybridge/pei_data.h M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/romstage.c M src/southbridge/intel/bd82x6x/early_usb.c M src/southbridge/intel/bd82x6x/early_usb_mrc.c M src/southbridge/intel/bd82x6x/pch.h 6 files changed, 40 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/81881/1 diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h index 0309cf3..db6347c 100644 --- a/src/northbridge/intel/sandybridge/pei_data.h +++ b/src/northbridge/intel/sandybridge/pei_data.h @@ -116,4 +116,5 @@ int ddr_refresh_rate_config; } __packed; +void southbridge_fill_pei_data(struct pei_data *pei_data); #endif diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 819bfcd..fc64178 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -291,7 +291,7 @@ } } -static void southbridge_fill_pei_data(struct pei_data *pei_data) +static void sb_fill_pei_data(struct pei_data *pei_data) { const struct device *dev = pcidev_on_root(0x19, 0); @@ -338,9 +338,6 @@ pei_data->nmode = cfg->nmode; pei_data->ddr_refresh_rate_config = cfg->ddr_refresh_rate_config; - memcpy(pei_data->usb_port_config, cfg->usb_port_config, - sizeof(pei_data->usb_port_config)); - pei_data->usb3.mode = cfg->usb3.mode; pei_data->usb3.hs_port_switch_mask = cfg->usb3.hs_port_switch_mask; pei_data->usb3.preboot_support = cfg->usb3.preboot_support; @@ -413,6 +410,8 @@ memcpy(&pei_data, &pd, sizeof(pd)); northbridge_fill_pei_data(&pei_data); + sb_fill_pei_data(&pei_data); + /* Have southbridge code fill in USB config data */ southbridge_fill_pei_data(&pei_data); devicetree_fill_pei_data(&pei_data); if (CONFIG(HAVE_SPD_IN_CBFS)) diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 56dc677..86569c1 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -58,7 +58,7 @@ /* When using MRC, USB is initialized by MRC */ if (CONFIG(USE_NATIVE_RAMINIT)) { - early_usb_init(mainboard_usb_ports); + early_usb_init(); } /* Perform some early chipset init needed before RAM initialization can work */ diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index 35bfeca..487504b 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -8,8 +8,9 @@ #include <southbridge/intel/common/pmbase.h> #include "pch.h" +#include "chip.h" -void early_usb_init(const struct southbridge_usb_port *portmap) +void early_usb_init(void) { u32 reg32; const u32 rcba_dump[8] = { @@ -19,6 +20,9 @@ const u32 currents[] = { USBIR_TXRX_GAIN_MOBILE_LOW, USBIR_TXRX_GAIN_DEFAULT, USBIR_TXRX_GAIN_HIGH, 0x20000f51, 0x2000094a, 0x2000035f, USBIR_TXRX_GAIN_DESKTOP_LOW, 0x20000357, 0x20000353 }; + const struct device *dev = pcidev_on_root(0x1d, 0); + const struct southbridge_intel_bd82x6x_config *config = dev->chip_info; + const struct southbridge_usb_port *portmap = config->usb_port_config; int i; /* Unlock registers. */ diff --git a/src/southbridge/intel/bd82x6x/early_usb_mrc.c b/src/southbridge/intel/bd82x6x/early_usb_mrc.c index f60cc0b..92ef93a 100644 --- a/src/southbridge/intel/bd82x6x/early_usb_mrc.c +++ b/src/southbridge/intel/bd82x6x/early_usb_mrc.c @@ -3,6 +3,8 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include "pch.h" +#include "chip.h" +#include <northbridge/intel/sandybridge/pei_data.h> #define PCH_EHCI1_TEMP_BAR0 0xe8000000 #define PCH_EHCI2_TEMP_BAR0 0xe8000400 @@ -29,3 +31,30 @@ PCH_EHCI2_TEMP_BAR0); pci_or_config16(usb1, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } + +/* + * Translate coreboot-formatted USB config data in devicetree + * into a format reference code expects: + * + * [MRC index] = .native_field // what for + * [0] = .enabled // enable + * [1] = .oc_pin // overcurrent pin + * [2] = .current // length + * + * For length, constants are defined and they must be used, as their values differ based on + * whether native or reference code is being used. + */ +void southbridge_fill_pei_data(struct pei_data *pei_data) +{ + const struct device *dev = pcidev_on_root(0x1d, 0); + const struct southbridge_intel_bd82x6x_config *config = dev->chip_info; + + for (unsigned int port = 0; port < ARRAY_SIZE(config->usb_port_config); port++) { + int ocp = config->usb_port_config[port].oc_pin; + if (ocp == -1) + ocp = (port < 8) ? 0 : 4; + pei_data->usb_port_config[port][0] = config->usb_port_config[port].enabled; + pei_data->usb_port_config[port][1] = ocp; + pei_data->usb_port_config[port][2] = config->usb_port_config[port].current; + } +} diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 040b477..17ee4b0 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -64,7 +64,7 @@ void pch_enable(struct device *dev); extern const struct southbridge_usb_port mainboard_usb_ports[14]; -void early_usb_init(const struct southbridge_usb_port *portmap); +void early_usb_init(void); /* PCI Configuration Space (D30:F0): PCI2PCI */ #define PSTS 0x06 -- To view, visit https://review.coreboot.org/c/coreboot/+/81881?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I38378c7ee0701abc434b030dd97873f2af63e6b0 Gerrit-Change-Number: 81881 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: SNB+MRC boards: Add consolidated USB port config
by Keith Hui (Code Review) 13 Apr '24

13 Apr '24

Attention is currently required from: Alexander Couzens. Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81880?usp=email ) Change subject: SNB+MRC boards: Add consolidated USB port config ...................................................................... SNB+MRC boards: Add consolidated USB port config For each sandybridge boards with option to use MRC or native platform init code, add a copy of the board's USB port config, consolidated between both code paths, into the southbridge devicetree, using macros created specifically to trick compiler into producing the correct values based on CONFIG(USE_NATIVE_RAMINIT) without need for runtime calculations. These get hooked up in a separate patch. Change-Id: I53efca3d29b3c5d4d5b7e3d6dc3e6ce6c34201e6 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb M src/mainboard/google/butterfly/devicetree.cb M src/mainboard/google/link/devicetree.cb M src/mainboard/google/parrot/devicetree.cb M src/mainboard/google/stout/devicetree.cb M src/mainboard/intel/dcp847ske/devicetree.cb M src/mainboard/intel/emeraldlake2/devicetree.cb M src/mainboard/lenovo/x220/variants/x220/overridetree.cb M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/samsung/lumpy/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb 13 files changed, 200 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/81880/1 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb index 5d688fd..c15767b 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb @@ -10,6 +10,21 @@ subsystemid 0x1043 0x84ca inherit chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH register "gen1_dec" = "0x000c0291" + register "usb_port_config" = "{ + {1, USB_GAIN_2, 0}, + {1, USB_GAIN_2, 0}, + {1, USB_GAIN_2, 1}, + {1, USB_GAIN_2, 1}, + {1, USB_GAIN_2, 2}, + {1, USB_GAIN_2, 2}, + {1, USB_GAIN_2, 3}, + {1, USB_GAIN_2, 3}, + {1, USB_GAIN_2, 4}, + {1, USB_GAIN_2, 4}, + {1, USB_GAIN_2, 6}, + {1, USB_GAIN_2, 5}, + {1, USB_GAIN_2, 5}, + {1, USB_GAIN_2, 6}}" device ref pcie_rp1 on end # PCIe x4 slot device ref pcie_rp2 off end diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb index da34af3..1a011c3 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb @@ -12,6 +12,21 @@ register "gen1_dec" = "0x000c0291" register "gen4_dec" = "0x0000ff29" register "pcie_port_coalesce" = "true" + register "usb_port_config" = "{ + {1, USB_GAIN_2, 0}, + {1, USB_GAIN_2, 0}, + {1, USB_GAIN_2, 1}, + {1, USB_GAIN_2, 1}, + {1, USB_GAIN_2, 2}, + {1, USB_GAIN_2, 2}, + {1, USB_GAIN_2, 3}, + {1, USB_GAIN_2, 3}, + {1, USB_GAIN_2, 4}, + {1, USB_GAIN_2, 4}, + {1, USB_GAIN_2, 6}, + {1, USB_GAIN_2, 5}, + {0, USB_GAIN_2, 5}, + {0, USB_GAIN_2, 6}}" device ref pcie_rp1 on end # PCIEX_16_3 device ref pcie_rp2 on end # RTL8111F diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index f3960ca..a001f73 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -69,6 +69,22 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" + register "usb_port_config" = "{ + { 1, USB_GAIN_L, -1 }, /* P0: Right USB 3.0 #1 (no OC) */ + { 1, USB_GAIN_L, -1 }, /* P1: Right USB 3.0 #2 (no OC) */ + { 1, USB_GAIN_L, -1 }, /* P2: Camera (no OC) */ + { 0, 0, -1 }, /* P3-P8: Empty */ + { 0, 0, -1 }, + { 0, 0, -1 }, + { 0, 0, -1 }, + { 0, 0, -1 }, + { 0, 0, -1 }, + { 1, USB_GAIN_H, -1 }, /* P9: Left USB 1 (no OC) */ + { 1, USB_GAIN_L, -1 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ + { 0, 0, -1 }, /* P11-P13: Empty */ + { 0, 0, -1 }, + { 0, 0, -1 }}" + device ref xhci on end # USB 3.0 Controller device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 88983dc..39b8452 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -65,6 +65,20 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" + register "usb_port_config" = "{ + {0, 0, -1}, /* P0: Empty */ + {1, USB_GAIN_L, 0}, /* P1: Left USB 1 (OC0) */ + {1, USB_GAIN_L, 1}, /* P2: Left USB 2 (OC1) */ + {1, USB_GAIN_L, -1}, /* P3: SDCARD (no OC) */ + {0, 0, -1}, /* P4: Empty */ + {1, USB_GAIN_L, -1}, /* P5: WWAN (no OC) */ + {0, 0, -1}, {0, 0, -1}, /* P6,P7: Empty */ + {1, USB_GAIN_L, -1}, /* P8: Camera (no OC) */ + {1, USB_GAIN_L, -1}, /* P9: Bluetooth (no OC) */ + {0, 0, -1}, + {0, 0, -1}, {0, 0, -1}, {0, 0, -1}, /* P10-P13: Empty */ + }" + device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 device ref me_ide_r off end # Management Engine IDE-R diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index 49b40b9..da7c388 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -56,6 +56,21 @@ register "sata_port_map" = "0x1" + register "usb_port_config" = "{ + {0, 0, -1}, /* P0: Empty */ + {1, USB_GAIN_L, 0}, /* P1: Left USB 1 (OC0) */ + {1, USB_GAIN_L, 1}, /* P2: Left USB 2 (OC1) */ + {1, USB_GAIN_L, 1}, /* P3: Left USB 3 (OC1) */ + {0, 0, -1}, /* P4-P7: Empty */ + {0, 0, -1}, + {0, 0, -1}, + {0, 0, -1}, + /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ + {1, USB_GAIN_L, -1}, /* P8: MiniPCIe (WLAN) (no OC) */ + {0, 0, -1}, /* P9: Empty */ + {1, USB_GAIN_L, -1}, /* P10: Camera (no OC) */ + {0, 0, -1}, {0, 0, -1}, {0, 0, -1}}" + # EC range is 0xFD60 (EC_IO) and 0x68/0x6C register "gen1_dec" = "0x0004fd61" register "gen2_dec" = "0x00040069" diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 8fd19fc..0c029fa 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -79,6 +79,19 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" + register "usb_port_config" = "{ + {1, USB_GAIN_L, 0}, /* P0: USB 3.0 1 (OC0) */ + {1, USB_GAIN_L, 0}, /* P1: USB 3.0 2 (OC0) */ + {0, 0, 0}, /* P2: Empty */ + {1, USB_GAIN_L, -1}, /* P3: Camera (no OC) */ + {1, USB_GAIN_L, -1}, /* P4: WLAN (no OC) */ + {1, USB_GAIN_L, -1}, /* P5: WWAN (no OC) */ + {0, 0, 0}, {0, 0, 0}, {0, 0, 0}, /* P6-P8: Empty */ + {1, USB_GAIN_L, 4}, /* P9: USB 2.0 (AUO4) (OC4) */ + {0, 0, 0}, {0, 0, 0}, {0, 0, 0}, /* P10-P12: Empty */ + {1, USB_GAIN_L, -1} /* P13: Bluetooth (no OC) */ + }" + device ref xhci on end # USB 3.0 Controller device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb index f4e948f..46624fb 100644 --- a/src/mainboard/intel/dcp847ske/devicetree.cb +++ b/src/mainboard/intel/dcp847ske/devicetree.cb @@ -43,6 +43,22 @@ register "gen1_dec" = "0x00fc0a01" # SuperIO @0xa00-0xaff + register "usb_port_config" = "{ + {1, USB_GAIN_1, 0}, /* back, towards HDMI plugs */ + {1, USB_GAIN_1, 0}, /* back, towards power plug */ + {1, USB_GAIN_1, 1}, /* half-width miniPCIe */ + {1, USB_GAIN_1, 1}, /* full-width miniPCIe */ + {1, USB_GAIN_1, 2}, /* front-panel header */ + {1, USB_GAIN_1, 2}, /* front-panel header */ + {1, USB_GAIN_1, 3}, /* front connector */ + {0, USB_GAIN_1, 3}, /* not available * 7 */ + {0, USB_GAIN_1, 4}, + {0, USB_GAIN_1, 4}, + {0, USB_GAIN_1, 5}, + {0, USB_GAIN_1, 5}, + {0, USB_GAIN_1, 6}, + {0, USB_GAIN_1, 6}}" + device ref xhci off end # USB xHCI device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index e75505e..32bab2c 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -58,6 +58,22 @@ register "gen2_dec" = "0x000c0181" # SuperIO range is 0x700-0x73f register "gen3_dec" = "0x003c0701" + register "usb_port_config" = "{ + { 1, USB_GAIN_L, 0 }, /* P0: Front port (OC0) */ + { 1, USB_GAIN_L, 1 }, /* P1: Back port (OC1) */ + { 1, USB_GAIN_L, -1 }, /* P2: MINIPCIE1 (no OC) */ + { 1, USB_GAIN_L, -1 }, /* P3: MMC (no OC) */ + { 1, USB_GAIN_L, 2 }, /* P4: Front port (OC2) */ + { 0, 0, -1 }, /* P5: Empty */ + { 0, 0, -1 }, /* P6: Empty */ + { 0, 0, -1 }, /* P7: Empty */ + { 1, USB_GAIN_L, 4 }, /* P8: Back port (OC4) */ + { 1, USB_GAIN_L, -1 }, /* P9: MINIPCIE3 (no OC) */ + { 1, USB_GAIN_L, -1 }, /* P10: BLUETOOTH (no OC) */ + { 0, 0, -1 }, /* P11: Empty */ + { 1, USB_GAIN_L, 6 }, /* P12: Back port (OC6) */ + { 1, USB_GAIN_L, 5 }, /* P13: Back port (OC5) */ + }" device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 diff --git a/src/mainboard/lenovo/x220/variants/x220/overridetree.cb b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb index b9caa25..1fd4937 100644 --- a/src/mainboard/lenovo/x220/variants/x220/overridetree.cb +++ b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb @@ -1,6 +1,22 @@ chip northbridge/intel/sandybridge device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "usb_port_config" = "{ + {1, USB_GAIN_L, 0 }, + {1, USB_GAIN_H, 1 }, + {1, USB_GAIN_H, 3 }, + {1, USB_GAIN_H, 3 }, + {1, USB_GAIN_H, -1}, + {1, USB_GAIN_H, -1}, + {1, USB_GAIN_L, 2 }, + {1, USB_GAIN_L, 2 }, + {1, USB_GAIN_H, 6 }, + {1, USB_GAIN_H, 5 }, + {1, USB_GAIN_H, 6 }, + {1, USB_GAIN_H, 6 }, + {1, USB_GAIN_H, 7 }, + {1, USB_GAIN_H, 6 }}" + device ref lpc on chip ec/lenovo/h8 device pnp ff.2 on end # dummy diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index 9da9cb8..4a89282 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -69,10 +69,25 @@ register "pcie_port_coalesce" = "false" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" - register "xhci_overcurrent_mapping" = "0x00080401" register "xhci_switchable_ports" = "0x0f" register "superspeed_capable_ports" = "0x0f" + register "usb_port_config" = "{ + {1, USB_GAIN_L, 0}, /* P00: 1st USB3 (OC #0) */ + {1, USB_GAIN_L, 4}, /* P01: 2nd USB3 (OC #4) */ + {1, USB_GAIN_H, 1}, /* P02: 1st Multibay USB3 (OC #1) */ + {1, USB_GAIN_H, 2}, /* P03: 2nd Multibay USB3 (OC #2) */ + {1, USB_GAIN_L, 8}, /* P04: MiniPCIe 1 USB2 (no OC) */ + {1, USB_GAIN_L, 8}, /* P05: MiniPCIe 2 USB2 (no OC) */ + {1, USB_GAIN_L, 8}, /* P06: MiniPCIe 3 USB2 (no OC) */ + {1, USB_GAIN_L, 8}, /* P07: GPS USB2 (no OC) */ + {1, USB_GAIN_L, 8}, /* P08: MiniPCIe 4 USB2 (no OC) */ + {1, USB_GAIN_L, 3}, /* P09: Express Card USB2 (OC #3) */ + {1, USB_GAIN_L, 8}, /* P10: SD card reader USB2 (no OC) */ + {1, USB_GAIN_L, 8}, /* P11: Sensors Hub? USB2 (no OC) */ + {1, USB_GAIN_L, 8}, /* P12: Touch Screen USB2 (no OC) */ + {1, USB_GAIN_L, 5} /* P13: reserved? USB2 (OC #5) */ + }" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index 9dae3ff..67773bb 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -73,10 +73,25 @@ register "pcie_port_coalesce" = "false" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 1, 1 }" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0f" register "superspeed_capable_ports" = "0x0f" + register "usb_port_config" = "{ + {1, USB_GAIN_H, 0}, /* P00: 1st (left) USB3 (OC #0) */ + {1, USB_GAIN_H, 0}, /* P01: 2nd (left) USB3 (OC #0) */ + {1, USB_GAIN_H, 1}, /* P02: 1st Multibay USB3 (OC #1) */ + {1, USB_GAIN_H, 1}, /* P03: 2nd Multibay USB3 (OC #1) */ + {1, USB_GAIN_L, 8}, /* P04: MiniPCIe 1 USB2 (no OC) */ + {1, USB_GAIN_L, 8}, /* P05: MiniPCIe 2 USB2 (no OC) */ + {1, USB_GAIN_L, 8}, /* P06: USB Hub x4 USB2 (no OC) */ + {1, USB_GAIN_L, 8}, /* P07: MiniPCIe 4 USB2 (no OC) */ + {1, USB_GAIN_H, 8}, /* P08: SD card reader USB2 (no OC) */ + {1, USB_GAIN_H, 4}, /* P09: 3rd (right) USB2 (OC #4) */ + {1, USB_GAIN_L, 5}, /* P10: 4th (right) USB2 (OC #5) */ + {1, USB_GAIN_L, 8}, /* P11: 3rd Multibay USB2 (no OC) */ + {1, USB_GAIN_H, 8}, /* P12: misc internal USB2 (no OC) */ + {1, USB_GAIN_H, 6} /* P13: misc internal USB2 (OC #6) */ + }" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index a8efd67..5bc15e7 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -56,6 +56,21 @@ register "gen1_dec" = "0x003c0a01" register "gen2_dec" = "0x003c0b01" register "gen3_dec" = "0x00fc1601" + register "usb_port_config" = "{ + {1, USB_GAIN_H, 0}, /* P0: Port 0 (OC0) */ + {1, USB_GAIN_H, 1}, /* P1: Port 1 (OC1) */ + {1, USB_GAIN_L, -1}, /* P2: MINIPCIE1 (no OC) */ + {1, USB_GAIN_L, -1}, /* P3: MMC (no OC) */ + {0, 0, -1}, /* P4-P7, P9-P10, P12-P13: Empty */ + {0, 0, -1}, + {0, 0, -1}, + {0, 0, -1}, + {1, USB_GAIN_L, -1}, /* P8: MINIPCIE2 (no OC) */ + {0, 0, -1}, + {0, 0, -1}, + {1, USB_GAIN_L, -1}, /* P11: Camera (no OC) */ + {0, 0, -1}, + {0, 0, -1}}" device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index ae3aab5..f9f6ef9 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -54,6 +54,23 @@ # SuperIO range is 0x700-0x73f register "gen2_dec" = "0x003c0701" + register "usb_port_config" = "{ + {1, USB_GAIN_H, 0}, /* P0: Front port */ + {1, USB_GAIN_L, 1}, /* P1: Back port */ + {1, USB_GAIN_L, -1}, /* P2: MINIPCIE1 */ + {1, USB_GAIN_L, -1}, /* P3: MMC */ + {1, USB_GAIN_H, 2}, /* P4: Front port */ + {0, 0, 0}, /* P5: Empty */ + {0, 0, 0}, /* P6: Empty */ + {0, 0, 0}, /* P7: Empty */ + {1, 0, 4}, /* P8: Back port */ + {1, USB_GAIN_L, -1}, /* P9: MINIPCIE3 */ + {1, USB_GAIN_L, -1}, /* P10: BLUETOOTH */ + {0, 0, -1}, /* P11: Empty */ + {1, USB_GAIN_L, 6}, /* P12: Back port */ + {1, USB_GAIN_L, 5} /* P13: Back port */ + }" + device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 device ref me_ide_r off end # Management Engine IDE-R -- To view, visit https://review.coreboot.org/c/coreboot/+/81880?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I53efca3d29b3c5d4d5b7e3d6dc3e6ce6c34201e6 Gerrit-Change-Number: 81880 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[main]: mb/*: Copy bd82x6x boards' USB port config into devicetree
by Keith Hui (Code Review) 13 Apr '24

13 Apr '24

Attention is currently required from: Alexander Couzens, Angel Pons, Evgeny Zinoviev, Kevin Keijzer. Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81879?usp=email ) Change subject: mb/*: Copy bd82x6x boards' USB port config into devicetree ...................................................................... mb/*: Copy bd82x6x boards' USB port config into devicetree For mainboards using southbridge/intel/bd82x6x, copy the contents of mainboard_usb_ports array into southbridge devicetree. In-line comments are maintained, otherwise the contents are reformatted into 3-4 lines with extra spaces removed. Boards also capable of using MRC raminit are done in a separate patch. Change-Id: Ia8a967eb3466106f3a34e024260e13d02f449a25 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/apple/macbookair4_2/devicetree.cb M src/mainboard/asrock/b75m-itx/devicetree.cb M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/asrock/h77pro4-m/devicetree.cb M src/mainboard/asus/h61-series/devicetree.cb M src/mainboard/asus/maximus_iv_gene-z/devicetree.cb M src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb M src/mainboard/biostar/th61-itx/devicetree.cb M src/mainboard/compulab/intense_pc/devicetree.cb M src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb M src/mainboard/gigabyte/ga-h61m-series/devicetree.cb M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb M src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb M src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb M src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb M src/mainboard/intel/dq67sw/devicetree.cb M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb M src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb M src/mainboard/lenovo/t530/variants/t530/overridetree.cb M src/mainboard/lenovo/t530/variants/w530/overridetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x220/variants/x1/overridetree.cb M src/mainboard/lenovo/x230/variants/x230/overridetree.cb M src/mainboard/lenovo/x230/variants/x230s/overridetree.cb M src/mainboard/msi/ms7707/devicetree.cb M src/mainboard/sapphire/pureplatinumh61/devicetree.cb M src/mainboard/supermicro/x9sae/devicetree.cb M src/mainboard/supermicro/x9scl/devicetree.cb 49 files changed, 467 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/81879/1 diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index c408d5a..0ce7787 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -26,6 +26,14 @@ register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x1" + register "usb_port_config" = "{ + {1, 0, -1}, /* USB HUB 1 */ + {0, 0, -1}, {0, 0, -1}, {0, 0, -1}, /* Unused * 7 */ + {0, 0, -1}, {0, 0, -1}, {0, 0, -1}, {0, 0, -1}, + {1, 0, -1}, /* USB HUB 2 */ + {1, 0, -1}, /* Camera */ + {0, 0, -1}, /* Unused * 4 */ + {0, 0, -1}, {0, 0, -1}, {0, 0, -1}}" device ref mei1 on # Management Engine Interface 1 subsystemid 0x8086 0x7270 end diff --git a/src/mainboard/asrock/b75m-itx/devicetree.cb b/src/mainboard/asrock/b75m-itx/devicetree.cb index 59645f0..5011f69 100644 --- a/src/mainboard/asrock/b75m-itx/devicetree.cb +++ b/src/mainboard/asrock/b75m-itx/devicetree.cb @@ -27,6 +27,11 @@ register "xhci_switchable_ports" = "0x0000000f" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" + register "usb_port_config" = "{ + {1, 0, 0}, {1, 0, 0}, {1, 1, 1}, {1, 1, 1}, + {1, 1, 2}, {1, 1, 2}, {1, 0, 3}, {1, 0, 3}, + {1, 0, 4}, {1, 0, 4}, {1, 0, 6}, + {1, 1, 5}, {1, 1, 5}, {1, 0, 6}}" device ref xhci on subsystemid 0x1849 0x1e31 diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index e2c898d..1910fad 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -39,6 +39,11 @@ register "xhci_switchable_ports" = "0x0000000f" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" + register "usb_port_config" = "{ + {1, 0, 0}, {1, 0, 0}, {1, 1, 1}, {1, 1, 1}, + {1, 1, 2}, {1, 1, 2}, {1, 0, 3}, {1, 0, 3}, + {1, 0, 4}, {1, 0, 4}, {1, 0, 6}, + {1, 1, 5}, {1, 1, 5}, {1, 0, 6}}" device ref xhci on # USB 3.0 Controller subsystemid 0x1849 0x1e31 diff --git a/src/mainboard/asrock/h77pro4-m/devicetree.cb b/src/mainboard/asrock/h77pro4-m/devicetree.cb index 2624c38..c853251 100644 --- a/src/mainboard/asrock/h77pro4-m/devicetree.cb +++ b/src/mainboard/asrock/h77pro4-m/devicetree.cb @@ -21,6 +21,11 @@ register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + {1, 0, 0}, {1, 0, 0}, {1, 1, 1}, {1, 1, 1}, + {1, 1, 2}, {1, 1, 2}, {1, 0, 3}, {1, 0, 3}, + {1, 0, 4}, {1, 0, 4}, {1, 0, 6}, + {1, 1, 5}, {1, 1, 5}, {1, 0, 6}}" device ref xhci on # USB 3.0 Controller subsystemid 0x1849 0x1e31 end diff --git a/src/mainboard/asus/h61-series/devicetree.cb b/src/mainboard/asus/h61-series/devicetree.cb index 7f37acc..97e990c 100644 --- a/src/mainboard/asus/h61-series/devicetree.cb +++ b/src/mainboard/asus/h61-series/devicetree.cb @@ -11,6 +11,11 @@ register "sata_port_map" = "0x33" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" + register "usb_port_config" = "{ + {1, 0, 0}, {1, 0, 0}, {1, 0, 1}, {1, 0, 1}, + {1, 0, 2}, {1, 0, 2}, {1, 0, 3}, {1, 0, 3}, + {1, 0, 4}, {1, 0, 4}, {1, 0, 5}, + {1, 0, 5}, {1, 0, 6}, {1, 0, 6}}" device ref mei1 on end device ref mei2 off end diff --git a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb index 2642fbd..5da3fdf 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb +++ b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb @@ -15,6 +15,12 @@ register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" + register "usb_port_config" = "{ + {1, 0, 0}, {1, 0, 0}, {1, 0, 1}, {1, 0, 1}, + {1, 0, 2}, {1, 0, 2}, {1, 0, 3}, {1, 0, 3}, + {1, 0, 4}, {1, 0, 4}, {1, 0, 5}, + {1, 0, 5}, {1, 0, 6}, {1, 0, 6}}" + device ref mei1 on end device ref mei2 off end device ref me_ide_r off end diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb index 4b7bb1c..27b1478 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb @@ -7,6 +7,11 @@ subsystemid 0x1043 0x84ca inherit chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" + register "usb_port_config" = "{ + {1, 0, 0}, {1, 0, 0}, {1, 0, 1}, {1, 0, 1}, + {1, 0, 2}, {1, 0, 2}, {1, 0, 3}, {1, 0, 3}, + {1, 0, 4}, {1, 0, 4}, {1, 0, 6}, + {1, 0, 5}, {1, 0, 5}, {1, 0, 6}}" device ref pcie_rp1 on end # PCIEX16_4 (electrical x4) device ref pcie_rp2 off end device ref pcie_rp3 off end diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb index dbf1f35..454d2f3 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb @@ -4,6 +4,11 @@ device domain 0 on subsystemid 0x1043 0x84ca inherit chip southbridge/intel/bd82x6x + register "usb_port_config" = "{ + {1, 0, 0}, {1, 0, 0}, {1, 0, 1}, {1, 0, 1}, + {1, 0, 2}, {1, 0, 2}, {1, 0, 3}, {1, 0, 3}, + {1, 0, 4}, {1, 0, 4}, {1, 0, 6}, + {1, 0, 5}, {1, 0, 5}, {1, 0, 6}}" register "gen1_dec" = "0x000c0291" device ref pcie_rp1 on end # PCIEX16_2 (electrical x4) device ref pcie_rp2 off end diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb index 043be06..8dad852 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb @@ -5,6 +5,11 @@ subsystemid 0x1043 0x84ca inherit device ref peg11 on end # PCIEX_16_2 chip southbridge/intel/bd82x6x + register "usb_port_config" = "{ + {1, 2, 0}, {1, 2, 0}, {1, 2, 1}, {1, 0, 1}, + {1, 0, 2}, {1, 2, 2}, {1, 2, 3}, {1, 2, 3}, + {1, 2, 4}, {1, 0, 4}, {1, 2, 6}, + {1, 2, 5}, {1, 2, 5}, {1, 2, 6}}" register "gen1_dec" = "0x000c0291" device ref gbe on end diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb index 0ae41b3..056f592 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb @@ -4,6 +4,12 @@ device domain 0 on subsystemid 0x1043 0x84ca inherit chip southbridge/intel/bd82x6x + register "usb_port_config" = "{ + {1, 0, 0}, {1, 0, 0}, {1, 0, 1}, {1, 0, 1}, + {1, 0, 2}, {1, 0, 2}, {1, 0, 3}, {1, 0, 3}, + {1, 0, 4}, {1, 0, 4}, {1, 0, 6}, + {1, 0, 5}, {1, 0, 5}, {1, 0, 6}}" + register "gen1_dec" = "0x000c0291" device ref pcie_rp1 on end # PCIEX16_2 (electrical x4) diff --git a/src/mainboard/biostar/th61-itx/devicetree.cb b/src/mainboard/biostar/th61-itx/devicetree.cb index af9f9b5..e074fa6 100644 --- a/src/mainboard/biostar/th61-itx/devicetree.cb +++ b/src/mainboard/biostar/th61-itx/devicetree.cb @@ -15,6 +15,11 @@ register "sata_port_map" = "0x33" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" + register "usb_port_config" = "{ + {1, 0, 0}, {1, 0, 0}, {1, 0, 1}, {1, 0, 1}, + {1, 0, 2}, {1, 0, 2}, {1, 0, 3}, {1, 0, 3}, + {1, 0, 4}, {1, 0, 4}, {1, 0, 6}, + {1, 0, 5}, {1, 0, 5}, {1, 0, 6}}" device ref mei1 on end # MEI #1 device ref ehci2 on end # EHCI #2 diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb index d09c9e0..2740d41 100644 --- a/src/mainboard/compulab/intense_pc/devicetree.cb +++ b/src/mainboard/compulab/intense_pc/devicetree.cb @@ -48,6 +48,11 @@ register "xhci_switchable_ports" = "0x0000000f" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" + register "usb_port_config" = "{ + {1, 1, 0}, {1, 1, 0}, {1, 1, 1}, {1, 1, 1}, + {1, 0, 2}, {1, 0, 2}, {1, 0, 3}, {1, 0, 3}, + {1, 1, 4}, {1, 1, 4}, {1, 0, 5}, + {1, 0, 5}, {1, 0, 6}, {1, 0, 6}}" device ref xhci on end # USB 3.0 Controller device ref mei1 off end # Management Engine Interface 1 diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb index 28c8d05..d498967 100644 --- a/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb +++ b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb @@ -30,6 +30,11 @@ register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x08040201" register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + {1, 6, 0}, {1, 6, 0}, {1, 1, 1}, {1, 1, 1}, + {1, 1, 2}, {1, 1, 2}, {1, 6, 3}, {1, 6, 3}, + {1, 6, 4}, {1, 6, 4}, {1, 6, 5}, + {1, 1, 5}, {1, 1, 6}, {1, 6, 6}}" device ref xhci on end device ref mei1 off end device ref mei2 off end diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index 3b95843..cbf29d0 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -20,7 +20,11 @@ register "xhci_switchable_ports" = "0xf" register "superspeed_capable_ports" = "0xf" - + register "usb_port_config" = "{ + {1, 5, 0}, {1, 5, 0}, {1, 5, 1}, {1, 5, 1}, + {1, 5, 2}, {1, 5, 2}, {1, 5, 3}, {1, 5, 3}, + {1, 5, 4}, {1, 5, 4}, {1, 5, 6}, + {1, 5, 5}, {1, 5, 5}, {1, 5, 6}}" device ref xhci on # USB 3.0 Controller subsystemid 0x1458 0x5007 diff --git a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb index 8a29171..76d9568 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb @@ -16,6 +16,12 @@ register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" + register "usb_port_config" = "{ + {1, 0, 0}, {1, 0, 0}, {1, 0, 1}, {1, 0, 1}, + {1, 0, 2}, {1, 0, 2}, {1, 0, 3}, {1, 0, 3}, + {1, 0, 4}, {1, 0, 4}, {1, 0, 6}, + {1, 0, 5}, {1, 0, 5}, {1, 0, 6}}" + device ref mei1 on end # MEI #1 device ref ehci2 on end # USB2 EHCI #2 device ref hda on end # HD Audio diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index 993721b..26eeb0b 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -26,6 +26,12 @@ register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x0" + register "usb_port_config" = "{ + {1, 0, -1}, {1, 0, -1}, {1, 0, -1}, {1, 0, -1}, + {1, 0, -1}, {1, 0, -1}, {1, 0, -1}, {1, 0, -1}, + {1, 0, -1}, {1, 0, -1}, {1, 0, -1}, + {1, 0, -1}, {1, 0, -1}, {1, 0, -1}}" + device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 device ref me_ide_r off end # Management Engine IDE-R diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb index 7a62df1..1972b44 100644 --- a/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb +++ b/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb @@ -19,6 +19,11 @@ register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + {1, 0, 0}, {1, 0, 0}, {1, 0, 1}, {1, 0, 1}, + {1, 0, 2}, {1, 0, 2}, {1, 0, 3}, {1, 0, 3}, + {1, 0, 4}, {1, 0, 4}, {1, 0, 6}, + {1, 0, 5}, {1, 0, 5}, {1, 0, 6}}" device ref xhci on # USB 3.0 Controller subsystemid 0x103c 0x3398 end diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb b/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb index 1867d3a..d8aae6e 100644 --- a/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb @@ -9,6 +9,11 @@ register "superspeed_capable_ports" = "0x0000000f" register "xhci_switchable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x0000000f" + register "usb_port_config" = "{ + {1, 0, 0}, {1, 0, 0}, {1, 0, 0}, {1, 0, 0}, + {1, 0, 3}, {1, 0, 3}, {1, 0, 3}, {1, 0, 3}, + {1, 1, 5}, {1, 0, 5}, {1, 0, 5}, {1, 0, 5}, + {1, 0, 7}, {1, 0, 7}}" device ref xhci on end device ref pcie_rp2 on end diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb b/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb index 560b407..ca6437a 100644 --- a/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb @@ -9,6 +9,11 @@ register "superspeed_capable_ports" = "0x0000000f" register "xhci_switchable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x0000000f" + register "usb_port_config" = "{ + {1, 0, 0}, {1, 0, 0}, {1, 0, 0}, {1, 0, 0}, + {1, 0, 3}, {1, 0, 3}, {1, 0, 3}, {1, 0, 3}, + {1, 1, 5}, {1, 0, 5}, {1, 0, 5}, {1, 0, 5}, + {1, 0, 7}, {1, 0, 7}}" device ref xhci on end end diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb index 092049c..14b5436 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb @@ -23,6 +23,21 @@ register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + {1, 1, 0}, /* SSP1: dock */ + {1, 1, 0}, /* SSP2: left, EHCI Debug */ + {0, 1, 1}, /* SSP3 */ + {1, 1, 1}, /* SSP4: right */ + {0, 0, 2}, /* B0P5 */ + {0, 0, 2}, /* B0P6 */ + {0, 0, 3}, /* B0P7 */ + {1, 0, 3}, /* B0P8: smart card reader */ + {1, 0, 4}, /* B1P1: fingerprint reader */ + {1, 0, 4}, /* B1P2: (EHCI Debug) wlan usb */ + {1, 1, 5}, /* B1P3: Camera */ + {1, 0, 5}, /* B1P4 */ + {1, 0, 6}, /* B1P5: wwan USB */ + {0, 0, 6}}" device ref xhci on end device ref mei1 on end diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb index c73786a..29c3300 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb @@ -21,6 +21,22 @@ # HDD(0), ODD(1), eSATA(4), dock eSATA(5) register "sata_port_map" = "0x33" + register "usb_port_config" = "{ + {1, 1, 0}, /* back bottom USB port, USB debug */ + {1, 1, 0}, /* back upper USB port */ + {1, 1, 1}, /* eSATA */ + {1, 1, 1}, /* webcam */ + {1, 0, 2}, + {1, 0, 2}, /* bluetooth */ + {1, 0, 3}, + {1, 0, 3}, /* smartcard */ + {1, 1, 4}, /* fingerprint reader */ + {1, 1, 4}, /* WWAN */ + {0, 0, 5}, + {1, 0, 5}, /* docking */ + {0, 0, 6}, + {0, 0, 6}}" + device ref pcie_rp1 off end device ref pcie_rp2 on smbios_slot_desc "SlotTypePcmcia" "SlotLengthShort" diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb index af80813..4763fe4 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb @@ -22,6 +22,21 @@ register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + {1, 1, 0}, + {0, 1, 0}, + {1, 1, 1}, + {1, 1, 1}, + {1, 0, 2}, + {1, 0, 2}, /* bluetooth */ + {0, 0, 3}, + {1, 0, 3}, /* smartcard */ + {1, 1, 4}, + {1, 1, 4}, /* mainboard USB 2.0 */ + {1, 0, 5}, /* camera */ + {0, 0, 5}, + {1, 0, 6}, /* WWAN */ + {0, 0, 6}}" device ref xhci on end device ref pcie_rp1 on end diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb index 9d1890a..7afeb9c 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb @@ -20,6 +20,12 @@ register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" register "sata_port_map" = "0x21" + register "usb_port_config" = "{ + {1, 1, 0}, {1, 1, 0}, {1, 1, 1}, {1, 1, 1}, + {1, 0, 2}, {1, 1, 2}, {0, 0, 3}, {1, 0, 3}, + {1, 1, 4}, {1, 0, 4}, {0, 0, 5}, + {1, 1, 5}, {0, 0, 6}, {1, 1, 6}}" + device ref pcie_rp1 on end device ref pcie_rp2 on smbios_slot_desc "SlotTypePcmcia" "SlotLengthShort" diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb index bf64099..621d104 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb @@ -21,6 +21,23 @@ # HDD(0), ODD(1), docking(3,5), eSATA(4) register "sata_port_map" = "0x3b" + register "usb_port_config" = "{ + {1, 1, 0}, /* USB0, eSATA */ + {1, 0, 0}, /* USB charger */ + {0, 1, 1}, + {1, 1, 1}, /* camera */ + {1, 0, 2}, /* USB4 expresscard */ + {1, 0, 2}, /* bluetooth */ + {0, 0, 3}, + {1, 0, 3}, /* smartcard */ + {1, 1, 4}, /* fingerprint */ + {1, 1, 4}, /* WWAN */ + {1, 0, 5}, /* CONN */ + {1, 0, 5}, /* docking */ + {1, 0, 6}, /* CONN */ + {1, 0, 6} /* docking */ + }" + device ref me_kt on end device ref pcie_rp1 on end device ref pcie_rp2 on diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb index cfc5372..8dba1ad 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb @@ -23,6 +23,11 @@ register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + {1, 1, 0}, {1, 1, 0}, {1, 1, 1}, {1, 1, 1}, + {1, 0, 2}, {0, 0, 2}, {0, 0, 3}, {1, 0, 3}, + {1, 1, 4}, {1, 1, 4}, {1, 0, 5}, + {1, 0, 5}, {1, 0, 6}, {1, 0, 6}}" device ref xhci on end device ref me_kt on end diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb index f326c40..acefde2 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb @@ -24,6 +24,22 @@ register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + {1, 1, 0}, /* Dock USB3.0 */ + {1, 1, 0}, /* Conn */ + {1, 1, 1}, /* USB 3.0 */ + {1, 1, 1}, /* USB 3.0 */ + {1, 0, 2}, /* Express Card */ + {1, 0, 2}, /* Bluetooth */ + {0, 0, 3}, + {1, 0, 3}, /* Smart Card */ + {1, 1, 4}, /* Fingerprint Reader */ + {1, 1, 4}, /* Conn (Charger) */ + {1, 0, 5}, /* Camera */ + {1, 0, 5}, /* Dock */ + {1, 0, 6}, /* WWAN */ + {1, 0, 6} /* Conn (eSATA Combo) */ + }" device ref xhci on end device ref pcie_rp1 on end diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb index 1e3984d..11f93f8 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb @@ -22,6 +22,21 @@ register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + {1, 1, 0}, /* SSP1: dock */ + {1, 1, 0}, /* SSP2: left, EHCI Debug */ + {1, 1, 1}, /* SSP3: right back side */ + {1, 1, 1}, /* SSP4: right front side */ + {1, 0, 2}, /* B0P5 */ + {1, 0, 2}, /* B0P6: wlan USB */ + {0, 0, 3}, /* B0P7 */ + {1, 1, 3}, /* B0P8: smart card reader */ + {1, 1, 4}, /* B1P1: fingerprint reader */ + {0, 0, 4}, /* B1P2: (EHCI Debug, not connected) */ + {1, 1, 5}, /* B1P3: Camera */ + {0, 0, 5}, /* B1P4 */ + {1, 1, 6}, /* B1P5: wwan USB */ + {0, 0, 6}}" device ref xhci on end device ref pcie_rp1 on end diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb index 64653bc..8b0526b 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb @@ -20,6 +20,22 @@ # FIXME: ports 3, 5 are untested register "sata_port_map" = "0x3b" + register "usb_port_config" = "{ + {1, 1, 0}, /* left front */ + {1, 1, 0}, /* left rear, debug */ + {1, 1, 1}, /* eSATA */ + {1, 1, 1}, /* webcam */ + {1, 0, 2}, + {1, 0, 2}, /* bluetooth */ + {0, 0, 3}, + {0, 0, 3}, + {1, 1, 4}, /* fingerprint reader */ + {1, 1, 4}, /* WWAN */ + {1, 0, 5}, /* right */ + {1, 0, 5}, + {1, 0, 6}, + {1, 0, 6}}" + device ref pcie_rp1 on end device ref pcie_rp2 on smbios_slot_desc "SlotTypePcmcia" "SlotLengthShort" diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb index 2e36371..6de01b8 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb @@ -22,6 +22,15 @@ register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + {1, 1, 0}, {1, 0, 0}, {1, 1, 1}, {0, 1, 1}, + {0, 0, 2}, {1, 0, 2}, {0, 0, 3}, {0, 0, 3}, + {1, 0, 4}, /* B1P1: Digitizer */ + {1, 0, 4}, /* B1P2: wlan USB, EHCI debug */ + {1, 1, 5}, /* B1P3: Camera */ + {0, 0, 5}, /* B1P4 */ + {1, 0, 6}, /* B1P5: wwan USB */ + {0, 0, 6}}" device ref xhci on end device ref pcie_rp1 on end diff --git a/src/mainboard/intel/dq67sw/devicetree.cb b/src/mainboard/intel/dq67sw/devicetree.cb index f29b772..5216bd9 100644 --- a/src/mainboard/intel/dq67sw/devicetree.cb +++ b/src/mainboard/intel/dq67sw/devicetree.cb @@ -14,6 +14,11 @@ register "sata_port_map" = "0x3f" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" + register "usb_port_config" = "{ + {1, 1, 0}, {1, 1, 0}, {1, 1, 1}, {1, 1, 1}, + {1, 0, 2}, {1, 0, 2}, {1, 0, 3}, {1, 0, 3}, + {1, 1, 4}, {1, 1, 4}, {0, 0, 5}, + {0, 0, 5}, {1, 0, 6}, {1, 0, 6}}" device ref mei1 on end # Management Engine Interface 1 device ref me_ide_r on end # Management Engine IDE-R device ref me_kt on end # Management Engine KT diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index a035628..0fc75e9 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -55,6 +55,22 @@ register "xhci_switchable_ports" = "0x0f" register "superspeed_capable_ports" = "0x0f" + register "usb_port_config" = "{ + { 1, USB_GAIN_L, 0 }, /* P0: lower left USB 3.0 (OC0) */ + { 1, USB_GAIN_L, 0 }, /* P1: upper left USB 3.0 (OC0) */ + { 1, USB_GAIN_L, 0 }, /* P2: lower right USB 3.0 (OC0) */ + { 1, USB_GAIN_L, 0 }, /* P3: upper right USB 3.0 (OC0) */ + { 1, USB_GAIN_L, 0 }, /* P4: lower USB 2.0 (OC0) */ + { 1, USB_GAIN_L, 0 }, /* P5: upper USB 2.0 (OC0) */ + { 1, USB_GAIN_L, 0 }, /* P6: front panel USB 2.0 (OC0) */ + { 1, USB_GAIN_L, 0 }, /* P7: front panel USB 2.0 (OC0) */ + { 1, USB_GAIN_L, 4 }, /* P8: internal USB 2.0 (OC4) */ + { 1, USB_GAIN_L, 4 }, /* P9: internal USB 2.0 (OC4) */ + { 1, USB_GAIN_L, 4 }, /* P10: internal USB 2.0 (OC4) */ + { 1, USB_GAIN_L, 4 }, /* P11: internal USB 2.0 (OC4) */ + { 1, USB_GAIN_L, 4 }, /* P12: internal USB 2.0 (OC4) */ + { 1, USB_GAIN_L, 4 }, /* P13: internal USB 2.0 (OC4) */ + }" device ref xhci on end # USB 3.0 Controller device ref mei1 on end # Management Engine Interface 1 diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index ead7e0b..e1f04ff 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -36,6 +36,12 @@ register "spi_uvscc" = "0" register "spi_lvscc" = "0x2005" + register "usb_port_config" = "{ + {1, 0, -1}, {1, 0, -1}, {1, 0, -1}, {1, 0, -1}, + {1, 0, -1}, {1, 0, -1}, {1, 0, -1}, {1, 0, -1}, + {1, 0, -1}, {1, 0, -1}, {1, 0, -1}, + {1, 0, -1}, {1, 0, -1}, {1, 0, -1}}" + device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 device ref me_ide_r off end # Management Engine IDE-R diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index eae9696..3436b76 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -34,6 +34,11 @@ register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + {1, 1, 0}, {1, 0, 0}, {1, 1, 1}, {1, 0, 1}, + {1, 1, 2}, {1, 0, 2}, {0, 0, 3}, {0, 1, 3}, + {1, 0, 4}, {1, 1, 4}, {1, 1, 5}, + {1, 1, 5}, {1, 1, 6}, {1, 1, 6}}" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index d4b31af..c03487e 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -51,6 +51,24 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" + # OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13 + register "usb_port_config" = "{ + {1, 1, 0}, /* P0: system port 4, OC0 */ + {1, 1, 1}, /* P1: system port 2 (EHCI debug), OC 1 */ + {1, 1, -1}, /* P2: HALF MINICARD (WLAN) no oc */ + {1, 0, -1}, /* P3: WWAN, no OC */ + {1, 0, -1}, /* P4: smartcard, no OC */ + {1, 1, -1}, /* P5: ExpressCard, no OC */ + {0, 0, -1}, /* P6: empty */ + {0, 0, -1}, /* P7: empty */ + {1, 1, 4}, /* P8: system port 3, OC4*/ + {1, 1, 5}, /* P9: system port 1 (EHCI debug), OC 5 */ + {1, 0, -1}, /* P10: fingerprint reader, no OC */ + {1, 0, -1}, /* P11: bluetooth, no OC. */ + {1, 1, -1}, /* P12: docking, no OC */ + {1, 1, -1} /* P13: camera (LCD), no OC */ + }" + device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 device ref me_ide_r off end # Management Engine IDE-R diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index fb30917..1d8851e 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -53,6 +53,23 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" + register "usb_port_config" = "{ + {0, 1, -1}, /* P0: empty */ + {1, 1, 1}, /* P1: system port 2 (To system port) (EHCI debug), OC 1 */ + {1, 1, -1}, /* P2: HALF MINICARD (WLAN) no oc */ + {1, 0, -1}, /* P3: WWAN, no OC */ + {1, 1, -1}, /* P4: smartcard, no OC */ + {1, 1, -1}, /* P5: ExpressCard, no OC */ + {0, 0, -1}, /* P6: empty */ + {0, 0, -1}, /* P7: empty */ + {0, 1, -1}, /* P8: empty (touch panel) */ + {1, 0, 5}, /* P9: system port 1 (To USBAO) (EHCI debug), OC 5 */ + {1, 0, -1}, /* P10: fingerprint reader, no OC */ + {1, 1, -1}, /* P11: bluetooth, no OC. */ + {1, 1, -1}, /* P12: docking, no OC */ + {1, 1, -1} /* P13: camera (LCD), no OC */ + }" + device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 device ref me_ide_r off end # Management Engine IDE-R diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 6492542..eb90f31 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -35,6 +35,11 @@ register "superspeed_capable_ports" = "0x7" register "xhci_switchable_ports" = "0x7" register "xhci_overcurrent_mapping" = "0x04000201" + register "usb_port_config" = "{ + {1, 1, 0}, {1, 1, 1}, {1, 2, 3}, {1, 1, -1}, + {1, 1, 2}, {1, 0, -1}, {0, 0, -1}, {1, 2, -1}, + {1, 0, -1}, {1, 1, 5}, {1, 0, -1}, + {1, 0, -1}, {1, 3, -1}, {1, 1, -1}}" # device specific SPI configuration register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb index 5677a87..a9da730 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb @@ -2,6 +2,22 @@ register "spd_addresses" = "{0x50, 0, 0x51, 0}" device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "usb_port_config" = "{ + { 1, 0, 0 }, /* P0:, OC 0 */ + { 1, 1, 1 }, /* P1: (EHCI debug), OC 1 */ + { 1, 1, 3 }, /* P2: OC 3 */ + { 1, 0, -1 }, /* P3: no OC */ + { 1, 2, -1 }, /* P4: no OC */ + { 1, 1, -1 }, /* P5: no OC */ + { 1, 1, -1 }, /* P6: no OC */ + { 0, 1, -1 }, /* P7: empty, no OC */ + { 1, 1, -1 }, /* P8: smart card reader, no OC */ + { 1, 0, 5 }, /* P9: (EHCI debug), OC 5 */ + { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ + { 1, 1, -1 }, /* P11: bluetooth, no OC. */ + { 0, 0, -1 }, /* P12: wlan, no OC */ + { 1, 1, -1 }, /* P13: camera, no OC */ + }" # Enable hotplug on Port 5 for Thunderbolt controller register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 1, 0, 0, 0 }" device ref pcie_rp5 on end # Thunderbolt controller diff --git a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb index e839358..15712f9 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb @@ -23,6 +23,23 @@ # T431s has no Express Card slot. register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "usb_port_config" = "{ + { 1, 0, 0 }, /* SSP1: right */ + { 1, 0, 1 }, /* SSP2: left, EHCI Debug */ + { 1, 1, 3 }, /* SSP3: dock USB3 */ + { 1, 1, -1 }, /* B0P4: wwan USB */ + { 1, 1, 2 }, /* B0P5: dock USB2 */ + { 0, 0, -1 }, /* B0P6 */ + { 0, 0, -1 }, /* B0P7 */ + { 1, 2, -1 }, /* B0P8: unknown */ + { 1, 0, -1 }, /* B1P1: smart card reader */ + { 0, 2, 5 }, /* B1P2 */ + { 1, 1, -1 }, /* B1P3: fingerprint reader */ + { 0, 0, -1 }, /* B1P4 */ + { 1, 1, -1 }, /* B1P5: wlan USB */ + { 1, 1, -1 }, /* B1P6: Camera */ + }" + device ref pcie_rp1 on chip drivers/ricoh/rce822 # Ricoh cardreader register "disable_mask" = "0x87" diff --git a/src/mainboard/lenovo/t530/variants/t530/overridetree.cb b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb index b574f36..3f058e3 100644 --- a/src/mainboard/lenovo/t530/variants/t530/overridetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb @@ -2,6 +2,22 @@ register "spd_addresses" = "{0x50, 0, 0x51, 0}" device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "usb_port_config" = "{ + { 1, 1, 0 }, /* P0: USB double port upper, USB3, OC 0 */ + { 1, 1, 1 }, /* P1: USB double port lower, USB3, (EHCI debug) OC 1 */ + { 1, 2, 3 }, /* P2: Dock, USB3, OC 3 */ + { 1, 1, -1 }, /* P3: WWAN slot, no OC */ + { 1, 1, 2 }, /* P4: yellow USB, OC 2 */ + { 1, 0, -1 }, /* P5: ExpressCard slot, no OC */ + { 0, 0, -1 }, /* P6: empty */ + { 1, 2, -1 }, /* P7: docking, no OC */ + { 1, 0, -1 }, /* P8: smart card reader, no OC */ + { 1, 1, 5 }, /* P9: USB port single (EHCI debug), OC 5 */ + { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ + { 1, 0, -1 }, /* P11: bluetooth, no OC. */ + { 1, 3, -1 }, /* P12: wlan, no OC - disabled in vendor bios*/ + { 1, 1, -1 }, /* P13: camera, no OC */ + }" device ref lpc on chip ec/lenovo/h8 device pnp ff.2 on end # dummy diff --git a/src/mainboard/lenovo/t530/variants/w530/overridetree.cb b/src/mainboard/lenovo/t530/variants/w530/overridetree.cb index 6b86387..a54db1e 100644 --- a/src/mainboard/lenovo/t530/variants/w530/overridetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/overridetree.cb @@ -5,6 +5,22 @@ subsystemid 0x17aa 0x21f5 end chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "usb_port_config" = "{ + { 1, 1, 0 }, /* P0: USB double port upper, USB3, OC 0 */ + { 1, 1, 1 }, /* P1: USB double port lower, USB3, (EHCI debug) OC 1 */ + { 1, 2, 3 }, /* P2: Dock, USB3, OC 3 */ + { 1, 1, -1 }, /* P3: WWAN slot, no OC */ + { 1, 1, 2 }, /* P4: yellow USB, OC 2 */ + { 1, 0, -1 }, /* P5: ExpressCard slot, no OC */ + { 1, 0, -1 }, /* P6: color sensor, no OC */ + { 1, 2, -1 }, /* P7: docking, no OC */ + { 1, 0, -1 }, /* P8: smart card reader, no OC */ + { 1, 1, 5 }, /* P9: USB port single (EHCI debug), OC 5 */ + { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ + { 1, 0, -1 }, /* P11: bluetooth, no OC. */ + { 1, 3, -1 }, /* P12: wlan, no OC - disabled in vendor bios*/ + { 1, 1, -1 }, /* P13: camera, no OC */ + }" device ref me_kt on end device ref pcie_rp1 on chip drivers/ricoh/rce822 # Ricoh cardreader diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index 96385ed..b74e78f 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -43,6 +43,18 @@ register "xhci_switchable_ports" = "0xf" register "superspeed_capable_ports" = "0xf" register "xhci_overcurrent_mapping" = "0x00000c03" + register "usb_port_config" = "{ + {1, 1, 0}, /* P0: USB 3.0 1 (OC0) */ + {1, 1, 0}, /* P1: USB 3.0 2 (OC0) */ + {0, 0, 0}, + {1, 1, -1}, /* P3: Camera (no OC) */ + {1, 0, -1}, /* P4: WLAN (no OC) */ + {1, 0, -1}, /* P5: WWAN (no OC) */ + {0, 0, 0}, {0, 0, 0}, {0, 0, 0}, + {1, 1, 4}, /* P9: USB 2.0 (AUO4) (OC4) */ + {0, 0, 0}, {0, 0, 0}, {0, 0, 0}, + {1, 0, -1} /* P13: Bluetooth (no OC) */ + }" # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index a423246..4abc9c0 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -43,6 +43,22 @@ register "xhci_switchable_ports" = "0xf" register "superspeed_capable_ports" = "0xf" register "xhci_overcurrent_mapping" = "0x4000201" + register "usb_port_config" = "{ + {0, 3, 0 }, /* P00 disconnected */ + {1, 1, 1 }, /* P01 left or right */ + {0, 1, 3 }, /* P02 disconnected */ + {1, 3, -1}, /* P03 WWAN */ + {0, 1, 2 }, /* P04 disconnected */ + {0, 1, -1}, /* P05 disconnected */ + {0, 1, -1}, /* P06 disconnected */ + {0, 2, -1}, /* P07 disconnected */ + {0, 1, -1}, /* P08 disconnected */ + {1, 2, 5 }, /* P09 left or right */ + {1, 3, -1}, /* P10 FPR */ + {1, 3, -1}, /* P11 Bluetooth */ + {1, 1, -1}, /* P12 WLAN */ + {1, 1, -1} /* P13 Camera */ + }" # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" diff --git a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb index bf88150..9d5778e 100644 --- a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb +++ b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb @@ -16,6 +16,21 @@ subsystemid 0x17aa 0x21e8 inherit chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "usb_port_config" = "{ + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 3 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 3 }, + { 0, 0, 3 }, + { 0, 0, 3 }, + { 1, 1, 4 }, + { 1, 1, 5 }, + { 1, 0, 7 }, + { 1, 1, 7 }, + { 1, 1, 7 }, + { 1, 0, 7 }}" # Enable SATA ports 0 (HDD bay) & 2 (msata) & 3 (esatap) register "sata_port_map" = "0x1d" # X1 does not have ExpressCard slot diff --git a/src/mainboard/lenovo/x230/variants/x230/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230/overridetree.cb index d82faae..e7b06b6 100644 --- a/src/mainboard/lenovo/x230/variants/x230/overridetree.cb +++ b/src/mainboard/lenovo/x230/variants/x230/overridetree.cb @@ -3,6 +3,22 @@ chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH register "docking_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + register "usb_port_config" = "{ + {1, 0, 0 }, /* P0 (left, fan side), OC 0 */ + {1, 0, 1 }, /* P1 (left touchpad side), OC 1 */ + {1, 1, 3 }, /* P2: dock, OC 3 */ + {1, 1, -1}, /* P3: wwan, no OC */ + {1, 1, -1}, /* P4: Wacom tablet on X230t, otherwise empty */ + {1, 1, -1}, /* P5: Expresscard, no OC */ + {0, 0, -1}, /* P6: Empty */ + {1, 2, -1}, /* P7: dock, no OC */ + {0, 0, -1}, /* P8: Empty */ + {1, 2, 5 }, /* P9: Right (EHCI debug), OC 5 */ + {1, 1, -1}, /* P10: fingerprint reader, no OC */ + {1, 1, -1}, /* P11: bluetooth, no OC. */ + {1, 1, -1}, /* P12: wlan, no OC */ + {1, 1, -1}, /* P13: webcam, no OC */ + }" device ref pcie_rp3 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end diff --git a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb index 09e7f92..a84b5f3 100644 --- a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb +++ b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb @@ -18,7 +18,22 @@ # X230s does not support docking # Enable SATA ports 0 (HDD bay) & 1 (WWAN M.2 SATA) register "sata_port_map" = "0x3" - + register "usb_port_config" = "{ + {1, 3, 0}, /* SSP1: Right */ + {1, 3, 1}, /* SSP2: Left, EHCI Debug */ + {0, 1, 3}, /* SSP3 */ + {1, 3, -1}, /* B0P4: WWAN USB */ + {0, 1, 2}, /* B0P5 */ + {0, 1, -1}, /* B0P6 */ + {0, 1, -1}, /* B0P7 */ + {0, 1, -1}, /* B0P8 */ + {0, 1, -1}, /* B1P1 */ + {0, 1, 5}, /* B1P2 */ + {1, 1, -1}, /* B1P3: Fingerprint Reader */ + {0, 1, -1}, /* B1P4 */ + {1, 3, -1}, /* B1P5: WLAN USB */ + {1, 1, -1}, /* B1P6: Camera */ + }" device ref lpc on chip ec/lenovo/h8 register "config1" = "0x05" diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb index 90eea95..c373cb8 100644 --- a/src/mainboard/msi/ms7707/devicetree.cb +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -17,6 +17,11 @@ register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" register "gpe0_en" = "0x28000040" + register "usb_port_config" = "{ + {1, 0, 0}, {1, 0, 0}, {1, 0, 1}, {1, 0, 1}, + {1, 0, 2}, {1, 0, 2}, {1, 0, 3}, {1, 0, 3}, + {1, 0, 4}, {1, 0, 4}, {1, 0, 6}, + {1, 0, 5}, {1, 0, 5}, {1, 0, 6}}" device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index 87d1532..6de2e5a 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -9,6 +9,12 @@ register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" + register "usb_port_config" = "{ + {1, 0, 0}, {1, 0, 0}, {1, 0, 1}, {1, 0, 1}, + {1, 0, 2}, {1, 0, 2}, {1, 0, 3}, {1, 0, 3}, + {1, 0, 4}, {1, 0, 4}, {1, 0, 6}, + {1, 0, 5}, {1, 0, 5}, {1, 0, 6}}" + register "spi.opprefixes" = "{ 0x50, 0x06 }" register "spi.ops" = "{{0x01, WRITE_NO_ADDR}, {0x02, WRITE_WITH_ADDR}, diff --git a/src/mainboard/supermicro/x9sae/devicetree.cb b/src/mainboard/supermicro/x9sae/devicetree.cb index f518381..d8d3159 100644 --- a/src/mainboard/supermicro/x9sae/devicetree.cb +++ b/src/mainboard/supermicro/x9sae/devicetree.cb @@ -26,6 +26,11 @@ register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + {1, 0, 0}, {1, 0, 0}, {1, 0, 1}, {1, 0, 1}, + {1, 0, 2}, {1, 0, 2}, {1, 0, 3}, {1, 0, 3}, + {1, 0, 4}, {1, 0, 4}, {1, 0, 6}, + {1, 0, 5}, {1, 0, 5}, {1, 0, 6}}" device ref xhci on end # xHCI device ref mei1 on end # MEI #1 diff --git a/src/mainboard/supermicro/x9scl/devicetree.cb b/src/mainboard/supermicro/x9scl/devicetree.cb index 203a7a6..de7decf 100644 --- a/src/mainboard/supermicro/x9scl/devicetree.cb +++ b/src/mainboard/supermicro/x9scl/devicetree.cb @@ -17,6 +17,13 @@ register "sata_port_map" = "0x3f" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" + + register "usb_port_config" = "{ + {1, 0, 0}, {1, 0, 0}, {1, 0, 1}, {1, 0, 1}, + {1, 0, 2}, {1, 0, 2}, {1, 0, 3}, {1, 0, 3}, + {1, 0, 4}, {1, 0, 4}, {1, 0, 6}, + {1, 0, 5}, {1, 0, 5}, {1, 0, 6}}" + device ref mei1 off end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 device ref me_ide_r off end # Management Engine IDE-R -- To view, visit https://review.coreboot.org/c/coreboot/+/81879?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia8a967eb3466106f3a34e024260e13d02f449a25 Gerrit-Change-Number: 81879 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Attention: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: sb/intel/bd82x6x: Make space for USB port config in devicetree
by Keith Hui (Code Review) 13 Apr '24

13 Apr '24

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81878?usp=email ) Change subject: sb/intel/bd82x6x: Make space for USB port config in devicetree ...................................................................... sb/intel/bd82x6x: Make space for USB port config in devicetree This is the first step to: - Move USB port configs, which are static, from C code to devicetree; - Unify USB port configs between MRC and native code path. For USB current strength/trace length settings, define one set of constants that match the selected RAM init code path, so compiler can produce the correct values for runtime. This structure will otherwise match the one in C code used by native code path. Change-Id: I59af466d41790e2163342cac8676457ac19371ea Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/southbridge/intel/bd82x6x/chip.h 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/81878/1 diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 66d5cb1..95ca08b 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -5,6 +5,20 @@ #include <southbridge/intel/common/spi.h> #include <types.h> +#include <southbridge/intel/bd82x6x/pch.h> + +/* Shorthands for boards using MRC */ +#if CONFIG(USE_NATIVE_RAMINIT) +#define USB_GAIN_1 1 +#define USB_GAIN_2 2 +#define USB_GAIN_L 0 +#define USB_GAIN_H 1 +#else +#define USB_GAIN_1 0x40 +#define USB_GAIN_2 0x80 +#define USB_GAIN_L 0x40 +#define USB_GAIN_H 0x80 +#endif struct southbridge_intel_bd82x6x_config { /** @@ -77,6 +91,7 @@ uint32_t spi_uvscc; uint32_t spi_lvscc; struct intel_swseq_spi_config spi; + struct southbridge_usb_port usb_port_config[14]; }; #endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81878?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I59af466d41790e2163342cac8676457ac19371ea Gerrit-Change-Number: 81878 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: nb/intel/sandybridge: Pre-render constants in MRC pei_data
by Keith Hui (Code Review) 13 Apr '24

13 Apr '24

Attention is currently required from: Angel Pons. Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78206?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: nb/intel/sandybridge: Pre-render constants in MRC pei_data ...................................................................... nb/intel/sandybridge: Pre-render constants in MRC pei_data Portions of MRC raminit code only serves to enter fixed constants into pei_data structure for MRC consumption. Since the constants are all to the front of the structure, set up a truncated copy for compiler to render at build time. Chipset code then uses it as a base to initialize the (in-CAR) structure and fill out the rest at runtime. TEST=No regression observed when booting on asus/p8z77-m. Change-Id: Ic0f429a7be11ea497ce31cde007966ea988a256f Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_mrc.c 1 file changed, 39 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/78206/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/78206?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic0f429a7be11ea497ce31cde007966ea988a256f Gerrit-Change-Number: 78206 Gerrit-PatchSet: 4 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[main]: mb/google/brya: Enable UFS driver for edk2 payload
by Subrata Banik (Code Review) 13 Apr '24

13 Apr '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Matt DeVillier, Nick Vaccaro. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81871?usp=email ) Change subject: mb/google/brya: Enable UFS driver for edk2 payload ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81871?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dc018582e974bf73c7668f78da9b81eeb038c01 Gerrit-Change-Number: 81871 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 13 Apr 2024 03:46:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[L] Change in coreboot[main]: Haswell NRI: Implement fast boot path
by Angel Pons (Code Review) 13 Apr '24

13 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81897?usp=email ) Change subject: Haswell NRI: Implement fast boot path ...................................................................... Haswell NRI: Implement fast boot path When the memory configuration hasn't changed, there is no need to do full memory training. Instead, boot firmware can use saved training data to reinitialise the memory controller and memory. Unlike native RAM init for other platforms, Haswell does not save the main structure (the "mighty ctrl" struct) to flash. Instead, separate structures define the data to be saved, which can be smaller than the main structure. This makes S3 suspend and resume work: RAM contents MUST be preserved for a S3 resume to succeed, but RAM training destroys RAM contents. Change-Id: I06f6cd39ceecdca104fae89159f28e85cf7ff4e6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/native_raminit/Makefile.mk M src/northbridge/intel/haswell/native_raminit/activate_mc.c M src/northbridge/intel/haswell/native_raminit/ddr3.c M src/northbridge/intel/haswell/native_raminit/raminit_main.c M src/northbridge/intel/haswell/native_raminit/raminit_native.c M src/northbridge/intel/haswell/native_raminit/raminit_native.h A src/northbridge/intel/haswell/native_raminit/save_restore.c 7 files changed, 504 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/81897/1 diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index d97da72..8fdd17c54 100644 --- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk +++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -13,6 +13,7 @@ romstage-y += raminit_native.c romstage-y += ranges.c romstage-y += reut.c +romstage-y += save_restore.c romstage-y += setup_wdb.c romstage-y += spd_bitmunching.c romstage-y += testing_io.c diff --git a/src/northbridge/intel/haswell/native_raminit/activate_mc.c b/src/northbridge/intel/haswell/native_raminit/activate_mc.c index 78a7ad2..0b3eb91 100644 --- a/src/northbridge/intel/haswell/native_raminit/activate_mc.c +++ b/src/northbridge/intel/haswell/native_raminit/activate_mc.c @@ -333,6 +333,23 @@ return RAMINIT_STATUS_SUCCESS; } +enum raminit_status normal_state(struct sysinfo *ctrl) +{ + /* Enable periodic COMP */ + mchbar_write32(M_COMP, (union pcu_comp_reg) { + .comp_interval = COMP_INT, + }.raw); + for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { + if (!does_ch_exist(ctrl, channel)) + continue; + + /* Set MC to normal mode and clean the ODT and CKE */ + mchbar_write32(REUT_ch_SEQ_CFG(channel), REUT_MODE_NOP << 12); + } + power_down_config(ctrl); + return RAMINIT_STATUS_SUCCESS; +} + static void mc_lockdown(void) { /* Lock memory controller registers */ diff --git a/src/northbridge/intel/haswell/native_raminit/ddr3.c b/src/northbridge/intel/haswell/native_raminit/ddr3.c index 6ddb114..9b6368e 100644 --- a/src/northbridge/intel/haswell/native_raminit/ddr3.c +++ b/src/northbridge/intel/haswell/native_raminit/ddr3.c @@ -2,6 +2,7 @@ #include <assert.h> #include <console/console.h> +#include <delay.h> #include <northbridge/intel/haswell/haswell.h> #include <types.h> @@ -215,3 +216,43 @@ ddr3_program_mr0(ctrl, 1); return reut_issue_zq(ctrl, ctrl->chanmap, ZQ_INIT); } + +enum raminit_status exit_selfrefresh(struct sysinfo *ctrl) +{ + for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { + if (!does_ch_exist(ctrl, channel)) + continue; + + /* Fields in ctrl aren't populated on a warm boot */ + union ddr_data_control_0_reg data_control_0 = { + .raw = mchbar_read32(DQ_CONTROL_0(channel, 0)), + }; + data_control_0.read_rf_rd = 1; + for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) { + if (!rank_in_ch(ctrl, rank, channel)) + continue; + + data_control_0.read_rf_rank = rank; + mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw); + } + } + + /* Time needed to stabilize the DCLK (~6 us) */ + udelay(6); + + /* Pull the DIMMs out of self refresh by asserting CKE high */ + for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { + const union reut_misc_cke_ctrl_reg reut_misc_cke_ctrl = { + .cke_on = ctrl->rankmap[channel], + }; + mchbar_write32(REUT_ch_MISC_CKE_CTRL(channel), reut_misc_cke_ctrl.raw); + } + mchbar_write32(REUT_MISC_ODT_CTRL, 0); + + const enum raminit_status status = reut_issue_zq(ctrl, ctrl->chanmap, ZQ_LONG); + if (status) { + /* ZQCL errors don't seem to be a fatal problem here */ + printk(BIOS_ERR, "ZQ Long failed during S3 resume or warm reset flow\n"); + } + return RAMINIT_STATUS_SUCCESS; +} diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c index 3a65fb0..056dde1 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c @@ -64,6 +64,22 @@ { train_read_mpr, true, "RDMPRT", }, { train_jedec_write_leveling, true, "JWRL", }, { activate_mc, true, "ACTIVATE", }, + { save_training_values, true, "SAVE_TRAIN", }, + { save_non_training, true, "SAVE_NONT", }, + { raminit_done, true, "RAMINITEND", }, +}; + +static const struct task_entry fast_boot[] = { + { collect_spd_info, true, "PROCSPD", }, + { restore_non_training, true, "RST_NONT", }, + { initialise_mpll, true, "INITMPLL", }, + { configure_mc, true, "CONFMC", }, + { configure_memory_map, true, "MEMMAP", }, + { do_jedec_init, true, "JEDECINIT", }, + { pre_training, true, "PRETRAIN", }, + { restore_training_values, true, "RST_TRAIN", }, + { exit_selfrefresh, true, "EXIT_SR", }, + { normal_state, true, "NORMALMODE", }, { raminit_done, true, "RAMINITEND", }, }; @@ -102,11 +118,11 @@ ctrl->bootmode = bootmode; } -static enum raminit_status try_raminit(struct sysinfo *ctrl) +static enum raminit_status try_raminit( + struct sysinfo *ctrl, + const struct task_entry *const schedule, + const size_t length) { - const struct task_entry *const schedule = cold_boot; - const size_t length = ARRAY_SIZE(cold_boot); - enum raminit_status status = RAMINIT_STATUS_UNSPECIFIED_ERROR; for (size_t i = 0; i < length; i++) { @@ -140,8 +156,16 @@ mighty_ctrl.bootmode = bootmode; initialize_ctrl(&mighty_ctrl); + enum raminit_status status = RAMINIT_STATUS_UNSPECIFIED_ERROR; + + if (bootmode != BOOTMODE_COLD) { + status = try_raminit(&mighty_ctrl, fast_boot, ARRAY_SIZE(fast_boot)); + if (status == RAMINIT_STATUS_SUCCESS) + return; + } + /** TODO: Try more than once **/ - enum raminit_status status = try_raminit(&mighty_ctrl); + status = try_raminit(&mighty_ctrl, cold_boot, ARRAY_SIZE(cold_boot)); if (status != RAMINIT_STATUS_SUCCESS) die("Memory initialization was met with utmost failure and misery\n"); diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c index 5f7ceec..3ad8ce2 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c @@ -54,23 +54,17 @@ return cpu_replaced; } -#define MRC_CACHE_VERSION 1 - -struct mrc_data { - const void *buffer; - size_t buffer_len; -}; - -static void save_mrc_data(struct mrc_data *md) +static void save_mrc_data(void) { - mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, md->buffer, md->buffer_len); + mrc_cache_stash_data(MRC_TRAINING_DATA, reg_frame_rev(), + reg_frame_ptr(), reg_frame_size()); } static struct mrc_data prepare_mrc_cache(void) { struct mrc_data md = {0}; md.buffer = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, - MRC_CACHE_VERSION, + reg_frame_rev(), &md.buffer_len); return md; } @@ -94,14 +88,15 @@ } static enum raminit_boot_mode do_actual_raminit( - struct mrc_data *md, const bool s3resume, const bool cpu_replaced, const enum raminit_boot_mode orig_bootmode) { + struct mrc_data md = prepare_mrc_cache(); + enum raminit_boot_mode bootmode = orig_bootmode; - bool save_data_valid = md->buffer && md->buffer_len == USHRT_MAX; /** TODO: sizeof() **/ + bool save_data_valid = md.buffer && md.buffer_len == reg_frame_size(); if (s3resume) { if (bootmode == BOOTMODE_COLD) { @@ -154,7 +149,7 @@ assert(save_data_valid != (bootmode == BOOTMODE_COLD)); if (save_data_valid) { printk(BIOS_INFO, "Using cached memory parameters\n"); - die("RAMINIT: Fast boot is not yet implemented\n"); + memcpy(reg_frame_ptr(), md.buffer, reg_frame_size()); } printk(RAM_DEBUG, "Initial bootmode: %s\n", bm_names[orig_bootmode]); printk(RAM_DEBUG, "Current bootmode: %s\n", bm_names[bootmode]); @@ -181,10 +176,8 @@ wait_txt_clear(); wrmsr(0x2e6, (msr_t) {.lo = 0, .hi = 0}); - struct mrc_data md = prepare_mrc_cache(); - const enum raminit_boot_mode bootmode = - do_actual_raminit(&md, s3resume, cpu_replaced, orig_bootmode); + do_actual_raminit(s3resume, cpu_replaced, orig_bootmode); /** TODO: report_memory_config **/ @@ -212,9 +205,8 @@ } /* Save training data on non-S3 resumes */ - /** TODO: Enable this once training data is populated **/ - if (0 && !s3resume) - save_mrc_data(&md); + if (!s3resume) + save_mrc_data(); /** TODO: setup_sdram_meminfo **/ } diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h index 9bab57b5..0750904 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h @@ -169,6 +169,8 @@ REG_FILE_USE_CURRENT, /* Used when changing parameters after the test */ }; +struct register_save_frame; + struct wdb_pat { uint32_t start_ptr; /* Starting pointer in WDB */ uint32_t stop_ptr; /* Stopping pointer in WDB */ @@ -219,6 +221,7 @@ RAMINIT_STATUS_RCVEN_FAILURE, RAMINIT_STATUS_RMPR_FAILURE, RAMINIT_STATUS_JWRL_FAILURE, + RAMINIT_STATUS_INVALID_CACHE, RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/ }; @@ -228,6 +231,11 @@ STEPPING_C0 = 3, }; +struct mrc_data { + const void *buffer; + size_t buffer_len; +}; + struct raminit_dimm_info { spd_raw_data raw_spd; struct dimm_attr_ddr3_st data; @@ -447,12 +455,22 @@ enum raminit_status train_receive_enable(struct sysinfo *ctrl); enum raminit_status train_read_mpr(struct sysinfo *ctrl); enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl); +enum raminit_status save_training_values(struct sysinfo *ctrl); +enum raminit_status restore_training_values(struct sysinfo *ctrl); +enum raminit_status save_non_training(struct sysinfo *ctrl); +enum raminit_status restore_non_training(struct sysinfo *ctrl); +enum raminit_status exit_selfrefresh(struct sysinfo *ctrl); +enum raminit_status normal_state(struct sysinfo *ctrl); enum raminit_status activate_mc(struct sysinfo *ctrl); enum raminit_status raminit_done(struct sysinfo *ctrl); void configure_timings(struct sysinfo *ctrl); void configure_refresh(struct sysinfo *ctrl); +struct register_save_frame *reg_frame_ptr(void); +size_t reg_frame_size(void); +uint32_t reg_frame_rev(void); + uint32_t get_tCKE(uint32_t mem_clock_mhz, bool lpddr); uint32_t get_tXPDLL(uint32_t mem_clock_mhz); uint32_t get_tAONPD(uint32_t mem_clock_mhz); diff --git a/src/northbridge/intel/haswell/native_raminit/save_restore.c b/src/northbridge/intel/haswell/native_raminit/save_restore.c new file mode 100644 index 0000000..f1f50e3 --- /dev/null +++ b/src/northbridge/intel/haswell/native_raminit/save_restore.c @@ -0,0 +1,387 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <assert.h> +#include <console/console.h> +#include <northbridge/intel/haswell/haswell.h> +#include <types.h> + +#include "raminit_native.h" + +uint32_t reg_frame_rev(void) +{ + /* + * Equivalent to MRC_CACHE_REVISION, but hidden via abstraction. + * The structures that get saved to flash are contained within + * this translation unit, so changes outside this file shouldn't + * require invalidating the cache. + */ + return 1; +} + +struct register_save { + uint16_t lower; + uint16_t upper; +}; + +/** TODO: Haswell DDRIO aliases writes: 0x80 .. 0xff => 0x00 .. 0x7f **/ +static const struct register_save ddrio_per_byte_list[] = { + {0x0000, 0x003c}, /* 16 registers */ +// {0x0048, 0x0084}, /* 16 registers */ /** TODO: BDW support **/ + {0x0048, 0x004c}, /* 2 registers */ + {0x005c, 0x0078}, /* 8 registers */ +}; +#define DDRIO_PER_BYTE_REGISTER_COUNT (16 + 2 + 8) + +static const struct register_save ddrio_per_ch_list[] = { + /* CKE */ + {0x1204, 0x1208}, /* 2 registers */ + {0x1214, 0x121c}, /* 3 registers */ + /* CMD North */ + {0x1404, 0x140c}, /* 3 registers */ + /* CLK */ + {0x1808, 0x1810}, /* 3 registers */ + /* CMD South */ + {0x1a04, 0x1a0c}, /* 3 registers */ + /* CTL */ + {0x1c14, 0x1c1c}, /* 3 registers */ +}; +#define DDRIO_PER_CH_REGISTER_COUNT (2 + 3 * 5) + +static const struct register_save ddrio_common_list[] = { + {0x2000, 0x2008}, /* 3 registers */ + {0x3a14, 0x3a1c}, /* 3 registers */ + {0x3a24, 0x3a24}, /* 1 registers */ +}; + +#define DDRIO_COMMON_REGISTER_COUNT (3 + 3 + 1) + +static const struct register_save mcmain_per_ch_list[] = { + {0x4000, 0x4014}, /* 6 registers */ + {0x4024, 0x4028}, /* 2 registers */ + {0x40d0, 0x40d0}, /* 1 registers */ + {0x4220, 0x4224}, /* 2 registers */ + {0x4294, 0x4294}, /* 1 registers */ + {0x429c, 0x42a0}, /* 2 registers */ + {0x42ec, 0x42fc}, /* 5 registers */ + {0x4328, 0x4328}, /* 1 registers */ + {0x438c, 0x4390}, /* 2 registers */ +}; +#define MCMAIN_PER_CH_REGISTER_COUNT (6 + 2 + 1 + 2 + 1 + 2 + 5 + 1 + 2) + +static const struct register_save misc_common_list[] = { + {0x5884, 0x5888}, /* 2 registers */ + {0x5890, 0x589c}, /* 4 registers */ + {0x58a4, 0x58a4}, /* 1 registers */ + {0x58d0, 0x58e4}, /* 6 registers */ + {0x5880, 0x5880}, /* 1 registers */ + {0x5000, 0x50dc}, /* 56 registers */ + {0x59b8, 0x59b8} /* 1 registers */ +}; +#define MISC_COMMON_REGISTER_COUNT (2 + 4 + 1 + 6 + 1 + 56 + 1) + +struct save_params { + bool is_initialised; + + /* Memory base frequency, either 100 or 133 MHz */ + uint8_t base_freq; + + /* Multiplier */ + uint32_t multiplier; + + /* Memory clock in MHz */ + uint32_t mem_clock_mhz; + + /* Memory clock in femtoseconds */ + uint32_t mem_clock_fs; + + /* Quadrature clock in picoseconds */ + uint16_t qclkps; + + /* Bitfield of supported CAS latencies */ + uint16_t cas_supported; + + /* CPUID value */ + uint32_t cpu; + + /* Cached CPU stepping value */ + uint8_t stepping; + + uint16_t vdd_mv; + + union dimm_flags_ddr3_st flags; + + /* Except for tCK, everything is stored in DCLKs */ + uint32_t tCK; + uint32_t tAA; + uint32_t tWR; + uint32_t tRCD; + uint32_t tRRD; + uint32_t tRP; + uint32_t tRAS; + uint32_t tRC; + uint32_t tRFC; + uint32_t tWTR; + uint32_t tRTP; + uint32_t tFAW; + uint32_t tCWL; + uint32_t tCMD; + + uint32_t tREFI; + uint32_t tXP; + + uint8_t lpddr_cke_rank_map[NUM_CHANNELS]; + + struct raminit_dimm_info dimms[NUM_CHANNELS][NUM_SLOTS]; + + uint8_t chanmap; + + uint32_t channel_size_mb[NUM_CHANNELS]; + + /* DIMMs per channel */ + uint8_t dpc[NUM_CHANNELS]; + + uint8_t rankmap[NUM_CHANNELS]; + + /* Whether a rank is mirrored or not (only rank 1 of each DIMM can be) */ + uint8_t rank_mirrored[NUM_CHANNELS]; + + /* + * FIXME: LPDDR support is incomplete. The largest chunks are missing, + * but some LPDDR-specific variations in algorithms have been handled. + * LPDDR-specific functions have stubs which will halt upon execution. + */ + bool lpddr; + + uint8_t lanes; + + /* FIXME: ECC support missing */ + bool is_ecc; +}; + +struct register_save_frame { + uint32_t ddrio_per_byte[NUM_CHANNELS][NUM_LANES][DDRIO_PER_BYTE_REGISTER_COUNT]; + uint32_t ddrio_per_ch[NUM_CHANNELS][DDRIO_PER_CH_REGISTER_COUNT]; + uint32_t ddrio_common[DDRIO_COMMON_REGISTER_COUNT]; + uint32_t mcmain_per_ch[NUM_CHANNELS][MCMAIN_PER_CH_REGISTER_COUNT]; + uint32_t misc_common[MISC_COMMON_REGISTER_COUNT]; + struct save_params params; +}; + +struct register_save_frame *reg_frame_ptr(void) +{ + /* The chonky register save frame struct, used for fast boot and S3 resume */ + static struct register_save_frame register_frame = { 0 }; + return &register_frame; +} + +size_t reg_frame_size(void) +{ + return sizeof(struct register_save_frame); +} + +typedef void (*reg_func_t)(const uint16_t offset, uint32_t *const value); + +static void save_value(const uint16_t offset, uint32_t *const value) +{ + *value = mchbar_read32(offset); +} + +static void restore_value(const uint16_t offset, uint32_t *const value) +{ + mchbar_write32(offset, *value); +} + +static void save_restore( + uint32_t *reg_frame, + const uint16_t g_offset, + const struct register_save *reg_save_list, + const size_t reg_save_length, + reg_func_t handle_reg) +{ + for (size_t i = 0; i < reg_save_length; i++) { + const struct register_save *entry = &reg_save_list[i]; + for (uint16_t offset = entry->lower; offset <= entry->upper; offset += 4) { + handle_reg(offset + g_offset, reg_frame++); + } + } +} + +static void save_restore_all(struct register_save_frame *reg_frame, reg_func_t handle_reg) +{ + for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { + for (uint8_t byte = 0; byte < NUM_LANES; byte++) { + const uint16_t g_offset = _DDRIO_C_R_B(0, channel, 0, byte); + save_restore( + reg_frame->ddrio_per_byte[channel][byte], + g_offset, + ddrio_per_byte_list, + ARRAY_SIZE(ddrio_per_byte_list), + handle_reg); + } + } + for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { + const uint16_t g_offset = _DDRIO_C_R_B(0, channel, 0, 0); + save_restore( + reg_frame->ddrio_per_ch[channel], + g_offset, + ddrio_per_ch_list, + ARRAY_SIZE(ddrio_per_ch_list), + handle_reg); + } + save_restore( + reg_frame->ddrio_common, + 0, + ddrio_common_list, + ARRAY_SIZE(ddrio_common_list), + handle_reg); + + for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { + const uint16_t g_offset = _MCMAIN_C(0, channel); + save_restore( + reg_frame->mcmain_per_ch[channel], + g_offset, + mcmain_per_ch_list, + ARRAY_SIZE(mcmain_per_ch_list), + handle_reg); + } + save_restore( + reg_frame->misc_common, + 0, + misc_common_list, + ARRAY_SIZE(misc_common_list), + handle_reg); +} + +enum raminit_status save_training_values(struct sysinfo *ctrl) +{ + save_restore_all(reg_frame_ptr(), save_value); + return RAMINIT_STATUS_SUCCESS; +} + +enum raminit_status restore_training_values(struct sysinfo *ctrl) +{ + save_restore_all(reg_frame_ptr(), restore_value); + return RAMINIT_STATUS_SUCCESS; +} + +enum raminit_status save_non_training(struct sysinfo *ctrl) +{ + struct register_save_frame *reg_frame = reg_frame_ptr(); + struct save_params *params = &reg_frame->params; + + params->is_initialised = true; + + params->base_freq = ctrl->base_freq; + params->multiplier = ctrl->multiplier; + params->mem_clock_mhz = ctrl->mem_clock_mhz; + params->mem_clock_fs = ctrl->mem_clock_fs; + params->qclkps = ctrl->qclkps; + params->cas_supported = ctrl->cas_supported; + params->cpu = ctrl->cpu; + params->stepping = ctrl->stepping; + params->vdd_mv = ctrl->vdd_mv; + params->flags = ctrl->flags; + + params->tCK = ctrl->tCK; + params->tAA = ctrl->tAA; + params->tWR = ctrl->tWR; + params->tRCD = ctrl->tRCD; + params->tRRD = ctrl->tRRD; + params->tRP = ctrl->tRP; + params->tRAS = ctrl->tRAS; + params->tRC = ctrl->tRC; + params->tRFC = ctrl->tRFC; + params->tWTR = ctrl->tWTR; + params->tRTP = ctrl->tRTP; + params->tFAW = ctrl->tFAW; + params->tCWL = ctrl->tCWL; + params->tCMD = ctrl->tCMD; + params->tREFI = ctrl->tREFI; + params->tXP = ctrl->tXP; + + params->chanmap = ctrl->chanmap; + for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { + params->lpddr_cke_rank_map[channel] = ctrl->lpddr_cke_rank_map[channel]; + for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) + params->dimms[channel][slot] = ctrl->dimms[channel][slot]; + } + for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { + params->dpc[channel] = ctrl->dpc[channel]; + params->rankmap[channel] = ctrl->rankmap[channel]; + params->rank_mirrored[channel] = ctrl->rank_mirrored[channel]; + params->channel_size_mb[channel] = ctrl->channel_size_mb[channel]; + } + params->lpddr = ctrl->lpddr; + params->lanes = ctrl->lanes; + params->is_ecc = ctrl->is_ecc; + return RAMINIT_STATUS_SUCCESS; +} + +#define RAMINIT_COMPARE(_s1, _s2) \ + ((sizeof(_s1) == sizeof(_s2)) && !memcmp(_s1, _s2, sizeof(_s1))) + +enum raminit_status restore_non_training(struct sysinfo *ctrl) +{ + struct register_save_frame *reg_frame = reg_frame_ptr(); + struct save_params *params = &reg_frame->params; + + if (!params->is_initialised) { + printk(BIOS_WARNING, "Cannot fast boot: saved data is invalid\n"); + return RAMINIT_STATUS_INVALID_CACHE; + } + + if (!RAMINIT_COMPARE(ctrl->dimms, params->dimms)) { + printk(BIOS_WARNING, "Cannot fast boot: DIMMs have changed\n"); + return RAMINIT_STATUS_INVALID_CACHE; + } + + if (ctrl->cpu != params->cpu) { + printk(BIOS_WARNING, "Cannot fast boot: CPU has changed\n"); + return RAMINIT_STATUS_INVALID_CACHE; + } + + ctrl->base_freq = params->base_freq; + ctrl->multiplier = params->multiplier; + ctrl->mem_clock_mhz = params->mem_clock_mhz; + ctrl->mem_clock_fs = params->mem_clock_fs; + ctrl->qclkps = params->qclkps; + ctrl->cas_supported = params->cas_supported; + ctrl->cpu = params->cpu; + ctrl->stepping = params->stepping; + ctrl->vdd_mv = params->vdd_mv; + ctrl->flags = params->flags; + + ctrl->tCK = params->tCK; + ctrl->tAA = params->tAA; + ctrl->tWR = params->tWR; + ctrl->tRCD = params->tRCD; + ctrl->tRRD = params->tRRD; + ctrl->tRP = params->tRP; + ctrl->tRAS = params->tRAS; + ctrl->tRC = params->tRC; + ctrl->tRFC = params->tRFC; + ctrl->tWTR = params->tWTR; + ctrl->tRTP = params->tRTP; + ctrl->tFAW = params->tFAW; + ctrl->tCWL = params->tCWL; + ctrl->tCMD = params->tCMD; + ctrl->tREFI = params->tREFI; + ctrl->tXP = params->tXP; + + ctrl->chanmap = params->chanmap; + for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { + ctrl->lpddr_cke_rank_map[channel] = params->lpddr_cke_rank_map[channel]; + for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) + ctrl->dimms[channel][slot] = params->dimms[channel][slot]; + } + for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { + ctrl->dpc[channel] = params->dpc[channel]; + ctrl->rankmap[channel] = params->rankmap[channel]; + ctrl->rank_mirrored[channel] = params->rank_mirrored[channel]; + ctrl->channel_size_mb[channel] = params->channel_size_mb[channel]; + } + ctrl->lpddr = params->lpddr; + ctrl->lanes = params->lanes; + ctrl->is_ecc = params->is_ecc; + return RAMINIT_STATUS_SUCCESS; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/81897?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I06f6cd39ceecdca104fae89159f28e85cf7ff4e6 Gerrit-Change-Number: 81897 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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