coreboot-gerrit April 2024

coreboot-gerrit@coreboot.org

1 participants
3293 discussions

[M] Change in coreboot[main]: haswell NRI: Post-process selected timings
by Angel Pons (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Arthur Heymans, Nico Huber. Hello Arthur Heymans, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64185?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: haswell NRI: Post-process selected timings ...................................................................... haswell NRI: Post-process selected timings Once the MPLL has been initialised, convert the timings from the SPD to be in DCLKs, which is what the hardware expects. In addition, calculate the values for tREFI and tXP. Change-Id: Id02caf858f75b9e08016762b3aefda282b274386 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/native_raminit/Makefile.mk A src/northbridge/intel/haswell/native_raminit/lookup_timings.c M src/northbridge/intel/haswell/native_raminit/raminit_main.c M src/northbridge/intel/haswell/native_raminit/raminit_native.h M src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c 5 files changed, 172 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/64185/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/64185?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id02caf858f75b9e08016762b3aefda282b274386 Gerrit-Change-Number: 64185 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[main]: mb/google/zork: Increase SMMSTORE size to 256K
by Matt DeVillier (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Jason Nien, Martin Roth. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81869?usp=email ) Change subject: mb/google/zork: Increase SMMSTORE size to 256K ...................................................................... mb/google/zork: Increase SMMSTORE size to 256K Anything below 128K will cause SMMSTORE driver in edk2 to fail, since a minimum of (2) 64K blocks are needed. Increase the size to 256K to match other boards in the tree. TEST=build/boot zork (morphius) with SMMSTORE enabled. Change-Id: Ifd3be9b0757e270d2f106e2fbebf3991e49dec65 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/zork/chromeos.fmd 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/81869/1 diff --git a/src/mainboard/google/zork/chromeos.fmd b/src/mainboard/google/zork/chromeos.fmd index 4d2eda0..b405b2f 100644 --- a/src/mainboard/google/zork/chromeos.fmd +++ b/src/mainboard/google/zork/chromeos.fmd @@ -19,7 +19,7 @@ RW_VPD(PRESERVE) 8K RW_NVRAM(PRESERVE) 20K PAD_TO_ALIGN_STORE 16K - SMMSTORE(PRESERVE) 64K + SMMSTORE(PRESERVE) 256K RW_LEGACY(CBFS) WP_RO@8M 8M { RO_VPD(PRESERVE) 16K -- To view, visit https://review.coreboot.org/c/coreboot/+/81869?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifd3be9b0757e270d2f106e2fbebf3991e49dec65 Gerrit-Change-Number: 81869 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: mb/google/skyrim: Increase SMMSTORE size to 256K
by Matt DeVillier (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Jason Nien, Martin Roth. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81868?usp=email ) Change subject: mb/google/skyrim: Increase SMMSTORE size to 256K ...................................................................... mb/google/skyrim: Increase SMMSTORE size to 256K Anything below 128K will cause SMMSTORE driver in edk2 to fail, since a minimum of (2) 64K blocks are needed. Increase the size to 256K to match other boards in the tree. TEST=build/boot skyrim (frostflow) with SMMSTORE enabled. Change-Id: I34f9d27c27ab7148dfc530322f741a576c348de7 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/skyrim/chromeos.fmd 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/81868/1 diff --git a/src/mainboard/google/skyrim/chromeos.fmd b/src/mainboard/google/skyrim/chromeos.fmd index 217fa98..afc6ce1 100644 --- a/src/mainboard/google/skyrim/chromeos.fmd +++ b/src/mainboard/google/skyrim/chromeos.fmd @@ -20,7 +20,7 @@ } RW_VPD(PRESERVE) 8K RW_NVRAM(PRESERVE) 20K - SMMSTORE(PRESERVE)@0x630000 64K + SMMSTORE(PRESERVE)@0x630000 256K RW_VBIOS_CACHE 64K RECOVERY_MRC_CACHE(PRESERVE) 120K RW_LEGACY(CBFS) -- To view, visit https://review.coreboot.org/c/coreboot/+/81868?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I34f9d27c27ab7148dfc530322f741a576c348de7 Gerrit-Change-Number: 81868 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: mb/google/myst: Increase SMMSTORE size to 256K
by Matt DeVillier (Code Review) 12 Apr '24

12 Apr '24

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81867?usp=email ) Change subject: mb/google/myst: Increase SMMSTORE size to 256K ...................................................................... mb/google/myst: Increase SMMSTORE size to 256K Anything below 128K will cause SMMSTORE driver in edk2 to fail, since a minimum of (2) 64K blocks are needed. Increase the size to 256K to match other boards in the tree. Change-Id: Ic45324b8c5bbd205e889e934c9d5dd17f7775152 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/myst/chromeos.fmd 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/81867/1 diff --git a/src/mainboard/google/myst/chromeos.fmd b/src/mainboard/google/myst/chromeos.fmd index f57a883..2bfa260 100644 --- a/src/mainboard/google/myst/chromeos.fmd +++ b/src/mainboard/google/myst/chromeos.fmd @@ -30,7 +30,7 @@ } RW_VPD(PRESERVE) 8K RW_NVRAM(PRESERVE) 20K - SMMSTORE(PRESERVE) 64K + SMMSTORE(PRESERVE) 256K RW_LEGACY(CBFS) RW_VBIOS_CACHE 64K RW_MRC_CACHE 256K -- To view, visit https://review.coreboot.org/c/coreboot/+/81867?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic45324b8c5bbd205e889e934c9d5dd17f7775152 Gerrit-Change-Number: 81867 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: mb/google/guybrush: Increase SMMSTORE size to 256K
by Matt DeVillier (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Jason Nien, Martin Roth. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81866?usp=email ) Change subject: mb/google/guybrush: Increase SMMSTORE size to 256K ...................................................................... mb/google/guybrush: Increase SMMSTORE size to 256K Anything below 128K will cause SMMSTORE driver in edk2 to fail, since a minimum of (2) 64K blocks are needed. Increase the size to 256K to match other boards in the tree. TEST=build/boot guybrush (dewatt) with SMMSTORE enabled. Change-Id: Ic4fdacd493d83fa3c1683a06d1276b0190f6db8b Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/guybrush/chromeos.fmd 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/81866/1 diff --git a/src/mainboard/google/guybrush/chromeos.fmd b/src/mainboard/google/guybrush/chromeos.fmd index 225fe2a..c4c90a1 100644 --- a/src/mainboard/google/guybrush/chromeos.fmd +++ b/src/mainboard/google/guybrush/chromeos.fmd @@ -18,7 +18,7 @@ } RW_VPD(PRESERVE) 8K RW_NVRAM(PRESERVE) 20K - SMMSTORE(PRESERVE)@0x620000 64K + SMMSTORE(PRESERVE)@0x620000 256K RW_LEGACY(CBFS) WP_RO@8M 8M { RO_VPD(PRESERVE) 16K -- To view, visit https://review.coreboot.org/c/coreboot/+/81866?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4fdacd493d83fa3c1683a06d1276b0190f6db8b Gerrit-Change-Number: 81866 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: mb/amd/*: Increase SMMSTORE size to 256K
by Matt DeVillier (Code Review) 12 Apr '24

12 Apr '24

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81865?usp=email ) Change subject: mb/amd/*: Increase SMMSTORE size to 256K ...................................................................... mb/amd/*: Increase SMMSTORE size to 256K Anything below 128K will cause SMMSTORE driver in edk2 to fail, since a minimum of (2) 64K blocks are needed. Increase the size to 256K to match other boards in the tree. Change-Id: I04d57ff7f74d79118652cfe227cf223375df6472 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/amd/birman/chromeos_glinda.fmd M src/mainboard/amd/birman/chromeos_phoenix.fmd M src/mainboard/amd/birman_plus/chromeos_glinda.fmd M src/mainboard/amd/birman_plus/chromeos_phoenix.fmd M src/mainboard/amd/chausie/chromeos.fmd M src/mainboard/amd/majolica/chromeos.fmd M src/mainboard/amd/mayan/chromeos.fmd 7 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/81865/1 diff --git a/src/mainboard/amd/birman/chromeos_glinda.fmd b/src/mainboard/amd/birman/chromeos_glinda.fmd index 843a026..66227c2 100644 --- a/src/mainboard/amd/birman/chromeos_glinda.fmd +++ b/src/mainboard/amd/birman/chromeos_glinda.fmd @@ -27,7 +27,7 @@ } RW_VPD(PRESERVE) 8K RW_NVRAM(PRESERVE) 20K - SMMSTORE(PRESERVE) 64K + SMMSTORE(PRESERVE) 256K RW_LEGACY(CBFS) EC_BODY@15872K 256K RW_MRC_CACHE(PRESERVE) 120K diff --git a/src/mainboard/amd/birman/chromeos_phoenix.fmd b/src/mainboard/amd/birman/chromeos_phoenix.fmd index 9d6d402..420ed6e 100644 --- a/src/mainboard/amd/birman/chromeos_phoenix.fmd +++ b/src/mainboard/amd/birman/chromeos_phoenix.fmd @@ -27,7 +27,7 @@ } RW_VPD(PRESERVE) 8K RW_NVRAM(PRESERVE) 20K - SMMSTORE(PRESERVE) 64K + SMMSTORE(PRESERVE) 256K RW_LEGACY(CBFS) EC_BODY@15872K 256K RW_MRC_CACHE(PRESERVE) 256K diff --git a/src/mainboard/amd/birman_plus/chromeos_glinda.fmd b/src/mainboard/amd/birman_plus/chromeos_glinda.fmd index 843a026..66227c2 100644 --- a/src/mainboard/amd/birman_plus/chromeos_glinda.fmd +++ b/src/mainboard/amd/birman_plus/chromeos_glinda.fmd @@ -27,7 +27,7 @@ } RW_VPD(PRESERVE) 8K RW_NVRAM(PRESERVE) 20K - SMMSTORE(PRESERVE) 64K + SMMSTORE(PRESERVE) 256K RW_LEGACY(CBFS) EC_BODY@15872K 256K RW_MRC_CACHE(PRESERVE) 120K diff --git a/src/mainboard/amd/birman_plus/chromeos_phoenix.fmd b/src/mainboard/amd/birman_plus/chromeos_phoenix.fmd index 9d6d402..420ed6e 100644 --- a/src/mainboard/amd/birman_plus/chromeos_phoenix.fmd +++ b/src/mainboard/amd/birman_plus/chromeos_phoenix.fmd @@ -27,7 +27,7 @@ } RW_VPD(PRESERVE) 8K RW_NVRAM(PRESERVE) 20K - SMMSTORE(PRESERVE) 64K + SMMSTORE(PRESERVE) 256K RW_LEGACY(CBFS) EC_BODY@15872K 256K RW_MRC_CACHE(PRESERVE) 256K diff --git a/src/mainboard/amd/chausie/chromeos.fmd b/src/mainboard/amd/chausie/chromeos.fmd index a27d5c3..c0e02dd 100644 --- a/src/mainboard/amd/chausie/chromeos.fmd +++ b/src/mainboard/amd/chausie/chromeos.fmd @@ -19,7 +19,7 @@ } RW_VPD(PRESERVE) 8K RW_NVRAM(PRESERVE) 20K - SMMSTORE(PRESERVE) 4K + SMMSTORE(PRESERVE) 256K RW_LEGACY(CBFS) WP_RO@10M 6M { RO_VPD(PRESERVE) 16K diff --git a/src/mainboard/amd/majolica/chromeos.fmd b/src/mainboard/amd/majolica/chromeos.fmd index bb21767..1a1d96b 100644 --- a/src/mainboard/amd/majolica/chromeos.fmd +++ b/src/mainboard/amd/majolica/chromeos.fmd @@ -19,7 +19,7 @@ } RW_VPD(PRESERVE) 8K RW_NVRAM(PRESERVE) 20K - SMMSTORE(PRESERVE) 4K + SMMSTORE(PRESERVE) 256K RW_LEGACY(CBFS) WP_RO@8M 8M { RO_VPD(PRESERVE) 16K diff --git a/src/mainboard/amd/mayan/chromeos.fmd b/src/mainboard/amd/mayan/chromeos.fmd index dca61fc..b70d561 100644 --- a/src/mainboard/amd/mayan/chromeos.fmd +++ b/src/mainboard/amd/mayan/chromeos.fmd @@ -27,7 +27,7 @@ } RW_VPD(PRESERVE) 8K RW_NVRAM(PRESERVE) 20K - SMMSTORE(PRESERVE) 64K + SMMSTORE(PRESERVE) 256K RW_LEGACY(CBFS) RW_MRC_CACHE(PRESERVE) 256K } -- To view, visit https://review.coreboot.org/c/coreboot/+/81865?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I04d57ff7f74d79118652cfe227cf223375df6472 Gerrit-Change-Number: 81865 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: mb/google/brox: Create greenbayupoc variant
by Shelley Chen (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Eren Peng, Ivan Chen, Sumeet R Pawnikar. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81565?usp=email ) Change subject: mb/google/brox: Create greenbayupoc variant ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81565?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I90936d97b41e59c49dd92997146caf580bce1f4f Gerrit-Change-Number: 81565 Gerrit-PatchSet: 5 Gerrit-Owner: Eren Peng <peng.eren(a)inventec.corp-partner.google.com> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Garen Wu <wu.garen(a)inventec.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <hsueh.rasheed(a)inventec.corp-partner.google.com> Gerrit-CC: Steven Yeh <yeh.stevenct(a)inventec.corp-partner.google.com> Gerrit-Attention: Eren Peng <peng.eren(a)inventec.corp-partner.google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Ivan Chen <yulunchen(a)google.com> Gerrit-Comment-Date: Fri, 12 Apr 2024 20:05:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: acpigen_ps2_keybd: Add support for dictation key
by Nick Vaccaro (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Aseda Aboagye, Cliff Huang, Lance Zhao, Tim Wawrzynczak. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81863?usp=email ) Change subject: acpigen_ps2_keybd: Add support for dictation key ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81863?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iabc56662a9d6b29e84ab81ed93cb46d2e8372de9 Gerrit-Change-Number: 81863 Gerrit-PatchSet: 1 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Comment-Date: Fri, 12 Apr 2024 19:37:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: cpu/x86: Link page tables in stage if possible
by Subrata Banik (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Arthur Heymans. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80337?usp=email ) Change subject: cpu/x86: Link page tables in stage if possible ...................................................................... Patch Set 22: (1 comment) Patchset: PS22: > > > > > Thankyou @arthur. Above mentioned patch was not part of the build as it is not yet mirrored to the chromium repo. Tried adding it still failed. Then added a fixed number as suggested then it is building. https://review.coreboot.org/c/coreboot/+/81680 > > > > > > > > we have filled an internal bug as well b/332445618 to follow on the fix. > > > > > > HI Arthur, > > > > > > I am reaching out to you today to inquire about the possibility of finding a solution to the section region overlapping issue without having to update the linker version. > > > > > > Do you have any suggestions for a similar or better solution? > > > > > > https://review.coreboot.org/c/coreboot/+/81680/1/src/arch/x86/bootblock.ld > > > > > > Our current efforts have been stymied by a cyclical dependency between updating the binutil from 2.37 to 2.4x within the chromium code repo. The most recent version of binutil is causing FSP build regressions in 32-bit mode. Unless the Intel/EDK2 team can debug and resolve this issue, we may not be able to update the linker. As a result, we will continue to experience the section overlapping issue. Please let me know your thoughts on this matter. > > > > > > We are working to update the linker within the chromium build, and once that has been completed, we can revert the proposed W/A CL. However, until then, we must find a solution in order to make progress. > > > > Add a Kconfig for a workaround that adds a fixed number to PROGRAM_SZ that makes all your builds succeed? > > Thanks Arthur for prompt response. > > Let me submit the CL. Hello Arthur, As discussed in our last conversation, I had planned to push a kconfig change to make extra space available for PROGRAM_SZ (between .text and .data). However, after cherry-picking CB:80346 and CB:81434 into the chromium repository, I am unable to replicate the overlap issue. Therefore, I will refrain from pushing any changes and keep an eye on this. As it stands, we are in good shape as long as CB:80346 and CB:81434 are landed in mainline. -- To view, visit https://review.coreboot.org/c/coreboot/+/80337?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562 Gerrit-Change-Number: 80337 Gerrit-PatchSet: 22 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 12 Apr 2024 19:04:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Appukuttan V K <appukuttan.vk(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: nb/intel/sandybridge/raminit: Add tCPDED corner case
by Felix Held (Code Review) 12 Apr '24

12 Apr '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79762?usp=email ) Change subject: nb/intel/sandybridge/raminit: Add tCPDED corner case ...................................................................... nb/intel/sandybridge/raminit: Add tCPDED corner case tCPDED is always 1, except for steppings earlier than Sandy Bridge D0. Reduces the differences to MRC.bin. Tested on Lenovo X220: Still boots and runs fine. Change-Id: I5294173c02f06c601fdb13ed785ee33d7a4e3eca Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79762 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 5 insertions(+), 2 deletions(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index fea3ca4..51d6786 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -171,7 +171,7 @@ .tXPDLL = MIN(ctrl->tXPDLL, 31), .tXP = MIN(ctrl->tXP, 7), .tAONPD = ctrl->tAONPD, - .tCPDED = 2, + .tCPDED = 1, .tPRPDEN = 1, }; @@ -2816,7 +2816,10 @@ union tc_othp_reg tc_othp = { .raw = mchbar_read32(TC_OTHP_ch(channel)), }; - tc_othp.tCPDED = 1; + if (IS_SANDY_CPU(ctrl->cpu) && (ctrl->cpu & 0xf) < SNB_STEP_D0) + tc_othp.tCPDED = 2; + else + tc_othp.tCPDED = 1; mchbar_write32(TC_OTHP_ch(channel), tc_othp.raw); /* 64 DCLKs until idle, decision per rank */ -- To view, visit https://review.coreboot.org/c/coreboot/+/79762?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5294173c02f06c601fdb13ed785ee33d7a4e3eca Gerrit-Change-Number: 79762 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2024