coreboot-gerrit April 2024

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[XL] Change in coreboot[main]: soc/intel/lnl/acpi: Add SoC ACPI directory for Lunar Lake
by Saurabh Mishra (Code Review) 12 Apr '24

12 Apr '24

Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81873?usp=email ) Change subject: soc/intel/lnl/acpi: Add SoC ACPI directory for Lunar Lake ...................................................................... soc/intel/lnl/acpi: Add SoC ACPI directory for Lunar Lake List of changes: 1. Select common ACPI Kconfig to include common ACPI code block from IA-common code 2. Select ACPI Kconfig support for wake up from sleep states. Change-Id: If0f538650fe3d0e8cf062f5545bbce0264be99b2 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- A src/soc/intel/lnl_dev/acpi/camera_clock_ctl.asl A src/soc/intel/lnl_dev/acpi/dptf.asl A src/soc/intel/lnl_dev/acpi/gpio.asl A src/soc/intel/lnl_dev/acpi/pch_hda.asl A src/soc/intel/lnl_dev/acpi/pci_irqs.asl A src/soc/intel/lnl_dev/acpi/pcie.asl A src/soc/intel/lnl_dev/acpi/serialio.asl A src/soc/intel/lnl_dev/acpi/southbridge.asl A src/soc/intel/lnl_dev/acpi/tcss.asl A src/soc/intel/lnl_dev/acpi/tcss_dma.asl A src/soc/intel/lnl_dev/acpi/tcss_pcierp.asl A src/soc/intel/lnl_dev/acpi/tcss_xhci.asl A src/soc/intel/lnl_dev/acpi/ufs.asl A src/soc/intel/lnl_dev/acpi/xhci.asl 14 files changed, 3,109 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/81873/1 diff --git a/src/soc/intel/lnl_dev/acpi/camera_clock_ctl.asl b/src/soc/intel/lnl_dev/acpi/camera_clock_ctl.asl new file mode 100644 index 0000000..aded020 --- /dev/null +++ b/src/soc/intel/lnl_dev/acpi/camera_clock_ctl.asl @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define R_ICLK_PCR_CAMERA1 0x8000 +#define B_ICLK_PCR_FREQUENCY 0x1 +#define B_ICLK_PCR_REQUEST 0x2 + +/* The clock control registers for each IMGCLK are offset by 0xC */ +#define B_ICLK_PCR_OFFSET 0xC + +Scope (\_SB.PCI0) { + + /* IsCLK PCH base register for clock settings */ + Name (ICKB, 0) + ICKB = PCRB (PID_ISCLK) + R_ICLK_PCR_CAMERA1 + /* + * Helper function for Read And Or Write + * Arg0 : Clock source select + * Arg1 : And data + * Arg2 : Or data + */ + Method (RAOW, 3, Serialized) + { + OperationRegion (ICLK, SystemMemory, (ICKB + (Arg0 * B_ICLK_PCR_OFFSET)), 4) + Field (ICLK, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Local0 = VAL0 + VAL0 = Local0 & Arg1 | Arg2 + } + + /* + * Clock control Method + * Arg0: Clock source select (0 .. 5 => IMGCLKOUT_0 .. IMGCLKOUT_5) + * Arg1: Frequency select (0: 24MHz, 1: 19.2MHz) + */ + Method (MCON, 0x2, NotSerialized) + { + /* Set Clock Frequency */ + RAOW (Arg0, ~B_ICLK_PCR_FREQUENCY, Arg1) + + /* Enable Clock */ + RAOW (Arg0, ~B_ICLK_PCR_REQUEST, B_ICLK_PCR_REQUEST) + } + + Method (MCOF, 0x1, NotSerialized) + { + /* Disable Clock */ + RAOW (Arg0, ~B_ICLK_PCR_REQUEST, 0) + } +} diff --git a/src/soc/intel/lnl_dev/acpi/dptf.asl b/src/soc/intel/lnl_dev/acpi/dptf.asl new file mode 100644 index 0000000..d9aab16 --- /dev/null +++ b/src/soc/intel/lnl_dev/acpi/dptf.asl @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Below are the unique ACPI Device IDs for thermal/dptf on SoC. */ +/* DPTF ACPI Device ID */ +#define DPTF_DPTF_DEVICE "INTC1041" +/* Generic ACPI Device ID for TSR0/1/2/3 and charger */ +#define DPTF_GEN_DEVICE "INTC1046" +/* Fan ACPI Device ID */ +#define DPTF_FAN_DEVICE "INTC1048" diff --git a/src/soc/intel/lnl_dev/acpi/gpio.asl b/src/soc/intel/lnl_dev/acpi/gpio.asl new file mode 100644 index 0000000..7e0e957 --- /dev/null +++ b/src/soc/intel/lnl_dev/acpi/gpio.asl @@ -0,0 +1,960 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <soc/gpio_defs.h> +#include <soc/intel/common/acpi/gpio.asl> +#include <soc/intel/common/block/acpi/acpi/gpio_op.asl> +#include <soc/irq.h> +#include <soc/pcr_ids.h> + +Device (GPI0) +{ + Name (_HID, CROS_GPIO_NAME) + Name (_CID, "INTC105F") + Name (_UID, 0) + Name (_DDN, "GPIO Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM0) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) + BAS0 = ^^PCRB (PID_GPIOCOM0) + LEN0 = GPIO_BASE_SIZE + Return (RBUF) + } + + Name (_DSD, Package (0x04) // _DSD: Device-Specific Data + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, + Package (0x09) + { + Package (0x02) + { + "intc-gpio-sw-revision", + 0x00010000 + }, + + Package (0x02) + { + "intc-gpio-community-name", + "Community0" + }, + + Package (0x02) + { + "intc-gpio-group-count", + 0x02 + }, + + Package (0x02) + { + "intc-gpio-group-stride", + 0x10 + }, + + Package (0x02) + { + "intc-gpio-pad-ownership-offset", + 0xD0 + }, + + Package (0x02) + { + "intc-gpio-pad-configuration-lock-offset", + 0x0110 + }, + + Package (0x02) + { + "intc-gpio-host-software-pad-ownership-offset", + 0x0130 + }, + + Package (0x02) + { + "intc-gpio-gpi-interrupt-status-offset", + 0x0200 + }, + + Package (0x02) + { + "intc-gpio-gpi-interrupt-enable-offset", + 0x0210 + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x02) + { + Package (0x02) + { + "intc-gpio-group-0-subproperties", + GPPV + }, + + Package (0x02) + { + "intc-gpio-group-1-subproperties", + GPPC + } + } + }) + + Name (GPPV, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-name", + "GPP_V" + }, + + Package (0x02) + { + "intc-gpio-pad-count", + 0x18 + }, + + Package (0x02) + { + "intc-gpio-group-offset", + 0x0600 + } + } + }) + + Name (GPPC, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-name", + "GPP_C" + }, + + Package (0x02) + { + "intc-gpio-pad-count", + 0x18 + }, + + Package (0x02) + { + "intc-gpio-group-offset", + 0x0780 + } + } + }) + + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } +} + +Device (GPI1) +{ + Name (_HID, CROS_GPIO_NAME) + Name (_CID, "INTC105F") + Name (_UID, 0x1) + Name (_DDN, "GPIO Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM1) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM1._BAS, BAS0) + CreateDWordField (^RBUF, ^COM1._LEN, LEN0) + BAS0 = ^^PCRB (PID_GPIOCOM1) + LEN0 = GPIO_BASE_SIZE + Return (RBUF) + } + + Name (_DSD, Package (0x04) // _DSD: Device-Specific Data + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, + Package (0x09) + { + Package (0x02) + { + "intc-gpio-sw-revision", + 0x00010000 + }, + + Package (0x02) + { + "intc-gpio-community-name", + "Community1" + }, + + Package (0x02) + { + "intc-gpio-group-count", + 0x03 + }, + + Package (0x02) + { + "intc-gpio-group-stride", + 0x10 + }, + + Package (0x02) + { + "intc-gpio-pad-ownership-offset", + 0xD0 + }, + + Package (0x02) + { + "intc-gpio-pad-configuration-lock-offset", + 0x0110 + }, + + Package (0x02) + { + "intc-gpio-host-software-pad-ownership-offset", + 0x0130 + }, + + Package (0x02) + { + "intc-gpio-gpi-interrupt-status-offset", + 0x0200 + }, + + Package (0x02) + { + "intc-gpio-gpi-interrupt-enable-offset", + 0x0210 + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-0-subproperties", + GPPF + }, + + Package (0x02) + { + "intc-gpio-group-1-subproperties", + GPPE + }, + + Package (0x02) + { + "intc-gpio-group-2-subproperties", + JTAG + } + } + }) + Name (GPPF, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-name", + "GPP_F" + }, + + Package (0x02) + { + "intc-gpio-pad-count", + 0x1A + }, + + Package (0x02) + { + "intc-gpio-group-offset", + 0x0600 + } + } + }) + Name (GPPE, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-name", + "GPP_E" + }, + + Package (0x02) + { + "intc-gpio-pad-count", + 0x19 + }, + + Package (0x02) + { + "intc-gpio-group-offset", + 0x07A0 + } + } + }) + Name (JTAG, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-name", + "CPUJTAG" + }, + + Package (0x02) + { + "intc-gpio-pad-count", + 0x0E + }, + + Package (0x02) + { + "intc-gpio-group-offset", + 0x0930 + } + } + }) + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } +} + +Device (GPI3) +{ + Name (_HID, CROS_GPIO_NAME) + Name (_CID, "INTC105F") + Name (_UID, 0x3) + Name (_DDN, "GPIO Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM3) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM3._BAS, BAS0) + CreateDWordField (^RBUF, ^COM3._LEN, LEN0) + BAS0 = ^^PCRB (PID_GPIOCOM3) + LEN0 = GPIO_BASE_SIZE + Return (RBUF) + } + + Name (_DSD, Package (0x04) // _DSD: Device-Specific Data + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, + Package (0x09) + { + Package (0x02) + { + "intc-gpio-sw-revision", + 0x00010000 + }, + + Package (0x02) + { + "intc-gpio-community-name", + "Community3" + }, + + Package (0x02) + { + "intc-gpio-group-count", + 0x03 + }, + + Package (0x02) + { + "intc-gpio-group-stride", + 0x10 + }, + + Package (0x02) + { + "intc-gpio-pad-ownership-offset", + 0xD0 + }, + + Package (0x02) + { + "intc-gpio-pad-configuration-lock-offset", + 0x0110 + }, + + Package (0x02) + { + "intc-gpio-host-software-pad-ownership-offset", + 0x0130 + }, + + Package (0x02) + { + "intc-gpio-gpi-interrupt-status-offset", + 0x0200 + }, + + Package (0x02) + { + "intc-gpio-gpi-interrupt-enable-offset", + 0x0210 + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-0-subproperties", + SPI0 + }, + + Package (0x02) + { + "intc-gpio-group-1-subproperties", + GPPH + }, + + Package (0x02) + { + "intc-gpio-group-2-subproperties", + PIO3 + } + } + }) + Name (SPI0, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-name", + "GPPASPI0" + }, + + Package (0x02) + { + "intc-gpio-pad-count", + 0x1A + }, + + Package (0x02) + { + "intc-gpio-group-offset", + 0x0600 + } + } + }) + Name (GPPH, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-name", + "GPP_H" + }, + + Package (0x02) + { + "intc-gpio-pad-count", + 0x1A + }, + + Package (0x02) + { + "intc-gpio-group-offset", + 0x07A0 + } + } + }) + Name (PIO3, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-name", + "vGPIO_3" + }, + + Package (0x02) + { + "intc-gpio-pad-count", + 0x0E + }, + + Package (0x02) + { + "intc-gpio-group-offset", + 0x0940 + } + } + }) + + + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } +} + +Device (GPI4) +{ + Name (_HID, CROS_GPIO_NAME) + Name (_CID, "INTC105F") + Name (_UID, 0x4) + Name (_DDN, "GPIO Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM4) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM4._BAS, BAS0) + CreateDWordField (^RBUF, ^COM4._LEN, LEN0) + BAS0 = ^^PCRB (PID_GPIOCOM4) + LEN0 = GPIO_BASE_SIZE + Return (RBUF) + } + + Name (_DSD, Package (0x04) // _DSD: Device-Specific Data + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, + Package (0x09) + { + Package (0x02) + { + "intc-gpio-sw-revision", + 0x00010000 + }, + + Package (0x02) + { + "intc-gpio-community-name", + "Community4" + }, + + Package (0x02) + { + "intc-gpio-group-count", + One + }, + + Package (0x02) + { + "intc-gpio-group-stride", + 0x10 + }, + + Package (0x02) + { + "intc-gpio-pad-ownership-offset", + 0xD0 + }, + + Package (0x02) + { + "intc-gpio-pad-configuration-lock-offset", + 0x0110 + }, + + Package (0x02) + { + "intc-gpio-host-software-pad-ownership-offset", + 0x0130 + }, + + Package (0x02) + { + "intc-gpio-gpi-interrupt-status-offset", + 0x0200 + }, + + Package (0x02) + { + "intc-gpio-gpi-interrupt-enable-offset", + 0x0210 + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "intc-gpio-group-0-subproperties", + GPPS + } + } + }) + Name (GPPS, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-name", + "GPP_S" + }, + + Package (0x02) + { + "intc-gpio-pad-count", + 0x08 + }, + + Package (0x02) + { + "intc-gpio-group-offset", + 0x0600 + } + } + }) + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } +} + +Device (GPI5) +{ + Name (_HID, CROS_GPIO_NAME) + Name (_CID, "INTC105F") + Name (_UID, 0x5) + Name (_DDN, "GPIO Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM5) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM5._BAS, BAS0) + CreateDWordField (^RBUF, ^COM5._LEN, LEN0) + BAS0 = ^^PCRB (PID_GPIOCOM5) + LEN0 = GPIO_BASE_SIZE + Return (RBUF) + } + + Name (_DSD, Package (0x04) // _DSD: Device-Specific Data + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, + Package (0x09) + { + Package (0x02) + { + "intc-gpio-sw-revision", + 0x00010000 + }, + + Package (0x02) + { + "intc-gpio-community-name", + "Community5" + }, + + Package (0x02) + { + "intc-gpio-group-count", + 0x03 + }, + + Package (0x02) + { + "intc-gpio-group-stride", + 0x10 + }, + + Package (0x02) + { + "intc-gpio-pad-ownership-offset", + 0xD0 + }, + + Package (0x02) + { + "intc-gpio-pad-configuration-lock-offset", + 0x0110 + }, + + Package (0x02) + { + "intc-gpio-host-software-pad-ownership-offset", + 0x0130 + }, + + Package (0x02) + { + "intc-gpio-gpi-interrupt-status-offset", + 0x0200 + }, + + Package (0x02) + { + "intc-gpio-gpi-interrupt-enable-offset", + 0x0210 + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-0-subproperties", + GPPB + }, + + Package (0x02) + { + "intc-gpio-group-1-subproperties", + GPPD + }, + + Package (0x02) + { + "intc-gpio-group-2-subproperties", + GPIO + } + } + }) + Name (GPPB, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-name", + "GPP_B" + }, + + Package (0x02) + { + "intc-gpio-pad-count", + 0x19 + }, + + Package (0x02) + { + "intc-gpio-group-offset", + 0x0600 + } + } + }) + Name (GPPD, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-name", + "GPP_D" + }, + + Package (0x02) + { + "intc-gpio-pad-count", + 0x18 + }, + + Package (0x02) + { + "intc-gpio-group-offset", + 0x0790 + } + } + }) + Name (GPIO, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-name", + "vGPIO" + }, + + Package (0x02) + { + "intc-gpio-pad-count", + 0x12 + }, + + Package (0x02) + { + "intc-gpio-group-offset", + 0x0910 + } + } + }) + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } +} + +/* + * Get GPIO DW0 Address + * Arg0 - GPIO Number + */ +Method (GADD, 1, NotSerialized) +{ + /* GPIO Community 0 */ + If (Arg0 >= GPIO_COM0_START && Arg0 <= GPIO_COM0_END) + { + Local0 = PID_GPIOCOM0 + Local1 = Arg0 - GPIO_COM0_START + } + /* GPIO Community 1 */ + If (Arg0 >= GPIO_COM1_START && Arg0 <= GPIO_COM1_END) + { + Local0 = PID_GPIOCOM1 + Local1 = Arg0 - GPIO_COM1_START + } + /* GPIO Community 3 */ + If (Arg0 >= GPIO_COM3_START && Arg0 <= GPIO_COM3_END) + { + Local0 = PID_GPIOCOM3 + Local1 = Arg0 - GPIO_COM3_START + } + /* GPIO Community 4 */ + If (Arg0 >= GPIO_COM4_START && Arg0 <= GPIO_COM4_END) + { + Local0 = PID_GPIOCOM4 + Local1 = Arg0 - GPIO_COM4_START + } + /* GPIO Community 5*/ + If (Arg0 >= GPIO_COM5_START && Arg0 <= GPIO_COM5_END) + { + Local0 = PID_GPIOCOM5 + Local1 = Arg0 - GPIO_COM5_START + } + + Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16) + Return (Local2) +} + +/* + * Return PCR Port ID of GPIO Communities + * + * Arg0: GPIO Community (0-5) + */ +Method (GPID, 1, Serialized) +{ + Switch (ToInteger (Arg0)) + { + Case (COMM_0) { + Local0 = PID_GPIOCOM0 + } + Case (COMM_1) { + Local0 = PID_GPIOCOM1 + } + Case (COMM_3) { + Local0 = PID_GPIOCOM3 + } + Case (COMM_4) { + Local0 = PID_GPIOCOM4 + } + Case (COMM_5) { + Local0 = PID_GPIOCOM5 + } + Default { + Return (0) + } + } + + Return (Local0) +} + +/* GPIO Power Management bits */ +Name(GPMB, Package(TOTAL_GPIO_COMM) {0, 0, 0, 0, 0}) + +/* + * Save GPIO Power Management bits + */ +Method (SGPM, 0, Serialized) +{ + For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++) + { + Local1 = GPID (Local0) + GPMB[Local0] = PCRR (Local1, GPIO_MISCCFG) + } +} + +/* + * Restore GPIO Power Management bits + */ +Method (RGPM, 0, Serialized) +{ + For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++) + { + CGPM (Local0, DerefOf(GPMB[Local0])) + } +} + +/* + * Save current setting of GPIO Power Management bits and + * enable all Power Management bits for all communities + */ +Method (EGPM, 0, Serialized) +{ + /* Save current setting and will restore it when resuming */ + SGPM () + /* Enable PM bits */ + For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++) + { + CGPM (Local0, MISCCFG_GPIO_PM_CONFIG_BITS) + } +} diff --git a/src/soc/intel/lnl_dev/acpi/pch_hda.asl b/src/soc/intel/lnl_dev/acpi/pch_hda.asl new file mode 100644 index 0000000..13b4d3d --- /dev/null +++ b/src/soc/intel/lnl_dev/acpi/pch_hda.asl @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Audio Controller - Device 31, Function 3 */ + +Device (HDAS) +{ + Name (_ADR, 0x001f0003) + Name (_DDN, "Audio Controller") + Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553")) + + /* Device is D3 wake capable */ + Name (_S0W, 3) + + /* NHLT Table Address populated from GNVS values */ + Name (NBUF, ResourceTemplate () { + QWordMemory (ResourceConsumer, PosDecode, MinFixed, + MaxFixed, NonCacheable, ReadOnly, + 0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI) + }) + + /* + * Device Specific Method + * Arg0 - UUID + * Arg1 - Revision + * Arg2 - Function Index + */ + Method (_DSM, 4) + { + If (Arg0 == ^UUID) { + /* + * Function 0: Function Support Query + * Returns a bitmask of functions supported. + */ + If (Arg2 == 0) { + /* + * NHLT Query only supported for revision 1 and + * if NHLT address and length are set in NVS. + */ + If ((Arg1 == 1) && (NHLA != 0) && (NHLL != 0)) { + Return (Buffer (One) { 0x03 }) + } Else { + Return (Buffer (One) { 0x01 }) + } + } + + /* + * Function 1: Query NHLT memory address used by + * Intel Offload Engine Driver to discover any non-HDA + * devices that are supported by the DSP. + * + * Returns a pointer to NHLT table in memory. + */ + If (Arg2 == 1) { + CreateQWordField (NBUF, ^NHLT._MIN, NBAS) + CreateQWordField (NBUF, ^NHLT._MAX, NMAS) + CreateQWordField (NBUF, ^NHLT._LEN, NLEN) + + NBAS = NHLA + NMAS = NHLA + NLEN = NHLL + + Return (NBUF) + } + } + + Return (Buffer (One) { 0x00 }) + } +} diff --git a/src/soc/intel/lnl_dev/acpi/pci_irqs.asl b/src/soc/intel/lnl_dev/acpi/pci_irqs.asl new file mode 100644 index 0000000..6740555 --- /dev/null +++ b/src/soc/intel/lnl_dev/acpi/pci_irqs.asl @@ -0,0 +1,155 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +Name (PICP, Package () { + /* D31 */ + Package(){0x001FFFFF, 0, 0, 16 }, + Package(){0x001FFFFF, 1, 0, 17 }, + Package(){0x001FFFFF, 2, 0, 18 }, + Package(){0x001FFFFF, 3, 0, 19 }, + /* D30 */ + Package(){0x001EFFFF, 0, 0, 16 }, + Package(){0x001EFFFF, 1, 0, 17 }, + Package(){0x001EFFFF, 2, 0, 27 }, + Package(){0x001EFFFF, 3, 0, 28 },, + /* D28 */ + Package(){0x001CFFFF, 0, 0, 16 }, + Package(){0x001CFFFF, 1, 0, 17 }, + Package(){0x001CFFFF, 2, 0, 18 }, + Package(){0x001CFFFF, 3, 0, 19 }, + /* D25 */ + Package(){0x0019FFFF, 0, 0, 29 }, + Package(){0x0019FFFF, 1, 0, 30 }, + Package(){0x0019FFFF, 2, 0, 31 }, + /* D23 */ + Package(){0x0017FFFF, 0, 0, 16 }, + /* D22 */ + Package(){0x0016FFFF, 0, 0, 16 }, + Package(){0x0016FFFF, 1, 0, 17 }, + Package(){0x0016FFFF, 2, 0, 18 }, + Package(){0x0016FFFF, 3, 0, 19 }, + /* D21 */ + Package(){0x0015FFFF, 0, 0, 32 }, + Package(){0x0015FFFF, 1, 0, 33 }, + Package(){0x0015FFFF, 2, 0, 34 }, + Package(){0x0015FFFF, 3, 0, 35 }, + /* D20 */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + /* D18 */ + Package(){0x0012FFFF, 0, 0, 26 }, + Package(){0x0012FFFF, 1, 0, 37 }, + Package(){0x0012FFFF, 2, 0, 25 }, + /* D16 */ + Package(){0x0010FFFF, 0, 0, 23 }, + Package(){0x0010FFFF, 1, 0, 22 }, + /* D13 */ + Package(){0x000DFFFF, 0, 0, 16 }, +// Package(){0x000DFFFF, 1, 0, 17 }, + /* D11 */ +// Package(){0x000BFFFF, 0, 0, 16 }, + /* D8 */ +// Package(){0x0008FFFF, 0, 0, 16 }, + /* D7 */ +// Package(){0x0007FFFF, 0, 0, 16 }, +// Package(){0x0007FFFF, 1, 0, 17 }, +// Package(){0x0007FFFF, 2, 0, 18 }, +// Package(){0x0007FFFF, 3, 0, 19 }, + /* D6 */ + Package(){0x0006FFFF, 0, 0, 16 }, + Package(){0x0006FFFF, 1, 0, 17 }, + Package(){0x0006FFFF, 2, 0, 18 }, + Package(){0x0006FFFF, 3, 0, 19 }, + /* D5 */ + Package(){0x0005FFFF, 0, 0, 16 }, + /* D4 */ + Package(){0x0004FFFF, 0, 0, 16 }, + /* D2 */ + Package(){0x0002FFFF, 0, 0, 16 }, + /* D1 */ + Package(){0x0001FFFF, 0, 0, 16 }, + Package(){0x0001FFFF, 1, 0, 17 }, + Package(){0x0001FFFF, 2, 0, 18 }, + Package(){0x0001FFFF, 3, 0, 19 }, +}) + +Name (PICN, Package () { + /* D31 */ + Package(){0x001FFFFF, 0, 0, 11 }, + Package(){0x001FFFFF, 1, 0, 10 }, + Package(){0x001FFFFF, 2, 0, 11 }, + Package(){0x001FFFFF, 3, 0, 11 }, + /* D30 */ + Package(){0x001EFFFF, 0, 0, 11 }, + Package(){0x001EFFFF, 1, 0, 10 }, + Package(){0x001EFFFF, 2, 0, 11 }, + Package(){0x001EFFFF, 3, 0, 11 }, + /* D28 */ + Package(){0x001CFFFF, 0, 0, 11 }, + Package(){0x001CFFFF, 1, 0, 10 }, + Package(){0x001CFFFF, 2, 0, 11 }, + Package(){0x001CFFFF, 3, 0, 11 }, + /* D25 */ + Package(){0x0019FFFF, 0, 0, 11 }, + Package(){0x0019FFFF, 1, 0, 10 }, + Package(){0x0019FFFF, 2, 0, 11 }, + /* D23 */ + Package(){0x0017FFFF, 0, 0, 11 }, + /* D22 */ + Package(){0x0016FFFF, 0, 0, 11 }, + Package(){0x0016FFFF, 1, 0, 10 }, + Package(){0x0016FFFF, 2, 0, 11 }, + Package(){0x0016FFFF, 3, 0, 11 }, + /* D21 */ + Package(){0x0015FFFF, 0, 0, 11 }, + Package(){0x0015FFFF, 1, 0, 10 }, + Package(){0x0015FFFF, 2, 0, 11 }, + Package(){0x0015FFFF, 3, 0, 11 }, + /* D20 */ + Package(){0x0014FFFF, 0, 0, 11 }, + Package(){0x0014FFFF, 1, 0, 10 }, + Package(){0x0014FFFF, 2, 0, 11 }, + /* D18 */ + Package(){0x0012FFFF, 0, 0, 11 }, + Package(){0x0012FFFF, 1, 0, 10 }, + Package(){0x0012FFFF, 2, 0, 11 }, + /* D16 */ + Package(){0x0010FFFF, 0, 0, 11 }, + Package(){0x0010FFFF, 1, 0, 10 }, + /* D13 */ + Package(){0x000DFFFF, 0, 0, 11 }, + /* D11 */ + Package(){0x000BFFFF, 0, 0, 11 }, + /* D8 */ + Package(){0x0008FFFF, 0, 0, 11 }, + /* D7 */ + Package(){0x0007FFFF, 0, 0, 11 }, + Package(){0x0007FFFF, 1, 0, 10 }, + Package(){0x0007FFFF, 2, 0, 11 }, + Package(){0x0007FFFF, 3, 0, 11 }, + /* D6 */ + Package(){0x0006FFFF, 0, 0, 11 }, + Package(){0x0006FFFF, 1, 0, 10 }, + Package(){0x0006FFFF, 2, 0, 11 }, + Package(){0x0006FFFF, 3, 0, 11 }, + /* D5 */ + Package(){0x0005FFFF, 0, 0, 11 }, + /* D4 */ + Package(){0x0004FFFF, 0, 0, 11 }, + /* D2 */ + Package(){0x0002FFFF, 0, 0, 11 }, + /* D1 */ + Package(){0x0001FFFF, 0, 0, 11 }, + Package(){0x0001FFFF, 1, 0, 10 }, + Package(){0x0001FFFF, 2, 0, 11 }, + Package(){0x0001FFFF, 3, 0, 11 }, +}) + +Method (_PRT) +{ + If (PICM) { + Return (^PICP) + } Else { + Return (^PICN) + } +} diff --git a/src/soc/intel/lnl_dev/acpi/pcie.asl b/src/soc/intel/lnl_dev/acpi/pcie.asl new file mode 100644 index 0000000..9cf0911 --- /dev/null +++ b/src/soc/intel/lnl_dev/acpi/pcie.asl @@ -0,0 +1,200 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Intel PCH PCIe support */ + +Method (IRQM, 1, Serialized) { + + /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ + Name (IQAA, Package () { + Package () { 0x0000ffff, 0, 0, 16 }, + Package () { 0x0000ffff, 1, 0, 17 }, + Package () { 0x0000ffff, 2, 0, 18 }, + Package () { 0x0000ffff, 3, 0, 19 } }) + Name (IQAP, Package () { + Package () { 0x0000ffff, 0, 0, 11 }, + Package () { 0x0000ffff, 1, 0, 10 }, + Package () { 0x0000ffff, 2, 0, 11 }, + Package () { 0x0000ffff, 3, 0, 11 } }) + + /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */ + Name (IQBA, Package () { + Package () { 0x0000ffff, 0, 0, 17 }, + Package () { 0x0000ffff, 1, 0, 18 }, + Package () { 0x0000ffff, 2, 0, 19 }, + Package () { 0x0000ffff, 3, 0, 16 } }) + Name (IQBP, Package () { + Package () { 0x0000ffff, 0, 0, 10 }, + Package () { 0x0000ffff, 1, 0, 11 }, + Package () { 0x0000ffff, 2, 0, 11 }, + Package () { 0x0000ffff, 3, 0, 11 } }) + + /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */ + Name (IQCA, Package () { + Package () { 0x0000ffff, 0, 0, 18 }, + Package () { 0x0000ffff, 1, 0, 19 }, + Package () { 0x0000ffff, 2, 0, 16 }, + Package () { 0x0000ffff, 3, 0, 17 } }) + Name (IQCP, Package () { + Package () { 0x0000ffff, 0, 0, 11 }, + Package () { 0x0000ffff, 1, 0, 11 }, + Package () { 0x0000ffff, 2, 0, 11 }, + Package () { 0x0000ffff, 3, 0, 10 } }) + + /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */ + Name (IQDA, Package () { + Package () { 0x0000ffff, 0, 0, 19 }, + Package () { 0x0000ffff, 1, 0, 16 }, + Package () { 0x0000ffff, 2, 0, 17 }, + Package () { 0x0000ffff, 3, 0, 18 } }) + Name (IQDP, Package () { + Package () { 0x0000ffff, 0, 0, 11 }, + Package () { 0x0000ffff, 1, 0, 11 }, + Package () { 0x0000ffff, 2, 0, 10 }, + Package () { 0x0000ffff, 3, 0, 11 } }) + + Switch (ToInteger (Arg0)) + { + Case (Package () { 1, 5, 9, 13 }) { + If (PICM) { + Return (IQAA) + } Else { + Return (IQAP) + } + } + + Case (Package () { 2, 6, 10, 14 }) { + If (PICM) { + Return (IQBA) + } Else { + Return (IQBP) + } + } + + Case (Package () { 3, 7, 11, 15 }) { + If (PICM) { + Return (IQCA) + } Else { + Return (IQCP) + } + } + + Case (Package () { 4, 8, 12, 16 }) { + If (PICM) { + Return (IQDA) + } Else { + Return (IQDP) + } + } + + Default { + If (PICM) { + Return (IQDA) + } Else { + Return (IQDP) + } + } + } +} + +Device (RP01) +{ + Name (_ADR, 0x001C0000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP02) +{ + Name (_ADR, 0x001C0001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP03) +{ + Name (_ADR, 0x001C0002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP04) +{ + Name (_ADR, 0x001C0003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP05) +{ + Name (_ADR, 0x001C0004) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP06) +{ + Name (_ADR, 0x001C0005) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + diff --git a/src/soc/intel/lnl_dev/acpi/serialio.asl b/src/soc/intel/lnl_dev/acpi/serialio.asl new file mode 100644 index 0000000..2404056 --- /dev/null +++ b/src/soc/intel/lnl_dev/acpi/serialio.asl @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Intel Serial IO Devices */ + +Device (I2C0) +{ + Name (_ADR, 0x00150000) + Name (_DDN, "Serial IO I2C Controller 0") +} + +Device (I2C1) +{ + Name (_ADR, 0x00150001) + Name (_DDN, "Serial IO I2C Controller 1") +} + +Device (I2C2) +{ + Name (_ADR, 0x00150002) + Name (_DDN, "Serial IO I2C Controller 2") +} + +Device (I2C3) +{ + Name (_ADR, 0x00150003) + Name (_DDN, "Serial IO I2C Controller 3") +} + +Device (I2C4) +{ + Name (_ADR, 0x00190000) + Name (_DDN, "Serial IO I2C Controller 4") +} + +Device (I2C5) +{ + Name (_ADR, 0x00190001) + Name (_DDN, "Serial IO I2C Controller 5") +} + +Device (FSPI) +{ + Name (_ADR, 0x001f0005) + Name (_DDN, "Fast SPI") +} + +Device (I3C0) +{ + Name (_ADR, 0x00110000) + Name (_DDN, "Serial IO I3C Controller 0") +} + +Device (I3C1) +{ + Name (_ADR, 0x00110002) + Name (_DDN, "Serial IO I3C Controller 1") +} + + +Device (SPI0) +{ + Name (_ADR, 0x001e0002) + Name (_DDN, "Serial IO SPI Controller 0") +} + +Device (SPI1) +{ + Name (_ADR, 0x001e0003) + Name (_DDN, "Serial IO SPI Controller 1") +} + +Device (SPI2) +{ + Name (_ADR, 0x00120006) + Name (_DDN, "Serial IO SPI Controller 2") +} + +Device (UAR0) +{ + Name (_ADR, 0x001e0000) + Name (_DDN, "Serial IO UART Controller 0") +} + +Device (UAR1) +{ + Name (_ADR, 0x001e0001) + Name (_DDN, "Serial IO UART Controller 1") +} + +Device (UAR2) +{ + Name (_ADR, 0x00190002) + Name (_DDN, "Serial IO UART Controller 2") +} diff --git a/src/soc/intel/lnl_dev/acpi/southbridge.asl b/src/soc/intel/lnl_dev/acpi/southbridge.asl new file mode 100644 index 0000000..a8d5e05 --- /dev/null +++ b/src/soc/intel/lnl_dev/acpi/southbridge.asl @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <intelblocks/itss.h> +#include <intelblocks/pcr.h> +#include <soc/itss.h> +#include <soc/pcr_ids.h> + +/* PCR access */ +#include <soc/intel/common/acpi/pch_pcr.asl> + +/* PCH clock */ +#include "camera_clock_ctl.asl" + +/* GPIO controller */ +#include "gpio.asl" + +/* ESPI 0:1f.0 */ +#include <soc/intel/common/block/acpi/acpi/lpc.asl> + +/* PCH HDA */ +#include "pch_hda.asl" + +/* PCIE Ports */ +#include "pcie.asl" + +/* Serial IO */ +#include "serialio.asl" + +/* SMBus 0:1f.4 */ +#include <soc/intel/common/block/acpi/acpi/smbus.asl> + +/* ISH 0:12.0 */ +#if CONFIG(DRIVERS_INTEL_ISH) +//#include <soc/intel/common/block/acpi/acpi/ish.asl> +#endif + +/* USB XHCI 0:14.0 */ +#include "xhci.asl" + +/* PCI _OSC */ +#include <soc/intel/common/acpi/pci_osc.asl> + +/* GbE 0:1f.6 */ +#if CONFIG(MAINBOARD_USES_IFD_GBE_REGION) +#include <soc/intel/common/block/acpi/acpi/pch_glan.asl> + +/* UFS 0:17:0 */ +#include "ufs.asl" +#endif diff --git a/src/soc/intel/lnl_dev/acpi/tcss.asl b/src/soc/intel/lnl_dev/acpi/tcss.asl new file mode 100644 index 0000000..3598808 --- /dev/null +++ b/src/soc/intel/lnl_dev/acpi/tcss.asl @@ -0,0 +1,832 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <intelblocks/tcss.h> +#include <soc/iomap.h> + +/* + * Type C Subsystem(TCSS) topology provides Runtime D3 support for USB host controller(xHCI), + * USB device controller(xDCI), Thunderbolt DMA devices and Thunderbolt PCIe controllers. + * PCIe RP0/RP1 is grouped with DMA0 and PCIe RP2/RP3 is grouped with DMA1. + */ +#define TCSS_TBT_PCIE0_RP0 0 +#define TCSS_TBT_PCIE0_RP1 1 +#define TCSS_TBT_PCIE0_RP2 2 +#define TCSS_TBT_PCIE0_RP3 3 +#define TCSS_XHCI 4 +#define TCSS_XDCI 5 +#define TCSS_DMA0 6 +#define TCSS_DMA1 7 + +/* + * MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE + * Command code 0x15 + * Description: Gateway command for handling TCSS DEVEN clear/restore. + * Field PARAM1[15:8] of the _INTERFACE register is used in this command to select from + * a pre-defined set of subcommands. + */ +#define MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE 0x00000015 +#define TCSS_DEVEN_MAILBOX_SUBCMD_GET_STATUS 0 /* Sub-command 0 */ +#define TCSS_DEVEN_MAILBOX_SUBCMD_TCSS_CHANGE_REQ 1 /* Sub-command 1 */ +#define TCSS_IOM_ACK_TIMEOUT_IN_MS 100 + +#define MCHBAR_TCSS_DEVEN_OFFSET 0x7090 + +#define REVISION_ID 1 +#define UNRECOGNIZED_UUID 0x4 +#define UNRECOGNIZED_REVISION 0x8 + +#define USB_TUNNELING 0x1 +#define DISPLAY_PORT_TUNNELING 0x2 +#define PCIE_TUNNELING 0x4 +#define INTER_DOMAIN_USB4_INTERNET_PROTOCOL 0x8 + +Scope (\_SB) +{ + /* Device base address */ + Method (BASE, 1) + { + Local0 = Arg0 & 0x7 /* Function number */ + Local1 = (Arg0 >> 16) & 0x1F /* Device number */ + Local2 = (Local0 << 12) + (Local1 << 15) + Local3 = \_SB.PCI0.GPCB() + Local2 + Return (Local3) + } + + /* + * Define PCH ACPIBASE IO as an ACPI operating region. The base address can be + * found in Device 31, Function 2, Offset 40h. + */ + OperationRegion (PMIO, SystemIO, ACPI_BASE_ADDRESS, 0x80) + Field (PMIO, ByteAcc, NoLock, Preserve) { + Offset(0x6C), /* 0x6C, General Purpose Event 0 Status [127:96] */ + , 19, + CPWS, 1, /* CPU WAKE STATUS */ + Offset(0x7C), /* 0x7C, General Purpose Event 0 Enable [127:96] */ + , 19, + CPWE, 1 /* CPU WAKE EN */ + } + + Name (C2PW, 0) /* Set default value to 0. */ + + /* + * C2PM (CPU to PCH Method) + * + * This object is Enable/Disable GPE_CPU_WAKE_EN. + * Arguments: (4) + * Arg0 - An Integer containing the device wake capability + * Arg1 - An Integer containing the target system state + * Arg2 - An Integer containing the target device state + * Arg3 - An Integer containing the request device type + * Return Value: + * return 0 + */ + Method (C2PM, 4, NotSerialized) + { + Local0 = 1 << Arg3 + /* This method is used to enable/disable wake from Tcss Device (WKEN). */ + If (Arg0 && Arg1) + { /* If entering Sx and enabling wake, need to enable WAKE capability. */ + If (CPWE == 0) { /* If CPU WAKE EN is not set, Set it. */ + If (CPWS) { /* If CPU WAKE STATUS is set, Clear it. */ + /* Clear CPU WAKE STATUS by writing 1. */ + CPWS = 1 + } + CPWE = 1 /* Set CPU WAKE EN by writing 1. */ + } + If ((C2PW & Local0) == 0) { + /* Set Corresponding Device En BIT in C2PW. */ + C2PW |= Local0 + } + } Else { /* If Staying in S0 or Disabling Wake. */ + If (Arg0 || Arg2) { /* Check if Exiting D0 and arming for wake. */ + /* If CPU WAKE EN is not set, Set it. */ + If (CPWE == 0) { + /* If CPU WAKE STATUS is set, Clear it. */ + If (CPWS) { + /* Clear CPU WAKE STATUS by writing 1. */ + CPWS = 1 + } + CPWE = 1 /* Set CPU WAKE EN by writing 1. */ + } + If ((C2PW & Local0) == 0) { + /* Set Corresponding Device En BIT in C2PW. */ + C2PW |= Local0 + } + } Else { + /* + * Disable runtime PME, either because staying in D0 or + * disabling wake. + */ + If ((C2PW & Local0) != 0) { + /* + * Clear Corresponding Device En BIT in C2PW. + */ + C2PW &= ~Local0 + } + If ((CPWE != 0) && (C2PW == 0)) { + /* + * If CPU WAKE EN is set, Clear it. Clear CPU WAKE EN + * by writing 0. + */ + CPWE = 0 + } + } + } + Return (0) + } + + Method (_OSC, 4, Serialized) + { + CreateDWordField (Arg3, 0, CDW1) + If (Arg0 == ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48")) { + /* Platform-Wide _OSC Capabilities + * Arg0: UUID = {0811B06E-4A27-44F9-8D60-3CBBC22E7B48} + * Arg1: Revision ID = 1 + * Arg2: Count of entries (DWORD) in Arge3 (Integer): 3 + * Arg3: DWORD capabilities buffer: + * First DWORD: The standard definition bits are used to return errors. + * Second DWORD: See ACPI specification Platform-Wide _OSC Capabilities + * DWORD2 table for Bits 0-17. Bit 18 is newly defined as native USB4 + * support. The OS sets this bit to indicate support for an OSPM-native + * USB4 Connection Manager which handles USB4 connection events and + * link management. + */ + If (Arg1 != REVISION_ID) { + CDW1 |= UNRECOGNIZED_REVISION + } + Return (Arg3) +#if CONFIG(SOFTWARE_CONNECTION_MANAGER) + /* + * Software Connection Manager doesn't work with Linux 5.13 or later and + * results in TBT ports timing out. Not advertising this results in + * Firmware Connection Manager being used and TBT works correctly. + */ + } ElseIf (Arg0 == ToUUID("23A0D13A-26AB-486C-9C5F-0FFA525A575A")) { + /* + * Operating System Capabilities for USB4 + * Arg0: UUID = {23A0D13A-26AB-486C-9C5F-0FFA525A575A} + * Arg1: Revision ID = 1 + * Arg2: Count of entries (DWORD) in Arg3 (Integer): 3 + * Arg3: DWORD capabilities buffer: + * First DWORD: The standard definition bits are used to return errors. + * Second DWORD: OSPM support field for USB4, bits [31:0] reserved. + * Third DWORD: OSPM control field for USB4. + * bit 0: USB tunneling + * bit 1: DisplayPort tunneling + * bit 2: PCIe tunneling + * bit 3: Inter-domain USB4 internet protocol + * bit 31:4: reserved + * Return: The platform acknowledges the capabilities buffer by + * returning a buffer of DWORD of the same length. Masked/Cleared bits + * in the control field indicate that the platform does not permit OSPM + * control of the respectively capabilities or features. + */ + CreateDWordField (Arg3, 8, CDW3) + Local0 = CDW3 + + If (Arg1 != REVISION_ID) { + CDW1 |= UNRECOGNIZED_REVISION + Return (Arg3) + } + Local0 |= USB_TUNNELING | DISPLAY_PORT_TUNNELING | PCIE_TUNNELING | + INTER_DOMAIN_USB4_INTERNET_PROTOCOL + CDW3 = Local0 + Return (Arg3) +#endif + } Else { + CDW1 |= UNRECOGNIZED_UUID + Return (Arg3) + } + } +} + +Scope (_GPE) +{ + /* PCI Express Hot-Plug wake event */ + Method (_L61, 0, NotSerialized) + { + /* + * Delay for 100ms to meet the timing requirements of the PCI Express Base + * Specification, Revision 1.0A, Section 6.6 ("...software must wait at least + * 100ms from the end of reset of one or more device before it is permitted + * to issue Configuration Requests to those devices"). + */ + Sleep (100) + + If (CondRefOf (\_SB.PCI0.TXHC)) { + /* Invoke PCIe root ports wake event handler */ + \_SB.PCI0.TRP0.HPEV() + \_SB.PCI0.TRP1.HPEV() + \_SB.PCI0.TRP2.HPEV() + \_SB.PCI0.TRP3.HPEV() + } + + /* Check Root Port 0 for a Hot Plug Event if the port is enabled */ + If (((\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP0.HPSX)) { + If (\_SB.PCI0.TRP0.PDCX) { + /* Clear all status bits */ + \_SB.PCI0.TRP0.PDCX = 1 + \_SB.PCI0.TRP0.HPSX = 1 + /* + * Intercept Presence Detect Changed interrupt and make sure + * the L0s is disabled on empty slots. + */ + If (!\_SB.PCI0.TRP0.PDSX) { + /* + * The PCIe slot is empty, so disable L0s on hot unplug. + */ + \_SB.PCI0.TRP0.L0SE = 0 + } + /* Performs proper notification to the OS. */ + Notify (\_SB.PCI0.TRP0, 0) + } Else { + /* False event. Clear Hot-Plug status, then exit. */ + \_SB.PCI0.TRP0.HPSX = 1 + } + } + + /* Check Root Port 1 for a Hot Plug Event if the port is enabled */ + If (((\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP1.HPSX)) { + If (\_SB.PCI0.TRP1.PDCX) { + \_SB.PCI0.TRP1.PDCX = 1 + \_SB.PCI0.TRP1.HPSX = 1 + If (!\_SB.PCI0.TRP1.PDSX) { + \_SB.PCI0.TRP1.L0SE = 0 + } + Notify (\_SB.PCI0.TRP1, 0) + } Else { + \_SB.PCI0.TRP1.HPSX = 1 + } + } + + /* Check Root Port 2 for a Hot Plug Event if the port is enabled */ + If (((\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP2.HPSX)) { + If (\_SB.PCI0.TRP2.PDCX) { + \_SB.PCI0.TRP2.PDCX = 1 + \_SB.PCI0.TRP2.HPSX = 1 + If (!\_SB.PCI0.TRP2.PDSX) { + \_SB.PCI0.TRP2.L0SE = 0 + } + Notify (\_SB.PCI0.TRP2, 0) + } Else { + \_SB.PCI0.TRP2.HPSX = 1 + } + } + + /* Check Root Port 3 for a Hot Plug Event if the port is enabled */ + If (((\_SB.PCI0.TRP3.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP3.HPSX)) { + If (\_SB.PCI0.TRP3.PDCX) { + \_SB.PCI0.TRP3.PDCX = 1 + \_SB.PCI0.TRP3.HPSX = 1 + If (!\_SB.PCI0.TRP3.PDSX) { + \_SB.PCI0.TRP3.L0SE = 0 + } + Notify (\_SB.PCI0.TRP3, 0) + } Else { + \_SB.PCI0.TRP3.HPSX = 1 + } + } + } + + /* PCI Express power management event */ + Method (_L69, 0, Serialized) + { + If (CondRefOf (\_SB.PCI0.TXHC)) { + If (\_SB.PCI0.TRP0.HPME() == 1) { + Notify (\_SB.PCI0.TDM0, 0x2) + Notify (\_SB.PCI0.TRP0, 0x2) + } + + If (\_SB.PCI0.TRP1.HPME() == 1) { + Notify (\_SB.PCI0.TDM0, 0x2) + Notify (\_SB.PCI0.TRP1, 0x2) + } + + If (\_SB.PCI0.TRP2.HPME() == 1) { + Notify (\_SB.PCI0.TDM1, 0x2) + Notify (\_SB.PCI0.TRP2, 0x2) + } + + If (\_SB.PCI0.TRP3.HPME() == 1) { + Notify (\_SB.PCI0.TDM1, 0x2) + Notify (\_SB.PCI0.TRP3, 0x2) + } + } + + /* Invoke PCIe root ports power management status handler */ + \_SB.PCI0.TRP0.HPME() + \_SB.PCI0.TRP1.HPME() + \_SB.PCI0.TRP2.HPME() + \_SB.PCI0.TRP3.HPME() + } +} + +Scope (\_SB.PCI0) +{ + Device (IOM) + { + Name (_HID, "INTC10EA") + Name (_DDN, "Intel(R) Lunar Lake Input Output Manager(IOM) driver") + /* IOM preserved MMIO range from 0x3fff0aa0000 to 0x3fff0aa15ff. */ + Name (_CRS, ResourceTemplate () { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, 0x0, + 0xE0800000, 0xE08015ff, 0x0, + 0x1600,,,) + }) + /* Hide the device so that Windows does not complain on missing driver */ + Name (_STA, 0xB) + } + + /* + * Operation region defined to access the TCSS_DEVEN. Get the MCHBAR in offset + * 0x48 in B0:D0:F0. TCSS device enable base address is in offset 0x7090 of MCHBAR. + */ + OperationRegion (TDEN, SystemMemory, (GMHB() + MCHBAR_TCSS_DEVEN_OFFSET), 0x4) + Field (TDEN, ByteAcc, NoLock, Preserve) + { + TRE0, 1, /* PCIE0_EN */ + TRE1, 1, /* PCIE1_EN */ + TRE2, 1, /* PCIE2_EN */ + TRE3, 1, /* PCIE3_EN */ + , 4, + THCE, 1, /* XHCI_EN */ + TDCE, 1, /* XDCI_EN */ + DME0, 1, /* TBT_DMA0_EN */ + DME1, 1, /* TBT_DMA1_EN */ + , 20 + } + + /* + * Operation region defined to access the pCode mailbox interface. Get the MCHBAR + * in offset 0x48 in B0:D0:F0. MMIO address is in offset 0x5DA0 of MCHBAR. + */ + OperationRegion (PBAR, SystemMemory, (GMHB() + 0x5DA0), 0x08) + Field (PBAR, DWordAcc, NoLock, Preserve) + { + PMBD, 32, /* pCode MailBox Data, offset 0x5DA0 in MCHBAR */ + PMBC, 8, /* pCode MailBox Command, [7:0] of offset 0x5DA4 in MCHBAR */ + PSCM, 8, /* pCode MailBox Sub-Command, [15:8] of offset 0x5DA4 in MCHBAR */ + , 15, /* Reserved */ + PMBR, 1 /* pCode MailBox RunBit, [31:31] of offset 0x5DA4 in MCHBAR */ + } + + /* + * Poll pCode MailBox Ready + * + * Return 0xFF - Timeout + * 0x00 - Ready + */ + Method (PMBY, 0) + { + Local0 = 0 + While (PMBR && (Local0 < 1000)) { + Local0++ + Stall (1) + } + If (Local0 == 1000) { + Printf("Timeout occurred.") + Return (0xFF) + } + Return (0) + } + + + /* From RegBar Base, IOM_TypeC_SW_configuration_1 is at offset 0x40 */ + /*OperationRegion (IOMR, SystemMemory, IOM_BASE_ADDR, 0x100)*/ + OperationRegion (IOMR, SystemMemory, 0xE0800000, 0x100) + Field (IOMR, DWordAcc, NoLock, Preserve) + { + Offset(0x40), + , 15, + TD3C, 1, /* [15:15] Type C D3 cold bit */ + TACK, 1, /* [16:16] IOM Acknowledge bit */ + DPOF, 1, /* [17:17] Set 1 to indicate IOM, all the */ + /* display is OFF, clear otherwise */ + Offset(0x70), /* Physical addr is offset 0x70. */ + IMCD, 32, /* R_SA_IOM_BIOS_MAIL_BOX_CMD */ + IMDA, 32 /* R_SA_IOM_BIOS_MAIL_BOX_DATA */ + } + + /* + * TBT Group0 ON method + */ + Method (TG0N, 0) + { + If (\_SB.PCI0.TDM0.VDID == 0xFFFFFFFF) { + Printf("TDM0 does not exist.") + } Else { + If (\_SB.PCI0.TDM0.STAT == 0) { + /* DMA0 is in D3Cold early. */ + \_SB.PCI0.TDM0.D3CX() /* RTD3 Exit */ + + Printf("Bring TBT RPs out of D3Code.") + If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) { + /* RP0 D3 cold exit. */ + \_SB.PCI0.TRP0.D3CX() + } + If (\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) { + /* RP1 D3 cold exit. */ + \_SB.PCI0.TRP1.D3CX() + } + } Else { + Printf("Drop TG0N due to it is already exit D3 cold.") + } + + /* TBT RTD3 exit 10ms delay. */ + Sleep (10) + } + } + + /* + * TBT Group0 OFF method + */ + Method (TG0F, 0) + { + If (\_SB.PCI0.TDM0.VDID == 0xFFFFFFFF) { + Printf("TDM0 does not exist.") + } Else { + If (\_SB.PCI0.TDM0.STAT == 1) { + /* DMA0 is not in D3Cold now. */ + \_SB.PCI0.TDM0.D3CE() /* Enable DMA RTD3 */ + + If (\_SB.PCI0.TDM0.IF30 != 1) { + Return + } + + Printf("Push TBT RPs to D3Cold together") + If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) { + /* Put RP0 to D3 cold. */ + \_SB.PCI0.TRP0.D3CE() + } + If (\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) { + /* Put RP1 to D3 cold. */ + \_SB.PCI0.TRP1.D3CE() + } + } + } + } + + /* + * TBT Group1 ON method + */ + Method (TG1N, 0) + { + If (\_SB.PCI0.TDM1.VDID == 0xFFFFFFFF) { + Printf("TDM1 does not exist.") + } Else { + If (\_SB.PCI0.TDM1.STAT == 0) { + /* DMA1 is in D3Cold early. */ + \_SB.PCI0.TDM1.D3CX() /* RTD3 Exit */ + + Printf("Bring TBT RPs out of D3Code.") + If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) { + /* RP2 D3 cold exit. */ + \_SB.PCI0.TRP2.D3CX() + } + If (\_SB.PCI0.TRP3.VDID != 0xFFFFFFFF) { + /* RP3 D3 cold exit. */ + \_SB.PCI0.TRP3.D3CX() + } + } Else { + Printf("Drop TG1N due to it is already exit D3 cold.") + } + + /* TBT RTD3 exit 10ms delay. */ + Sleep (10) + } + } + + /* + * TBT Group1 OFF method + */ + Method (TG1F, 0) + { + If (\_SB.PCI0.TDM1.VDID == 0xFFFFFFFF) { + Printf("TDM1 does not exist.") + } Else { + If (\_SB.PCI0.TDM1.STAT == 1) { + /* DMA1 is not in D3Cold now */ + \_SB.PCI0.TDM1.D3CE() /* Enable DMA RTD3. */ + + If (\_SB.PCI0.TDM1.IF30 != 1) { + Return + } + + Printf("Push TBT RPs to D3Cold together") + If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) { + /* Put RP2 to D3 cold. */ + \_SB.PCI0.TRP2.D3CE() + } + If (\_SB.PCI0.TRP3.VDID != 0xFFFFFFFF) { + /* Put RP3 to D3 cold */ + \_SB.PCI0.TRP3.D3CE() + } + } + } + } + + PowerResource (TBT0, 5, 1) + { + Method (_STA, 0) + { + Return (\_SB.PCI0.TDM0.STAT) + } + + Method (_ON, 0) + { + TG0N() + } + + Method (_OFF, 0) + { + If (\_SB.PCI0.TDM0.SD3C == 0) { + TG0F() + } + } + } + + PowerResource (TBT1, 5, 1) + { + Method (_STA, 0) + { + Return (\_SB.PCI0.TDM1.STAT) + } + + Method (_ON, 0) + { + TG1N() + } + + Method (_OFF, 0) + { + If (\_SB.PCI0.TDM1.SD3C == 0) { + TG1F() + } + } + } + +#if CONFIG(D3COLD_SUPPORT) + Method (TCON, 0) + { + /* Reset IOM D3 cold bit if it is in D3 cold now. */ + If (TD3C == 1) /* It was in D3 cold before. */ + { + /* Reset IOM D3 cold bit. */ + TD3C = 0 /* Request IOM for D3 cold exit sequence. */ + Local0 = 0 /* Time check counter variable */ + /* Wait for ack, the maximum wait time for the ack is 100 msec. */ + While ((TACK != 0) && (Local0 < TCSS_IOM_ACK_TIMEOUT_IN_MS)) { + /* + * Wait in this loop until TACK becomes 0 with timeout + * TCSS_IOM_ACK_TIMEOUT_IN_MS by default. + */ + Sleep (1) /* Delay of 1ms. */ + Local0++ + } + + If (Local0 == TCSS_IOM_ACK_TIMEOUT_IN_MS) { + Printf("Error: Timeout occurred.") + } + Else + { + Printf("TCSS D3 exit."); + } + } + Else { + Printf("Drop TCON due to it is already exit D3 cold.") + } + } + + Method (TCOF, 0) + { + If ((\_SB.PCI0.TXHC.SD3C != 0) || (\_SB.PCI0.TDM0.SD3C != 0) + || (\_SB.PCI0.TDM1.SD3C != 0)) + { + Printf("Skip D3C entry.") + Return + } + + /* Request IOM for D3 cold entry sequence. */ + /* + * FIXME: Remove this workaround after resolving b/244082753 + * + * Document #742990: TCCold exit flow may not complete when processor at package + * C0. The implication is that the system may hang. + */ + // TD3C = 1 + } + + PowerResource (D3C, 5, 0) + { + /* + * Variable to save power state + * 1 - TC Cold request cleared. + * 0 - TC Cold request sent. + */ + Name (STAT, 0x1) + + Method (_STA, 0) + { + Return (STAT) + } + + Method (_ON, 0) + { + \_SB.PCI0.TCON() + STAT = 1 + } + + Method (_OFF, 0) + { + \_SB.PCI0.TCOF() + STAT = 0 + } + } +#endif // D3COLD_SUPPORT + + /* + * TCSS xHCI device + */ + Device (TXHC) + { + Name (_ADR, 0x000D0000) + Name (_DDN, "North XHCI controller") + Name (_STR, Unicode ("North XHCI controller")) + Name (DCPM, TCSS_XHCI) + + Method (_STA, 0x0, NotSerialized) + { + If (THCE == 1) { + Return (0x0F) + } Else { + Return (0x0) + } + } + #include "tcss_xhci.asl" + } + + /* + * TCSS DMA0 device + */ + Device (TDM0) + { + Name (_ADR, 0x000D0002) + Name (_DDN, "TBT DMA0 controller") + Name (_STR, Unicode ("TBT DMA0 controller")) + Name (DUID, 0) /* TBT DMA number */ + Name (DCPM, TCSS_DMA0) + + Method (_STA, 0x0, NotSerialized) + { + If (DME0 == 1) { + Return (0x0F) + } Else { + Return (0x0) + } + } + #include "tcss_dma.asl" + } + + /* + * TCSS DMA1 device + */ + Device (TDM1) + { + Name (_ADR, 0x000D0003) + Name (_DDN, "TBT DMA1 controller") + Name (_STR, Unicode ("TBT DMA1 controller")) + Name (DUID, 1) /* TBT DMA number */ + Name (DCPM, TCSS_DMA1) + + Method (_STA, 0x0, NotSerialized) + { + If (DME1 == 1) { + Return (0x0F) + } Else { + Return (0x0) + } + } + #include "tcss_dma.asl" + } + + /* + * TCSS PCIE Root Port #00 + */ + Device (TRP0) + { + Name (_ADR, 0x00070000) + Name (TUID, 0) /* TBT PCIE RP Number 0 for RP00 */ + Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */ + Name (LMSL, 0) /* PCIE LTR max snoop Latency */ + Name (LNSL, 0) /* PCIE LTR max no snoop Latency */ + Name (DCPM, TCSS_TBT_PCIE0_RP0) + + Method (_STA, 0x0, NotSerialized) + { + If (TRE0 == 1) { + Return (0x0F) + } Else { + Return (0x0) + } + } + + Method (_INI) + { + LTEN = 0 + LMSL = 0x88C8 + LNSL = 0x88C8 + } + #include "tcss_pcierp.asl" + } + + /* + * TCSS PCIE Root Port #01 + */ + Device (TRP1) + { + Name (_ADR, 0x00070001) + Name (TUID, 1) /* TBT PCIE RP Number 1 for RP01 */ + Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */ + Name (LMSL, 0) /* PCIE LTR max snoop Latency */ + Name (LNSL, 0) /* PCIE LTR max no snoop Latency */ + Name (DCPM, TCSS_TBT_PCIE0_RP1) + + Method (_STA, 0x0, NotSerialized) + { + If (TRE1 == 1) { + Return (0x0F) + } Else { + Return (0x0) + } + } + + Method (_INI) + { + LTEN = 0 + LMSL = 0x88C8 + LNSL = 0x88C8 + } + #include "tcss_pcierp.asl" + } + + /* + * TCSS PCIE Root Port #02 + */ + Device (TRP2) + { + Name (_ADR, 0x00070002) + Name (TUID, 2) /* TBT PCIE RP Number 2 for RP02 */ + Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */ + Name (LMSL, 0) /* PCIE LTR max snoop Latency */ + Name (LNSL, 0) /* PCIE LTR max no snoop Latency */ + Name (DCPM, TCSS_TBT_PCIE0_RP2) + + Method (_STA, 0x0, NotSerialized) + { + If (TRE2 == 1) { + Return (0x0F) + } Else { + Return (0x0) + } + } + + Method (_INI) + { + LTEN = 0 + LMSL = 0x88C8 + LNSL = 0x88C8 + } + #include "tcss_pcierp.asl" + } + + /* + * TCSS PCIE Root Port #03 + */ + Device (TRP3) + { + Name (_ADR, 0x00070003) + Name (TUID, 3) /* TBT PCIE RP Number 3 for RP03 */ + Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */ + Name (LMSL, 0) /* PCIE LTR max snoop Latency */ + Name (LNSL, 0) /* PCIE LTR max no snoop Latency */ + Name (DCPM, TCSS_TBT_PCIE0_RP3) + + Method (_STA, 0x0, NotSerialized) + { + If (TRE3 == 1) { + Return (0x0F) + } Else { + Return (0x0) + } + } + + Method (_INI) + { + LTEN = 0 + LMSL = 0x88C8 + LNSL = 0x88C8 + } + #include "tcss_pcierp.asl" + } +} diff --git a/src/soc/intel/lnl_dev/acpi/tcss_dma.asl b/src/soc/intel/lnl_dev/acpi/tcss_dma.asl new file mode 100644 index 0000000..d2aab97 --- /dev/null +++ b/src/soc/intel/lnl_dev/acpi/tcss_dma.asl @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +OperationRegion (DPME, SystemMemory, BASE(_ADR), 0x100) +Field (DPME, AnyAcc, NoLock, Preserve) +{ + VDID, 32, + Offset(0x84), /* 0x84, DMA CFG PM CAP */ + PMST, 2, /* 1:0, PM_STATE */ + Offset (0x85), + PMEE, 1, /* 8, PME_EN */ + , 6, + PMES, 1, /* 15, PME_STATUS */ + Offset(0xC8), /* 0xC8, TBT NVM FW Revision */ + , 30, + IF30, 1, /* ITBT FW Version Bit30 */ + INFR, 1, /* TBT NVM FW Ready */ + Offset(0xEC), /* 0xEC, TBT TO PCIE Register */ + TB2P, 32, /* TBT to PCIe */ + P2TB, 32, /* PCIe to TBT */ + Offset(0xFC), /* 0xFC, DMA RTD3 Force Power */ + DD3E, 1, /* 0:0 DMA RTD3 Enable */ + DFPE, 1, /* 1:1 DMA Force Power */ + Offset (0xFF), + DMAD, 8 /* 31:24 DMA Active Delay */ +} + +Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */ + +Method (_S0W, 0x0) +{ +#if CONFIG(D3COLD_SUPPORT) + Return (0x04) +#else + Return (0x03) +#endif // D3COLD_SUPPORT +} + +/* + * Get power resources that are dependent on this device for Operating System Power Management + * to put the device in the D0 device state + */ +Method (_PR0) +{ +#if CONFIG(D3COLD_SUPPORT) + If (DUID == 0) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } +#else + If (DUID == 0) { + Return (Package() { \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.TBT1 }) + } +#endif // D3COLD_SUPPORT +} + +Method (_PR3) +{ +#if CONFIG(D3COLD_SUPPORT) + If (DUID == 0) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } +#else + If (DUID == 0) { + Return (Package() { \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.TBT1 }) + } +#endif // D3COLD_SUPPORT +} + +/* + * RTD3 Exit Method to bring TBT controller out of RTD3 mode. + */ +Method (D3CX, 0, Serialized) +{ + DD3E = 0x00 /* Disable DMA RTD3 */ + STAT = 0x01 +} + +/* + * RTD3 Entry method to enable TBT controller RTD3 mode. + */ +Method (D3CE, 0, Serialized) +{ + DD3E = 0x01 /* Enable DMA RTD3 */ + STAT = 0x00 +} + +/* + * Variable to skip TCSS/TBT D3 cold; 1+: Skip D3CE, 0 - Enable D3CE + * TCSS D3 Cold and TBT RTD3 is only available when system power state is in S0. + */ +Name (SD3C, 0) + +Method (_DSW, 3) +{ + /* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */ + SD3C = Arg1 +} + +Method (_PRW, 0) +{ + Return (Package() { 0x6D, 4 }) +} diff --git a/src/soc/intel/lnl_dev/acpi/tcss_pcierp.asl b/src/soc/intel/lnl_dev/acpi/tcss_pcierp.asl new file mode 100644 index 0000000..f09392d --- /dev/null +++ b/src/soc/intel/lnl_dev/acpi/tcss_pcierp.asl @@ -0,0 +1,318 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +OperationRegion (PXCS, SystemMemory, BASE(_ADR), 0xC00) +Field (PXCS, AnyAcc, NoLock, Preserve) +{ + VDID, 32, + Offset(0x50), /* LCTL - Link Control Register */ + L0SE, 1, /* 0, L0s Entry Enabled */ + , 3, + LDIS, 1, /* 1, Link Disable */ + , 3, + Offset(0x51), + Offset(0x52), /* LSTS - Link Status Register */ + , 13, + LASX, 1, /* 0, Link Active Status */ + Offset(0x5A), /* SLSTS[7:0] - Slot Status Register */ + ABPX, 1, /* 0, Attention Button Pressed */ + , 2, + PDCX, 1, /* 3, Presence Detect Changed */ + , 2, + PDSX, 1, /* 6, Presence Detect State */ + , 1, + Offset (0x5B), + DLSC, 1, /* 8, Data Link Layer State Changed */ + Offset(0x60), /* RSTS - Root Status Register */ + Offset(0x62), + PSPX, 1, /* 16, PME Status */ + Offset (0x68), + , 10, + LNRE, 1, + Offset(0xA4), + D3HT, 2, /* Power State */ + Offset (0x404), + LSOE, 1, + LNSE, 1, + Offset(0x420), /* 0x420, PCIEPMECTL (PCIe PM Extension Control) */ + , 30, + DPGE, 1, /* PCIEPMECTL[30]: Disabled, Detect and L23_Rdy State PHY Lane */ + /* Power Gating Enable (DLSULPPGE) */ + Offset(0x5BC), /* 0x5BC, PCIE ADVMCTRL */ + , 3, + RPER, 1, /* RTD3PERST[3] */ + RPFE, 1, /* RTD3PFETDIS[4] */ + Offset(0xBA8), /* 0xBA8, MPC - Miscellaneous Port Configuration Register */ + , 30, + HPEX, 1, /* 30, Hot Plug SCI Enable */ + PMEX, 1, /* 31, Power Management SCI Enable */ + Offset(0xBB2), /* 0xBB2, RPPGEN - Root Port Power Gating Enable */ + , 2, + L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */ + L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */ +} + +Field (PXCS, AnyAcc, NoLock, WriteAsZeros) +{ + Offset(0xBAC), /* 0xDC, SMSCS - SMI/SCI Status Register */ + , 30, + HPSX, 1, /* 30, Hot Plug SCI Status */ + PMSX, 1 /* 31, Power Management SCI Status */ +} + +/* + * _DSM Device Specific Method + * + * Arg0: UUID Unique function identifier + * Arg1: Integer Revision Level + * Arg2: Integer Function Index (0 = Return Supported Functions) + * Arg3: Package Parameters + */ +Method (_DSM, 4, Serialized) +{ + Return (Buffer() { 0x00 }) +} + +/* + * A bitmask of functions support + */ +Name(OPTS, Buffer(2) {0, 0}) + +Device (PXSX) +{ + Name (_ADR, 0x00000000) + + /* + * _DSM Device Specific Method + * + * Arg0: UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D + * Arg1: Revision ID: 3 + * Arg2: Function index: 0, 9 + * Arg3: Empty package + */ + Method (_DSM, 4, Serialized) + { + If (Arg0 == ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D")) { + If (Arg1 >= 3) { + If (Arg2 == 0) { + /* + * Function index: 0 + * Standard query - A bitmask of functions supported + */ + CreateBitField(OPTS, 9, FUN9) + FUN9 = 1 + Return (OPTS) + } ElseIf (Arg2 == 9) { + /* + * Function index: 9 + * Specifying device readiness durations + */ + Return (Package() { FW_RESET_TIME, FW_DL_UP_TIME, + FW_FLR_RESET_TIME, FW_D3HOT_TO_D0_TIME, + FW_VF_ENABLE_TIME }) + } + } + } + Return (Buffer() { 0x0 }) + } + + Method (_PRW, 0) + { + Return (Package() { 0x69, 4 }) + } +} + +Method (_DSW, 3) +{ + /* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */ + If ((TUID == 0) || (TUID == 1)) { + \_SB.PCI0.TDM0.SD3C = Arg1 + } Else { + \_SB.PCI0.TDM1.SD3C = Arg1 + } + + C2PM (Arg0, Arg1, Arg2, DCPM) +} + +Method (_PRW, 0) +{ + Return (Package() { 0x69, 4 }) +} + +/* + * Sub-Method of _L61 Hot-Plug event + * _L61 event handler should invoke this method to support HotPlug wake event from TBT RP. + */ +Method (HPEV, 0, Serialized) +{ + If ((VDID != 0xFFFFFFFF) && HPSX) { + If ((PDCX == 1) && (DLSC == 1)) { + /* Clear all status bits first. */ + PDCX = 1 + HPSX = 1 + + /* Perform proper notification to the OS. */ + Notify (^, 0) + } Else { + /* False event. Clear Hot-Plug Status, then exit. */ + HPSX = 1 + } + } +} + +/* + * Power Management routine for D3 + */ +Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */ + +/* + * RTD3 Exit Method to bring TBT controller out of RTD3 mode. + */ +Method (D3CX, 0, Serialized) +{ + If (STAT == 0x1) { + Return + } + + RPFE = 0 /* Set RTD3PFETDIS = 0 */ + RPER = 0 /* Set RTD3PERST = 0 */ + L23R = 1 /* Set L23r2dt = 1 */ + + /* + * Poll for L23r2dt == 0. Wait for transition to Detect. + */ + Local0 = 0 + Local1 = L23R + While (Local1) { + If (Local0 > 20) { + Break + } + Sleep(5) + Local0++ + Local1 = L23R + } + STAT = 0x1 +} + +/* + * RTD3 Entry method to enable TBT controller RTD3 mode. + */ +Method (D3CE, 0, Serialized) +{ + If (STAT == 0x0) { + Return + } + + L23E = 1 /* Set L23er = 1 */ + + /* Poll until L23er == 0 */ + Local0 = 0 + Local1 = L23E + While (Local1) { + If (Local0 > 20) { + Break + } + Sleep(5) + Local0++ + Local1 = L23E + } + + STAT = 0 /* D3Cold */ + RPFE = 1 /* Set RTD3PFETDIS = 1 */ + RPER = 1 /* Set RTD3PERST = 1 */ +} + +Method (_PS0, 0, Serialized) +{ + HPEV () /* Check and handle Hot Plug SCI status. */ + If (HPEX == 1) { + HPEX = 0 /* Disable Hot Plug SCI */ + } + HPME () /* Check and handle PME SCI status */ + If (PMEX == 1) { + PMEX = 0 /* Disable Power Management SCI */ + } +} + +Method (_PS3, 0, Serialized) +{ + /* Check it is hotplug SCI or not, then clear PDC accordingly */ + If (PDCX == 1) { + If (DLSC == 0) { + /* Clear PDC since it is not a hotplug. */ + PDCX = 1 + } + } + + If (HPEX == 0) { + HPEX = 1 /* Enable Hot Plug SCI. */ + HPEV () /* Check and handle Hot Plug SCI status. */ + } + If (PMEX == 0) { + PMEX = 1 /* Enable Power Management SCI. */ + HPME () /* Check and handle PME SCI status. */ + } +} + +Method (_S0W, 0x0, NotSerialized) +{ +#if CONFIG(D3COLD_SUPPORT) + Return (0x4) +#else + Return (0x3) +#endif // D3COLD_SUPPORT +} + +Method (_PR0) +{ +#if CONFIG(D3COLD_SUPPORT) + If ((TUID == 0) || (TUID == 1)) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } +#else + If ((TUID == 0) || (TUID == 1)) { + Return (Package() { \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.TBT1 }) + } +#endif // D3COLD_SUPPORT +} + +Method (_PR3) +{ +#if CONFIG(D3COLD_SUPPORT) + If ((TUID == 0) || (TUID == 1)) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } +#else + If ((TUID == 0) || (TUID == 1)) { + Return (Package() { \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.TBT1 }) + } +#endif // D3COLD_SUPPORT +} + +/* + * PCI_EXP_STS Handler for PCIE Root Port + */ +Method (HPME, 0, Serialized) +{ + If ((VDID != 0xFFFFFFFF) && (PMSX == 1)) { /* if port exists and PME SCI Status set */ + /* + * Notify child device; this will cause its driver to clear PME_Status from + * device. + */ + Notify (PXSX, 0x2) + PMSX = 1 /* clear rootport's PME SCI status */ + /* + * Consume one pending PME notification to prevent it from blocking the queue. + */ + PSPX = 1 + Return (0x01) + } + Return (0x00) +} diff --git a/src/soc/intel/lnl_dev/acpi/tcss_xhci.asl b/src/soc/intel/lnl_dev/acpi/tcss_xhci.asl new file mode 100644 index 0000000..6252fd5 --- /dev/null +++ b/src/soc/intel/lnl_dev/acpi/tcss_xhci.asl @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +OperationRegion (XPRT, SystemMemory, BASE(_ADR), 0x100) +Field (XPRT, ByteAcc, NoLock, Preserve) +{ + VDID, 32, + Offset(0x74), /* 0x74, XHCI CFG Power Control And Status */ + D0D3, 2, /* 0x74 BIT[1:0] */ + , 6, + PMEE, 1, /* PME Enable */ + , 6, + PMES, 1, /* PME Status */ +} + +Method (_PS0, 0, Serialized) +{ + If (\_SB.PCI0.TXHC.PMEE == 1) { + /* Clear PME_EN of CPU xHCI */ + \_SB.PCI0.TXHC.PMEE = 0 + } +} + +Method (_PS3, 0, Serialized) +{ + If (\_SB.PCI0.TXHC.PMEE == 0) { + /* Set PME_EN of CPU xHCI */ + \_SB.PCI0.TXHC.PMEE = 1 + } +} + +Method (_S0W, 0x0, NotSerialized) +{ +#if CONFIG(D3COLD_SUPPORT) + Return (0x4) +#else + Return (0x3) +#endif // D3COLD_SUPPORT +} + +/* + * Variable to skip TCSS/TBT D3 cold; 1+: Skip D3CE, 0 - Enable D3CE + * TCSS D3 Cold and TBT RTD3 is only available when system power state is in S0. + */ +Name (SD3C, 0) + +#if CONFIG(D3COLD_SUPPORT) +Method (_PR0) +{ + Return (Package () { \_SB.PCI0.D3C }) +} + +Method (_PR3) +{ + Return (Package () { \_SB.PCI0.D3C }) +} +#endif // D3COLD_SUPPORT + +/* + * XHCI controller _DSM method + */ +Method (_DSM, 4, serialized) +{ + Return (Buffer() { 0 }) +} + +/* + * _SXD and _SXW methods + */ +Method (_S3D, 0, NotSerialized) +{ + Return (3) +} + +Method (_S4D, 0, NotSerialized) +{ + Return (3) +} + +Method (_S3W, 0, NotSerialized) +{ + Return (3) +} + +Method (_S4W, 0, NotSerialized) +{ + Return (3) +} + +/* + * Power resource for wake + */ +Method (_PRW, 0) +{ + Return (Package() { 0x6D, 4 }) +} + +/* + * Device sleep wake + */ +Method (_DSW, 3) +{ + C2PM (Arg0, Arg1, Arg2, DCPM) + /* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */ + SD3C = Arg1 +} + +/* + * xHCI Root Hub Device + */ +Device (RHUB) +{ + Name (_ADR, 0) + + /* High Speed Ports */ + Device (HS01) + { + Name (_ADR, 0x01) + } + + /* Super Speed Ports */ + Device (SS01) + { + Name (_ADR, 0x02) + Method (_DSD, 0, NotSerialized) + { + Return( Package () + { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (2) { "usb4-host-interface", \_SB.PCI0.TDM0 }, + Package (2) { "usb4-port-number", 0 } + } + }) + } + } + + Device (SS02) + { + Name (_ADR, 0x03) + Method (_DSD, 0, NotSerialized) + { + Return( Package () + { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (2) { "usb4-host-interface", \_SB.PCI0.TDM0 }, + Package (2) { "usb4-port-number", 1 } + } + }) + } + } + + Device (SS03) + { + Name (_ADR, 0x04) + Method (_DSD, 0, NotSerialized) + { + Return( Package () + { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (2) { "usb4-host-interface", \_SB.PCI0.TDM1 }, + Package (2) { "usb4-port-number", 2 } + } + }) + } + } + + Device (SS04) + { + Name (_ADR, 0x05) + Method (_DSD, 0, NotSerialized) + { + Return( Package () + { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (2) { "usb4-host-interface", \_SB.PCI0.TDM1 }, + Package (2) { "usb4-port-number", 3 } + } + }) + } + } +} diff --git a/src/soc/intel/lnl_dev/acpi/ufs.asl b/src/soc/intel/lnl_dev/acpi/ufs.asl new file mode 100644 index 0000000..23ffa65 --- /dev/null +++ b/src/soc/intel/lnl_dev/acpi/ufs.asl @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (UFS) +{ + Name (_ADR, 0x00170000) + Name (_DDN, "UFS Controller") + + Method (_DSD, 0, NotSerialized) + { + Return ( Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, + Package (0x01) + { + Package (0x02) + { + "ref-clk-freq", + CONFIG_SOC_INTEL_UFS_CLK_FREQ_HZ + } + } + }) + } +} diff --git a/src/soc/intel/lnl_dev/acpi/xhci.asl b/src/soc/intel/lnl_dev/acpi/xhci.asl new file mode 100644 index 0000000..dda4878 --- /dev/null +++ b/src/soc/intel/lnl_dev/acpi/xhci.asl @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpe.h> + +/* XHCI Controller 0:14.0 */ + +Device (XHCI) +{ + Name (_ADR, 0x00140000) + + Name (_PRW, Package () { GPE0_PME_B0, 3 }) + + Name (_S3D, 3) /* D3 supported in S3 */ + Name (_S0W, 3) /* D3 can wake device in S0 */ + Name (_S3W, 3) /* D3 can wake system from S3 */ + + Method (_PS0, 0, Serialized) + { + /* Disable Clock Gating */ +#if CONFIG(SOC_INTEL_LUNARLAKE) + ^^PCRA (PID_XHCI, 0x0, ~(1 << 3)) +#endif + } + + Method (_PS3, 0, Serialized) + { + /* Enable Clock Gating */ +#if CONFIG(SOC_INTEL_LUNARLAKE) + ^^PCRO (PID_XHCI, 0x0, 1 << 3) +#endif + } + + /* Root Hub for Lunarlake */ + Device (RHUB) + { + Name (_ADR, 0) + + /* USB2 */ + Device (HS01) { Name (_ADR, 1) } + Device (HS02) { Name (_ADR, 2) } + Device (HS03) { Name (_ADR, 3) } + Device (HS04) { Name (_ADR, 4) } + Device (HS05) { Name (_ADR, 5) } + Device (HS06) { Name (_ADR, 6) } + Device (HS07) { Name (_ADR, 7) } + Device (HS08) { Name (_ADR, 8) } + Device (HS09) { Name (_ADR, 9) } + Device (HS10) { Name (_ADR, 10) } + /* USB3 */ + Device (SS01) { Name (_ADR, 11) } + Device (SS02) { Name (_ADR, 12) } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/81873?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If0f538650fe3d0e8cf062f5545bbce0264be99b2 Gerrit-Change-Number: 81873 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-MessageType: newchange

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[XL] Change in coreboot[main]: soc/intel/lnl: Do initial Lunar Lake SoC commit till romstage
by Saurabh Mishra (Code Review) 12 Apr '24

12 Apr '24

Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81872?usp=email ) Change subject: soc/intel/lnl: Do initial Lunar Lake SoC commit till romstage ...................................................................... soc/intel/lnl: Do initial Lunar Lake SoC commit till romstage List of changes: 1. Add required SoC programming till romstage 2. Include only required headers into include/soc 3. Fill required FSP-M UPD to call FSP-M API Change-Id: Id6a01284018c3dcaa80ad1b2e92d6b88ddb83018 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- A src/soc/intel/lnl_dev/chip.h A src/soc/intel/lnl_dev/espi.c A src/soc/intel/lnl_dev/include/soc/gpe.h A src/soc/intel/lnl_dev/include/soc/meminit.h A src/soc/intel/lnl_dev/include/soc/msr.h A src/soc/intel/lnl_dev/include/soc/pmc.h A src/soc/intel/lnl_dev/include/soc/romstage.h A src/soc/intel/lnl_dev/include/soc/soc_chip.h A src/soc/intel/lnl_dev/include/soc/soc_info.h A src/soc/intel/lnl_dev/include/soc/systemagent.h A src/soc/intel/lnl_dev/lunarlake/chipset.cb A src/soc/intel/lnl_dev/lunarlake/meminit.c A src/soc/intel/lnl_dev/lunarlake/romstage/fsp_params.c A src/soc/intel/lnl_dev/lunarlake/romstage/systemagent.c A src/soc/intel/lnl_dev/p2sb.c A src/soc/intel/lnl_dev/reset.c A src/soc/intel/lnl_dev/romstage.c A src/soc/intel/lnl_dev/systemagent.c 18 files changed, 2,031 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/81872/1 diff --git a/src/soc/intel/lnl_dev/chip.h b/src/soc/intel/lnl_dev/chip.h new file mode 100644 index 0000000..9f348c3 --- /dev/null +++ b/src/soc/intel/lnl_dev/chip.h @@ -0,0 +1,367 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_CHIP_H_ +#define _SOC_CHIP_H_ + +#include <drivers/i2c/designware/dw_i2c.h> +#include <device/pci_ids.h> +#include <intelblocks/cfg.h> +#include <intelblocks/gpio.h> +#include <intelblocks/gspi.h> +#include <intelblocks/power_limit.h> +#include <intelblocks/pcie_rp.h> +#include <intelblocks/tcss.h> +#include <soc/gpe.h> +#include <soc/pci_devs.h> +#include <soc/pmc.h> +#include <soc/serialio.h> +#include <soc/usb.h> +#include <stdint.h> +#include <soc/powerlimit.h> + +/* Define config parameters for In-Band ECC (IBECC). */ +#ifndef MAX_IBECC_REGIONS +#define MAX_IBECC_REGIONS 8 +#endif +/* In-Band ECC Operation Mode */ +enum ibecc_mode { + IBECC_MODE_PER_REGION, + IBECC_MODE_NONE, + IBECC_MODE_ALL +}; + +struct ibecc_config { + bool enable; + enum ibecc_mode mode; + bool range_enable[MAX_IBECC_REGIONS]; + uint16_t range_base[MAX_IBECC_REGIONS]; + uint16_t range_mask[MAX_IBECC_REGIONS]; + /* add ECC error injection if needed by a mainboard */ +}; + +#ifdef MAX_IBECC_REGIONS +#undef MAX_IBECC_REGIONS +#endif + +/* Types of display ports */ +enum ddi_ports { + DDI_PORT_A, + DDI_PORT_B, + DDI_PORT_C, + DDI_PORT_1, + DDI_PORT_2, + DDI_PORT_3, + DDI_PORT_4, + DDI_PORT_COUNT, +}; + +enum ddi_port_flags { + DDI_ENABLE_DDC = 1 << 0, // Display Data Channel + DDI_ENABLE_HPD = 1 << 1, // Hot Plug Detect +}; + +/* + * The Max Pkg Cstate + * Values 0 - C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10, + * 254 - CPU Default , 255 - Auto. + */ +enum pkgcstate_limit { + LIMIT_C0_C1 = 0, + LIMIT_C2 = 1, + LIMIT_C3 = 2, + LIMIT_C6 = 3, + LIMIT_C7 = 4, + LIMIT_C7S = 5, + LIMIT_C8 = 6, + LIMIT_C9 = 7, + LIMIT_C10 = 8, + LIMIT_CPUDEFAULT = 254, + LIMIT_AUTO = 255, +}; + +/* Bit values for use in LpmStateEnableMask. */ +enum lpm_state_mask { + LPM_S0i2_0 = BIT(0), + LPM_S0i2_1 = BIT(1), + LPM_S0i2_2 = BIT(2), + LPM_S0i3_0 = BIT(3), + LPM_S0i3_1 = BIT(4), + LPM_S0i3_2 = BIT(5), + LPM_S0i3_3 = BIT(6), + LPM_S0i3_4 = BIT(7), + LPM_S0iX_ALL = LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2 + | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4, +}; + +struct soc_intel_lnl_dev_config { + + /* Common struct containing soc config data required by common code */ + struct soc_intel_common_config common_soc_config; + + /* Common struct containing power limits configuration information */ + struct soc_power_limits_config power_limits_config[LNL_POWER_LIMITS_COUNT]; + + /* Gpio group routed to each dword of the GPE0 block. Values are + * of the form PMC_GPP_[A:U] or GPD. */ + uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ + uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */ + uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */ + + /* Generic IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; + + /* Enable S0iX support */ + int s0ix_enable; + /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */ + uint8_t tcss_d3_hot_disable; + /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */ + uint8_t TcssD3ColdDisable; + /* Enable DPTF support */ + int dptf_enable; + + /* Deep SX enable for both AC and DC */ + int deep_s3_enable_ac; + int deep_s3_enable_dc; + int deep_s5_enable_ac; + int deep_s5_enable_dc; + + /* Deep Sx Configuration + * DSX_EN_WAKE_PIN - Enable WAKE# pin + * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin + * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */ + uint32_t deep_sx_config; + + /* TCC activation offset */ + uint32_t tcc_offset; + + /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs. + * When enabled memory will be training at two different frequencies. + * 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, + * 4:FixedPoint3, 5:Enabled */ + enum { + SaGv_Disabled, + SaGv_FixedPoint0, + SaGv_FixedPoint1, + SaGv_FixedPoint2, + SaGv_FixedPoint3, + SaGv_Enabled, + } sagv; + + /* Rank Margin Tool. 1:Enable, 0:Disable */ + uint8_t rmt; + + /* USB related */ + struct usb2_port_config usb2_ports[CONFIG_SOC_INTEL_USB2_DEV_MAX]; + struct usb3_port_config usb3_ports[CONFIG_SOC_INTEL_USB3_DEV_MAX]; + uint8_t usb2_port_reset_msg_en[CONFIG_SOC_INTEL_USB2_DEV_MAX]; + /* Wake Enable Bitmap for USB2 ports */ + uint16_t usb2_wake_enable_bitmap; + /* Wake Enable Bitmap for USB3 ports */ + uint16_t usb3_wake_enable_bitmap; + /* Program OC pins for TCSS */ + struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS]; + uint8_t tbt_pcie_port_disable[4]; + uint8_t tcss_cap_policy[4]; + /* Validate TBT firmware authenticated and loaded into IMR */ + bool tbt_authentication; + + /* Audio related */ + uint8_t pch_hda_dsp_enable; + + /* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */ + enum { + HDA_TMODE_2T = 0, + HDA_TMODE_4T = 2, + HDA_TMODE_8T = 3, + HDA_TMODE_16T = 4, + } pch_hda_idisp_link_tmode; + + /* iDisp-Link Freq 4: 96MHz, 3: 48MHz. */ + enum { + HDA_LINKFREQ_48MHZ = 3, + HDA_LINKFREQ_96MHZ = 4, + } pch_hda_idisp_link_frequency; + + bool pch_hda_idisp_codec_enable; + + struct pcie_rp_config pcie_rp[CONFIG_MAX_ROOT_PORTS]; + uint8_t pcie_clk_config_flag[CONFIG_MAX_PCIE_CLOCK_SRC]; + + /* Gfx related */ + enum { + IGD_SM_0MB = 0x00, + IGD_SM_32MB = 0x01, + IGD_SM_64MB = 0x02, + IGD_SM_96MB = 0x03, + IGD_SM_128MB = 0x04, + IGD_SM_160MB = 0x05, + IGD_SM_4MB = 0xF0, + IGD_SM_8MB = 0xF1, + IGD_SM_12MB = 0xF2, + IGD_SM_16MB = 0xF3, + IGD_SM_20MB = 0xF4, + IGD_SM_24MB = 0xF5, + IGD_SM_28MB = 0xF6, + IGD_SM_36MB = 0xF8, + IGD_SM_40MB = 0xF9, + IGD_SM_44MB = 0xFA, + IGD_SM_48MB = 0xFB, + IGD_SM_52MB = 0xFC, + IGD_SM_56MB = 0xFD, + IGD_SM_60MB = 0xFE, + } IgdDvmt50PreAlloc; + uint8_t skip_ext_gfx_scan; + + /* CNVi WiFi Core Enable/Disable */ + bool cnvi_wifi_core; + + /* CNVi BT Core Enable/Disable */ + bool cnvi_bt_core; + + /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ + bool cnvi_bt_audio_offload; + + /* In-Band ECC (IBECC) configuration */ + struct ibecc_config ibecc; + + /* HeciEnabled decides the state of Heci1 at end of boot + * Setting to 0 (default) disables Heci1 and hides the device from OS */ + uint8_t HeciEnabled; + + /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ + uint8_t eist_enable; + + /* Enable C6 DRAM */ + uint8_t enable_c6dram; + uint8_t PmTimerDisabled; + /* + * SerialIO device mode selection: + * PchSerialIoDisabled, + * PchSerialIoPci, + * PchSerialIoHidden, + * PchSerialIoLegacyUart, + * PchSerialIoSkipInit + */ + uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX]; + uint8_t SerialIoI3cMode[CONFIG_SOC_INTEL_I3C_DEV_MAX]; + uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX]; + /* + * GSPIn Default Chip Select Mode: + * 0:Hardware Mode, + * 1:Software Mode + */ + uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + /* + * GSPIn Default Chip Select State: + * 0: Low, + * 1: High + */ + uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + + /* Debug interface selection */ + enum { + DEBUG_INTERFACE_RAM = (1 << 0), + DEBUG_INTERFACE_UART_8250IO = (1 << 1), + DEBUG_INTERFACE_USB3 = (1 << 3), + DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4), + DEBUG_INTERFACE_TRACEHUB = (1 << 5), + } debug_interface_flag; + + /* + * These GPIOs will be programmed by the IOM to handle biasing of the + * Type-C aux (SBU) signals when certain alternate modes are used. + * `pad_auxn_dc` should be assigned to the GPIO pad providing negative + * bias (name usually contains `AUXN_DC` or `AUX_N`); similarly, + * `pad_auxp_dc` should be assigned to the GPIO providing positive bias + * (name often contains `AUXP_DC` or `_AUX_P`). + */ + struct typec_aux_bias_pads typec_aux_bias_pads[MAX_TYPE_C_PORTS]; + + /* + * SOC Aux orientation override: + * This is a bitfield that corresponds to up to 4 TCSS ports on LNL. + * Even numbered bits (0, 2, 4, 6) control the retimer being handled by SOC. + * Odd numbered bits (1, 3, 5, 7) control the orientation of the physical aux lines + * on the motherboard. + */ + uint16_t tcss_aux_ori; + + /* Connect Topology Command timeout value */ + uint16_t itbt_connect_topology_timeout_in_ms; + + /* + * Override GPIO PM configuration: + * 0: Use FSP default GPIO PM program, + * 1: coreboot to override GPIO PM program + */ + uint8_t gpio_override_pm; + + /* + * GPIO PM configuration: 0 to disable, 1 to enable power gating + * Bit 6-7: Reserved + * Bit 5: MISCCFG_GPSIDEDPCGEN + * Bit 4: MISCCFG_GPRCOMPCDLCGEN + * Bit 3: MISCCFG_GPRTCDLCGEN + * Bit 2: MISCCFG_GSXLCGEN + * Bit 1: MISCCFG_GPDPCGEN + * Bit 0: MISCCFG_GPDLCGEN + */ + uint8_t gpio_pm[TOTAL_GPIO_COMM]; + + /* DP config */ + /* + * Port config + * 0:Disabled, 1:eDP, 2:MIPI DSI + */ + uint8_t ddi_port_A_config; + uint8_t ddi_port_B_config; + + /* Enable(1)/Disable(0) HPD/DDC */ + uint8_t ddi_ports_config[DDI_PORT_COUNT]; + + /* Hybrid storage mode enable (1) / disable (0) + * This mode makes FSP detect Optane and NVME and set PCIe lane mode + * accordingly */ + uint8_t HybridStorageMode; + + /* + * Override CPU flex ratio value: + * CPU ratio value controls the maximum processor non-turbo ratio. + * Valid Range 0 to 63. + * + * In general descriptor provides option to set default cpu flex ratio. + * Default cpu flex ratio is 0 ensures booting with non-turbo max frequency. + * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0. + * + * Only override CPU flex ratio if don't want to boot with non-turbo max. + */ + uint8_t cpu_ratio_override; + + /* + * Enable(0)/Disable(1) DMI Power Optimizer on PCH side. + * Default 0. Setting this to 1 disables the DMI Power Optimizer. + */ + uint8_t DmiPwrOptimizeDisable; + + /* + * Enable(1)/Disable(0) CPU Replacement check. + * Default 0. Setting this to 1 to check CPU replacement. + */ + uint8_t cpu_replacement_check; + + /* ISA Serial Base selection. */ + enum { + ISA_SERIAL_BASE_ADDR_3F8, + ISA_SERIAL_BASE_ADDR_2F8, + } IsaSerialUartBase; + + /* USB overcurrent pin mapping */ + uint8_t pch_usb_oc_enable; +}; + +typedef struct soc_intel_lnl_dev_config config_t; +#endif diff --git a/src/soc/intel/lnl_dev/espi.c b/src/soc/intel/lnl_dev/espi.c new file mode 100644 index 0000000..4928f17 --- /dev/null +++ b/src/soc/intel/lnl_dev/espi.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci.h> +#include <pc80/isa-dma.h> +#include <pc80/i8259.h> +#include <arch/ioapic.h> +#include <intelblocks/itss.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> +#include <soc/espi.h> +#include <soc/iomap.h> +#include <soc/irq.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <soc/soc_chip.h> + +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) +{ + const config_t *config = config_of_soc(); + + gen_io_dec[0] = config->gen1_dec; + gen_io_dec[1] = config->gen2_dec; + gen_io_dec[2] = config->gen3_dec; + gen_io_dec[3] = config->gen4_dec; +} + +#if ENV_RAMSTAGE +void lpc_soc_init(struct device *dev) +{ + /* Legacy initialization */ + isa_dma_init(); + pch_misc_init(); + + /* Enable CLKRUN_EN for power gating ESPI */ + lpc_enable_pci_clk_cntl(); + + /* Set ESPI Serial IRQ mode */ + if (CONFIG(SERIRQ_CONTINUOUS_MODE)) + lpc_set_serirq_mode(SERIRQ_CONTINUOUS); + else + lpc_set_serirq_mode(SERIRQ_QUIET); + + /* Interrupt configuration */ + pch_enable_ioapic(); + pch_pirq_init(); + setup_i8259(); + i8259_configure_irq_trigger(9, 1); +} +#endif diff --git a/src/soc/intel/lnl_dev/include/soc/gpe.h b/src/soc/intel/lnl_dev/include/soc/gpe.h new file mode 100644 index 0000000..ac69788 --- /dev/null +++ b/src/soc/intel/lnl_dev/include/soc/gpe.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_LNL_GPE_H_ +#define _SOC_INTEL_LNL_GPE_H_ + +#include <intelpch/gpe.h> + +#endif /* _SOC_INTEL_LNL_GPE_H_ */ diff --git a/src/soc/intel/lnl_dev/include/soc/meminit.h b/src/soc/intel/lnl_dev/include/soc/meminit.h new file mode 100644 index 0000000..7012144 --- /dev/null +++ b/src/soc/intel/lnl_dev/include/soc/meminit.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_LNL_MEMINIT_H_ +#define _SOC_INTEL_LNL_MEMINIT_H_ + +#include <types.h> +#include <fsp/soc_binding.h> +#include <intelblocks/meminit.h> + +enum mem_type { + MEM_TYPE_LP5X, +}; + +struct lpx_dq { + uint8_t dq0[BITS_PER_BYTE]; + uint8_t dq1[BITS_PER_BYTE]; +}; + +struct lpx_dqs { + uint8_t dqs0; + uint8_t dqs1; +}; + +struct lpx_dq_map { + struct lpx_dq ddr0; + struct lpx_dq ddr1; + struct lpx_dq ddr2; + struct lpx_dq ddr3; + struct lpx_dq ddr4; + struct lpx_dq ddr5; + struct lpx_dq ddr6; + struct lpx_dq ddr7; +}; + +struct lpx_dqs_map { + struct lpx_dqs ddr0; + struct lpx_dqs ddr1; + struct lpx_dqs ddr2; + struct lpx_dqs ddr3; + struct lpx_dqs ddr4; + struct lpx_dqs ddr5; + struct lpx_dqs ddr6; + struct lpx_dqs ddr7; +}; + +struct mem_lp5x_config { + uint8_t ccc_config; +}; + +struct rcomp { + /* + * Rcomp resistor value. This values represents the resistance in + * ohms of the rcomp resistor attached to the DDR_COMP pin on the SoC. + * + * Note: If mainboard users don't want to override rcomp related settings + * then associated rcomp UPDs will have its default value. + */ + uint16_t resistor; + /* Rcomp target values. */ + uint16_t targets[5]; +}; + +struct mb_cfg { + enum mem_type type; + struct rcomp rcomp; + union { + /* + * DQ CPU<>DRAM map: + * Index of the array represents DQ# on the CPU and the value represents DQ# on + * the DRAM part. + */ + uint8_t dq_map[CONFIG_DATA_BUS_WIDTH]; + struct lpx_dq_map lpx_dq_map; + }; + + union { + /* + * DQS CPU<>DRAM map: + * Index of the array represents DQS# on the CPU and the value represents DQS# + * on the DRAM part. + */ + uint8_t dqs_map[CONFIG_DATA_BUS_WIDTH/BITS_PER_BYTE]; + struct lpx_dqs_map lpx_dqs_map; + }; + + struct mem_lp5x_config lp5x_config; + + /* Early Command Training Enable/Disable Control */ + bool ect; + + /* Board type */ + uint8_t UserBd; + + /* Command Mirror */ + uint8_t CmdMirror; + + /* Enable/Disable TxDqDqs Retraining for Lp4/Lp5/DDR */ + uint8_t LpDdrDqDqsReTraining; +}; + +void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, + const struct mem_spd *spd_info, bool half_populated); + +#endif /* _SOC_INTEL_LNL_MEMINIT_H_ */ diff --git a/src/soc/intel/lnl_dev/include/soc/msr.h b/src/soc/intel/lnl_dev/include/soc/msr.h new file mode 100644 index 0000000..0764720 --- /dev/null +++ b/src/soc/intel/lnl_dev/include/soc/msr.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_LNL_MSR_H_ +#define _SOC_INTEL_LNL_MSR_H_ + +#include <intelblocks/msr.h> + +#define MSR_BIOS_DONE 0x151 +#define ENABLE_IA_UNTRUSTED (1 << 0) +#define MSR_VR_MISC_CONFIG2 0x636 + +#endif //_SOC_INTEL_LNL_MSR_H_ diff --git a/src/soc/intel/lnl_dev/include/soc/pmc.h b/src/soc/intel/lnl_dev/include/soc/pmc.h new file mode 100644 index 0000000..68dffa8 --- /dev/null +++ b/src/soc/intel/lnl_dev/include/soc/pmc.h @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_LNL_PMC_H_ +#define _SOC_INTEL_LNL_PMC_H_ +#include <device/device.h> + +extern struct device_operations pmc_ops; + +/* PCI Configuration Space (D31:F2): PMC */ +#define PWRMBASE 0x10 +#define ABASE 0x20 + +/* Memory mapped IO registers in PMC */ +#define GEN_PMCON_A 0x1020 +#define DC_PP_DIS (1 << 30) +#define DSX_PP_DIS (1 << 29) +#define AG3_PP_EN (1 << 28) +#define SX_PP_EN (1 << 27) +#define ALLOW_ICLK_PLL_SD_INC0 (1 << 26) +#define GBL_RST_STS (1 << 24) +#define DISB (1 << 23) +#define ALLOW_OPI_PLL_SD_INC0 (1 << 22) +#define MEM_SR (1 << 21) +#define ALLOW_SPXB_CG_INC0 (1 << 20) +#define ALLOW_L1LOW_C0 (1 << 19) +#define MS4V (1 << 18) +#define ALLOW_L1LOW_OPI_ON (1 << 17) +#define SUS_PWR_FLR (1 << 16) +#define PME_B0_S5_DIS (1 << 15) +#define PWR_FLR (1 << 14) +#define ALLOW_L1LOW_BCLKREQ_ON (1 << 13) +#define DIS_SLP_X_STRCH_SUS_UP (1 << 12) +#define SLP_S3_MIN_ASST_WDTH_MASK (3 << 10) +#define SLP_S3_MIN_ASST_WDTH_60USEC (0 << 10) +#define SLP_S3_MIN_ASST_WDTH_1MS (1 << 10) +#define SLP_S3_MIN_ASST_WDTH_50MS (2 << 10) +#define SLP_S3_MIN_ASST_WDTH_2S (3 << 10) +#define HOST_RST_STS (1 << 9) +#define ESPI_SMI_LOCK (1 << 8) +#define S4MAW_MASK (3 << 4) +#define S4MAW_1S (1 << 4) +#define S4MAW_2S (2 << 4) +#define S4MAW_3S (3 << 4) +#define S4MAW_4S (0 << 4) +#define S4ASE (1 << 3) +#define PER_SMI_SEL_MASK (3 << 1) +#define SMI_RATE_64S (0 << 1) +#define SMI_RATE_32S (1 << 1) +#define SMI_RATE_16S (2 << 1) +#define SMI_RATE_8S (3 << 1) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) + +#define GEN_PMCON_B 0x1024 +#define ST_FDIS_LOCK (1 << 21) +#define SLP_STR_POL_LOCK (1 << 18) +#define ACPI_BASE_LOCK (1 << 17) +#define PM_DATA_BAR_DIS (1 << 16) +#define WOL_EN_OVRD (1 << 13) +#define BIOS_PCI_EXP_EN (1 << 10) +#define PWRBTN_LVL (1 << 9) +#define SMI_LOCK (1 << 4) +#define RTC_BATTERY_DEAD (1 << 2) + +#define ETR 0x1048 +#define CF9_LOCK (1 << 31) +#define CF9_GLB_RST (1 << 20) + +#define SSML 0x104C +#define SSML_SSL_DS (0 << 0) +#define SSML_SSL_EN (1 << 0) + +#define SSMC 0x1050 +#define SSMC_SSMS (1 << 0) + +#define SSMD 0x1054 +#define SSMD_SSD_MASK (0xffff << 0) + +#define PRSTS 0x1810 + +#define PM_CFG 0x1818 +#define PM_CFG_DBG_MODE_LOCK (1 << 27) +#define PM_CFG_XRAM_READ_DISABLE (1 << 22) + +#define S3_PWRGATE_POL 0x1828 +#define S3DC_GATE_SUS (1 << 1) +#define S3AC_GATE_SUS (1 << 0) + +#define S4_PWRGATE_POL 0x182c +#define S4DC_GATE_SUS (1 << 1) +#define S4AC_GATE_SUS (1 << 0) + +#define S5_PWRGATE_POL 0x1830 +#define S5DC_GATE_SUS (1 << 15) +#define S5AC_GATE_SUS (1 << 14) + +#define DSX_CFG 0x1834 +#define REQ_CNV_NOWAKE_DSX (1 << 4) +#define REQ_BATLOW_DSX (1 << 3) +#define DSX_EN_WAKE_PIN (1 << 2) +#define DSX_DIS_AC_PRESENT_PD (1 << 1) +#define DSX_EN_LAN_WAKE_PIN (1 << 0) +#define DSX_CFG_MASK (0x1f << 0) + +#define PMSYNC_TPR_CFG 0x18C4 +#define PCH2CPU_TPR_CFG_LOCK (1 << 31) +#define PCH2CPU_TT_EN (1 << 26) + +#define PCH_PWRM_ACPI_TMR_CTL 0x18FC +#define ACPI_TIM_DIS (1 << 1) +#define GPIO_GPE_CFG 0x1920 +#define GPE0_DWX_MASK 0xf +#define GPE0_DW_SHIFT(x) (4*(x)) + +#define PMC_GPP_V 0x0 +#define PMC_GPP_C 0x1 +#define PMC_GPP_A 0x2 +#define PMC_GPP_E 0x3 +#define PMC_GPP_H 0x4 +#define PMC_GPP_F 0x5 +#define PMC_GPP_S 0x6 +#define PMC_GPP_B 0x7 +#define PMC_GPP_D 0x8 + +#define GBLRST_CAUSE0 0x1924 +#define GBLRST_CAUSE0_THERMTRIP (1 << 5) +#define GBLRST_CAUSE1 0x1928 +#define HPR_CAUSE0 0x192C +#define HPR_CAUSE0_MI_HRPD (1 << 10) +#define HPR_CAUSE0_MI_HRPC (1 << 9) +#define HPR_CAUSE0_MI_HR (1 << 8) + +#define SLP_S0_RES 0x193c + +#define CPPMVRIC 0x1B1C +#define XTALSDQDIS (1 << 22) + +#define IRQ_REG ACTL +#define SCI_IRQ_ADJUST 0 +#define ACTL 0x1BD8 +#define PWRM_EN (1 << 8) +#define ACPI_EN (1 << 7) +#define SCI_IRQ_SEL (7 << 0) + +#define SCIS_IRQ9 0 +#define SCIS_IRQ10 1 +#define SCIS_IRQ11 2 +#define SCIS_IRQ20 4 +#define SCIS_IRQ21 5 +#define SCIS_IRQ22 6 +#define SCIS_IRQ23 7 +#endif //_SOC_INTEL_LNL_PMC_H_ diff --git a/src/soc/intel/lnl_dev/include/soc/romstage.h b/src/soc/intel/lnl_dev/include/soc/romstage.h new file mode 100755 index 0000000..aa70744 --- /dev/null +++ b/src/soc/intel/lnl_dev/include/soc/romstage.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_LNL_ROMSTAGE_H_ +#define _SOC_INTEL_LNL_ROMSTAGE_H_ + +#include <fsp/api.h> +#include <stddef.h> +#include <soc/soc_chip.h> + +void soc_die_early_sa_init(void); +void mainboard_update_premem_soc_chip_config(struct soc_intel_lnl_dev_config *config); +void mainboard_memory_init_params(FSPM_UPD *memupd); +void systemagent_early_init(void); + +/* Board type */ +enum board_type { + BOARD_TYPE_MOBILE = 0, + BOARD_TYPE_DESKTOP = 1, + BOARD_TYPE_ULT_ULX = 5, + BOARD_TYPE_SERVER = 7 +}; + +#endif /* _SOC_INTEL_LNL_ROMSTAGE_H_ */ diff --git a/src/soc/intel/lnl_dev/include/soc/soc_chip.h b/src/soc/intel/lnl_dev/include/soc/soc_chip.h new file mode 100644 index 0000000..f318066 --- /dev/null +++ b/src/soc/intel/lnl_dev/include/soc/soc_chip.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_LNL_SOC_CHIP_H_ +#define _SOC_INTEL_LNL_SOC_CHIP_H_ + +#include "../../chip.h" + +#endif /* _SOC_INTEL_LNL_SOC_CHIP_H_ */ diff --git a/src/soc/intel/lnl_dev/include/soc/soc_info.h b/src/soc/intel/lnl_dev/include/soc/soc_info.h new file mode 100644 index 0000000..56d94a3 --- /dev/null +++ b/src/soc/intel/lnl_dev/include/soc/soc_info.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _SOC_INTEL_LNL_SOC_INFO_H_ +#define _SOC_INTEL_LNL_SOC_INFO_H_ + +#include <platform_soc_defs.h> + +enum { + NOT_DETECTED = 0, + LNLM, + PTLP, +}; + +uint8_t get_soctype(void); +uint8_t get_max_usb20_port(void); +uint8_t get_max_usb30_port(void); +uint8_t get_max_tcss_port(void); +uint8_t get_max_tbt_pcie_port(void); +uint8_t get_max_pcie_port(void); +uint8_t get_max_pcie_clock(void); +uint8_t get_max_uart_port(void); +uint8_t get_max_i2c_port(void); +uint8_t get_max_i3c_port(void); +uint8_t get_max_gspi_port(void); +#endif //_SOC_INTEL_LNL_SOC_INFO_H_ diff --git a/src/soc/intel/lnl_dev/include/soc/systemagent.h b/src/soc/intel/lnl_dev/include/soc/systemagent.h new file mode 100644 index 0000000..aeacb19 --- /dev/null +++ b/src/soc/intel/lnl_dev/include/soc/systemagent.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_LNL_SYSTEMAGENT_H_ +#define _SOC_INTEL_LNL_SYSTEMAGENT_H_ + +#include <intelblocks/systemagent.h> +#include <platform_soc_defs.h> + +/* Device 0:0.0 PCI configuration space */ + +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) + +/* MCHBAR offsets */ +#define VTDBAR 0x5410 +#define GFXVTBAR VTDBAR + +#define MCH_DDR_POWER_LIMIT_LO 0x58e0 +#define MCH_DDR_POWER_LIMIT_HI 0x58e4 +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 +#define BIOS_RESET_CPL 0x5da8 +#define IMRBASE 0x6a40 +#define IMRLIMIT 0x6a48 +#define IPUVTBAR 0x7880 +#define TBTxBAR(x) (0x7888 + (x) * 8) + +#define VTBAR_ENABLED 0x01 +#define VTBAR_MASK 0x7ffffff000ull + +static const struct sa_mmio_descriptor soc_vtd_resources[] = { + { VTDBAR, VTD_BASE_ADDRESS, VTD_BASE_SIZE, "VTDBAR" }, +}; + +#define V_P2SB_CFG_IBDF_BUS 0 +#define V_P2SB_CFG_IBDF_DEV 30 +#define V_P2SB_CFG_IBDF_FUNC 7 +#define V_P2SB_CFG_HBDF_BUS 0 +#define V_P2SB_CFG_HBDF_DEV 30 +#define V_P2SB_CFG_HBDF_FUNC 6 + +#define TPM_BASE_ADDRESS 0xFED40000 +#define TPM_SIZE (64 * KiB) +#define LT_SECURITY_BASE_ADDR 0xFED20000 +#define LT_SECURITY_SIZE (384 * KiB) +#define APIC_SIZE (1 * MiB) + +#define MASK_PCIEXBAR_LENGTH 0x0000000E // bits [3:1] +#define PCIEXBAR_LENGTH_LSB 1 // used to shift right + +#define DSM_BASE_ADDR_REG 0xB0 +#define MASK_DSM_LENGTH 0xFF00 // [15:8] +#define MASK_DSM_LENGTH_LSB 8 // used to shift right +#define MASK_GSM_LENGTH 0xC0 // [7:6] +#define MASK_GSM_LENGTH_LSB 6 // used to shift right +#define DPR_REG 0x5C +#define MASK_DPR_LENGTH 0xFF0 // [11:4] +#define MASK_DPR_LENGTH_LSB 4 // used to shift right + +uint64_t get_mmcfg_size(const struct device *dev); +uint64_t get_dsm_size(const struct device *dev); +uint64_t get_gsm_size(const struct device *dev); +uint64_t get_dpr_size(const struct device *dev); +#endif //_SOC_INTEL_LNL_SYSTEMAGENT_H_ diff --git a/src/soc/intel/lnl_dev/lunarlake/chipset.cb b/src/soc/intel/lnl_dev/lunarlake/chipset.cb new file mode 100644 index 0000000..b422c98 --- /dev/null +++ b/src/soc/intel/lnl_dev/lunarlake/chipset.cb @@ -0,0 +1,149 @@ +chip soc/intel/lnl_dev + + device cpu_cluster 0 on end + + register "power_limits_config[LNL_M_POWER_LIMITS]" = "{ + .tdp_pl1_override = 9, + .tdp_pl2_override = 30, + }" + + # NOTE: if any variant wants to override this value, use the same format + # as register "common_soc_config.pch_thermal_trip" = "value", instead of + # putting it under register "common_soc_config" in overridetree.cb file. + #FIXME: update value for LNL + register "common_soc_config.pch_thermal_trip" = "100" + + device domain 0 on + device pci 00.0 alias system_agent on end + device pci 02.0 alias igpu on end + device pci 04.0 alias dtt off end + device pci 05.0 alias ipu off end + device pci 07.0 alias tbt_pcie_rp0 off + chip soc/intel/common/block/usb4 + use tcss_dma0 as usb4_port + device generic 0 on end + end + end + device pci 07.1 alias tbt_pcie_rp1 off + chip soc/intel/common/block/usb4 + use tcss_dma0 as usb4_port + device generic 1 on end + end + end + device pci 07.2 alias tbt_pcie_rp2 off + chip soc/intel/common/block/usb4 + use tcss_dma1 as usb4_port + device generic 0 on end + end + end + device pci 0a.0 alias crashlog off end + device pci 0b.0 alias npu on end + device pci 0d.0 alias tcss_xhci off + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias tcss_root_hub off + chip drivers/usb/acpi + device usb 3.0 alias tcss_usb3_port0 off end + end + chip drivers/usb/acpi + device usb 3.1 alias tcss_usb3_port1 off end + end + chip drivers/usb/acpi + device usb 3.2 alias tcss_usb3_port2 off end + end + end + end + end + device pci 0d.2 alias tcss_dma0 off end + device pci 0d.3 alias tcss_dma1 off end + device pci 10.0 alias thc0 off end + device pci 10.1 alias thc1 off end + device pci 11.0 alias i3c off end + device pci 11.2 alias i3c1 off end + device pci 12.0 alias ish off end + device pci 12.1 alias p2sb2 hidden end + device pci 12.6 alias gspi2 off end + device pci 12.7 alias ufs off end + device pci 13.0 alias heci_1 off end + device pci 13.1 alias heci_2 off end + device pci 13.2 alias heci_3 off end + device pci 14.0 alias xhci on + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias xhci_root_hub off + chip drivers/usb/acpi + device usb 2.0 alias usb2_port1 off end + end + chip drivers/usb/acpi + device usb 2.1 alias usb2_port2 off end + end + chip drivers/usb/acpi + device usb 2.2 alias usb2_port3 off end + end + chip drivers/usb/acpi + device usb 2.3 alias usb2_port4 off end + end + chip drivers/usb/acpi + device usb 2.4 alias usb2_port5 off end + end + chip drivers/usb/acpi + device usb 2.5 alias usb2_port6 off end + end + chip drivers/usb/acpi + device usb 2.6 alias usb2_port7 off end + end + chip drivers/usb/acpi + device usb 2.7 alias usb2_port8 off end + end + chip drivers/usb/acpi + device usb 2.8 alias usb2_port9 off end + end + chip drivers/usb/acpi + device usb 2.9 alias usb2_port10 off end + end + chip drivers/usb/acpi + device usb 3.0 alias usb3_port1 off end + end + chip drivers/usb/acpi + device usb 3.1 alias usb3_port2 off end + end + end + end + end + device pci 14.2 alias shared_sram off end + device pci 14.3 alias cnvi_wifi on end + device pci 14.7 alias cnvi_bluetooth on end + device pci 15.0 alias i2c0 off end + device pci 15.1 alias i2c1 off end + device pci 15.2 alias i2c2 off end + device pci 15.3 alias i2c3 off end + device pci 16.0 alias heci1 on end + device pci 16.1 alias heci2 off end + device pci 16.4 alias heci3 off end + device pci 16.5 alias heci4 off end + device pci 18.0 alias eheci1 off end + device pci 18.1 alias eheci2 off end + device pci 18.2 alias eheci3 off end + device pci 19.0 alias i2c4 off end + device pci 19.1 alias i2c5 off end + device pci 19.2 alias uart2 off end + device pci 1c.0 alias pcie_rp1 off end + device pci 1c.1 alias pcie_rp2 off end + device pci 1c.2 alias pcie_rp3 off end + device pci 1c.3 alias pcie_rp4 off end + device pci 1c.4 alias pcie_rp5 off end + device pci 1c.5 alias pcie_rp6 off end + device pci 1e.0 alias uart0 off end + device pci 1e.1 alias uart1 off end + device pci 1e.2 alias gspi0 off end + device pci 1e.3 alias gspi1 off end + device pci 1f.0 alias soc_espi on end + device pci 1f.1 alias p2sb hidden end + device pci 1f.2 alias pmc hidden end + device pci 1f.3 alias hda off end + device pci 1f.4 alias smbus off end + device pci 1f.5 alias fast_spi on end + device pci 1f.6 alias gbe off end + device pci 1f.7 alias npk off end + end +end diff --git a/src/soc/intel/lnl_dev/lunarlake/meminit.c b/src/soc/intel/lnl_dev/lunarlake/meminit.c new file mode 100644 index 0000000..39e3aac --- /dev/null +++ b/src/soc/intel/lnl_dev/lunarlake/meminit.c @@ -0,0 +1,175 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <fsp/util.h> +#include <soc/meminit.h> +#include <string.h> + +#define LPX_PHYSICAL_CH_WIDTH 16 +#define LPX_CHANNELS CHANNEL_COUNT(LPX_PHYSICAL_CH_WIDTH) + +static void set_rcomp_config(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg) +{ + if (mb_cfg->rcomp.resistor != 0) + mem_cfg->RcompResistor = mb_cfg->rcomp.resistor; + + for (size_t i = 0; i < ARRAY_SIZE(mem_cfg->RcompTarget); i++) { + if (mb_cfg->rcomp.targets[i] != 0) + mem_cfg->RcompTarget[i] = mb_cfg->rcomp.targets[i]; + } +} + +static void meminit_lp5x(FSP_M_CONFIG *mem_cfg, const struct mem_lp5x_config *lp5x_config) +{ + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->Lp5CccConfig = lp5x_config->ccc_config; +} + +static const struct soc_mem_cfg soc_mem_cfg[] = { + [MEM_TYPE_LP5X] = { + .num_phys_channels = LPX_CHANNELS, + .phys_to_mrc_map = { + [0] = 0, + [1] = 1, + [2] = 2, + [3] = 3, + [4] = 4, + [5] = 5, + [6] = 6, + [7] = 7, + }, + .md_phy_masks = { + /* + * Physical channels 0, 1, 2 and 3 are populated in case of + * half-populated configurations. + */ + .half_channel = BIT(0) | BIT(1) | BIT(2) | BIT(3), + /* LP5x does not support mixed topologies. */ + }, + }, +}; + +static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data) +{ + uint64_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = { + [0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, }, + [1] = { &mem_cfg->MemorySpdPtr010, &mem_cfg->MemorySpdPtr011, }, + [2] = { &mem_cfg->MemorySpdPtr020, &mem_cfg->MemorySpdPtr021, }, + [3] = { &mem_cfg->MemorySpdPtr030, &mem_cfg->MemorySpdPtr031, }, + [4] = { &mem_cfg->MemorySpdPtr100, &mem_cfg->MemorySpdPtr101, }, + [5] = { &mem_cfg->MemorySpdPtr110, &mem_cfg->MemorySpdPtr111, }, + [6] = { &mem_cfg->MemorySpdPtr120, &mem_cfg->MemorySpdPtr121, }, + [7] = { &mem_cfg->MemorySpdPtr130, &mem_cfg->MemorySpdPtr131, }, + }; + uint8_t *disable_channel_upds[MRC_CHANNELS] = { + &mem_cfg->DisableMc0Ch0, + &mem_cfg->DisableMc0Ch1, + &mem_cfg->DisableMc0Ch2, + &mem_cfg->DisableMc0Ch3, + &mem_cfg->DisableMc1Ch0, + &mem_cfg->DisableMc1Ch1, + &mem_cfg->DisableMc1Ch2, + &mem_cfg->DisableMc1Ch3, + }; + size_t ch, dimm; + + mem_cfg->MemorySpdDataLen = data->spd_len; + + for (ch = 0; ch < MRC_CHANNELS; ch++) { + uint8_t *disable_channel_ptr = disable_channel_upds[ch]; + bool enable_channel = 0; + + for (dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) { + uint64_t *spd_ptr = spd_upds[ch][dimm]; + + *spd_ptr = data->spd[ch][dimm]; + if (*spd_ptr) + enable_channel = 1; + } + *disable_channel_ptr = !enable_channel; + } +} + +static void mem_init_dq_dqs_upds(void *upds[MRC_CHANNELS], const void *map, size_t upd_size, + const struct mem_channel_data *data, bool auto_detect) +{ + size_t i; + + for (i = 0; i < MRC_CHANNELS; i++, map += upd_size) { + if (auto_detect || + !channel_is_populated(i, MRC_CHANNELS, data->ch_population_flags)) + memset(upds[i], 0, upd_size); + else + memcpy(upds[i], map, upd_size); + } +} + +static void mem_init_dq_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data, + const struct mb_cfg *mb_cfg, bool auto_detect) +{ + void *dq_upds[MRC_CHANNELS] = { + &mem_cfg->DqMapCpu2DramMc0Ch0, + &mem_cfg->DqMapCpu2DramMc0Ch1, + &mem_cfg->DqMapCpu2DramMc0Ch2, + &mem_cfg->DqMapCpu2DramMc0Ch3, + &mem_cfg->DqMapCpu2DramMc1Ch0, + &mem_cfg->DqMapCpu2DramMc1Ch1, + &mem_cfg->DqMapCpu2DramMc1Ch2, + &mem_cfg->DqMapCpu2DramMc1Ch3, + }; + + const size_t upd_size = sizeof(mem_cfg->DqMapCpu2DramMc0Ch0); + + _Static_assert(sizeof(mem_cfg->DqMapCpu2DramMc0Ch0) == CONFIG_MRC_CHANNEL_WIDTH, + "Incorrect DQ UPD size!"); + + mem_init_dq_dqs_upds(dq_upds, mb_cfg->dq_map, upd_size, data, auto_detect); +} + +static void mem_init_dqs_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data, + const struct mb_cfg *mb_cfg, bool auto_detect) +{ + void *dqs_upds[MRC_CHANNELS] = { + &mem_cfg->DqsMapCpu2DramMc0Ch0, + &mem_cfg->DqsMapCpu2DramMc0Ch1, + &mem_cfg->DqsMapCpu2DramMc0Ch2, + &mem_cfg->DqsMapCpu2DramMc0Ch3, + &mem_cfg->DqsMapCpu2DramMc1Ch0, + &mem_cfg->DqsMapCpu2DramMc1Ch1, + &mem_cfg->DqsMapCpu2DramMc1Ch2, + &mem_cfg->DqsMapCpu2DramMc1Ch3, + }; + + const size_t upd_size = sizeof(mem_cfg->DqsMapCpu2DramMc0Ch0); + + _Static_assert(sizeof(mem_cfg->DqsMapCpu2DramMc0Ch0) == CONFIG_MRC_CHANNEL_WIDTH / 8, + "Incorrect DQS UPD size!"); + + mem_init_dq_dqs_upds(dqs_upds, mb_cfg->dqs_map, upd_size, data, auto_detect); +} + +void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, + const struct mem_spd *spd_info, bool half_populated) +{ + struct mem_channel_data data; + bool dq_dqs_auto_detect = false; + FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; + + mem_cfg->ECT = mb_cfg->ect; + mem_cfg->UserBd = mb_cfg->UserBd; + set_rcomp_config(mem_cfg, mb_cfg); + + switch (mb_cfg->type) { + case MEM_TYPE_LP5X: + meminit_lp5x(mem_cfg, &mb_cfg->lp5x_config); + break; + default: + die("Unsupported memory type(%d)\n", mb_cfg->type); + } + + mem_populate_channel_data(memupd, &soc_mem_cfg[mb_cfg->type], spd_info, + half_populated, &data); + mem_init_spd_upds(mem_cfg, &data); + mem_init_dq_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect); + mem_init_dqs_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect); +} diff --git a/src/soc/intel/lnl_dev/lunarlake/romstage/fsp_params.c b/src/soc/intel/lnl_dev/lunarlake/romstage/fsp_params.c new file mode 100755 index 0000000..2fa9736 --- /dev/null +++ b/src/soc/intel/lnl_dev/lunarlake/romstage/fsp_params.c @@ -0,0 +1,395 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <console/console.h> +#include <cpu/intel/cpu_ids.h> +#include <cpu/x86/msr.h> +#include <device/device.h> +#include <fsp/fsp_debug_event.h> +#include <fsp/util.h> +#include <intelblocks/cpulib.h> +#include <intelblocks/pcie_rp.h> +#include <option.h> +#include <gpio_soc_defs.h> +#include <soc/iomap.h> +#include <soc/msr.h> +#include <soc/pci_devs.h> +#include <soc/pcie.h> +#include <soc/romstage.h> +#include <soc/soc_chip.h> +#include <soc/soc_info.h> +#include <string.h> +#include <drivers/wifi/generic/wifi.h> +#include <cpu/intel/common/common.h> + +#define FSP_CLK_NOTUSED 0xFF +#define FSP_CLK_LAN 0x70 +#define FSP_CLK_FREE_RUNNING 0x80 + +struct soc_intel_lnl_dev_config dev_cfg; + +__weak void mainboard_update_premem_soc_chip_config( + struct soc_intel_lnl_dev_config *config) +{ + /* Override settings per board. */ +} + +static void fill_fspm_cnvi_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_lnl_dev_config *config) +{ + /* CNVi DDR RFI Mitigation */ + const struct device_path path[] = { + { .type = DEVICE_PATH_PCI, .pci.devfn = PCI_DEVFN_CNVI_WIFI }, + { .type = DEVICE_PATH_GENERIC, .generic.id = 0 } }; + const struct device *dev = find_dev_nested_path(pci_root_bus(), path, + ARRAY_SIZE(path)); + if (is_dev_enabled(dev)) + m_cfg->CnviDdrRfim = wifi_generic_cnvi_ddr_rfim_enabled(dev); + m_cfg->CnviDdrRfim = 1; +} + +static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, + const struct pcie_rp_config *cfg, size_t cfg_count) +{ + size_t i; + static unsigned int clk_req_mapping = 0; + + for (i = 0; i < cfg_count; i++) { + if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) { + m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING; + continue; + } + if (!(en_mask & BIT(i))) + continue; + if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED) + continue; + if (!cfg[i].flags && cfg[i].clk_src == 0 && cfg[i].clk_req == 0) { + printk(BIOS_WARNING, "Missing root port clock structure definition\n"); + continue; + } + if (clk_req_mapping & (1 << cfg[i].clk_req)) + printk(BIOS_WARNING, "Found overlapped clkreq assignment on clk req %d\n" + , cfg[i].clk_req); + if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) { + m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req; + clk_req_mapping |= 1 << cfg[i].clk_req; + } + m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = i; + } +} + +static void fill_fspm_pcie_rp_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_lnl_dev_config *config) +{ + /* Disable all PCIe clock sources by default. And set RP irrelevant clock. */ + unsigned int i; + uint8_t max_clock = get_max_pcie_clock(); + + for (i = 0; i < max_clock; i++) { + if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING) + m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING; + else if (config->pcie_clk_config_flag[i] & PCIE_CLK_LAN) + m_cfg->PcieClkSrcUsage[i] = FSP_CLK_LAN; + else + m_cfg->PcieClkSrcUsage[i] = FSP_CLK_NOTUSED; + m_cfg->PcieClkSrcClkReq[i] = FSP_CLK_NOTUSED; + } + + /* PCIE ports */ + m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pcie_rp_table()); + pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, config->pcie_rp, + get_max_pcie_port()); +} + +static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_lnl_dev_config *config) +{ + unsigned int i; + const struct ddi_port_upds { + uint8_t *ddc; + uint8_t *hpd; + } ddi_port_upds[] = { + [DDI_PORT_A] = {&m_cfg->DdiPortADdc, &m_cfg->DdiPortAHpd}, + [DDI_PORT_B] = {&m_cfg->DdiPortBDdc, &m_cfg->DdiPortBHpd}, + [DDI_PORT_C] = {&m_cfg->DdiPortCDdc, &m_cfg->DdiPortCHpd}, + [DDI_PORT_1] = {&m_cfg->DdiPort1Ddc, &m_cfg->DdiPort1Hpd}, + [DDI_PORT_2] = {&m_cfg->DdiPort2Ddc, &m_cfg->DdiPort2Hpd}, + [DDI_PORT_3] = {&m_cfg->DdiPort3Ddc, &m_cfg->DdiPort3Hpd}, + [DDI_PORT_4] = {&m_cfg->DdiPort4Ddc, &m_cfg->DdiPort4Hpd}, + }; + m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(PCI_DEVFN_IGD); + if (m_cfg->InternalGfx) { + /* IGD is enabled, set IGD stolen size to 64MB. */ + m_cfg->IgdDvmt50PreAlloc = IGD_SM_64MB; + /* DP port config */ + m_cfg->DdiPortAConfig = config->ddi_port_A_config; + m_cfg->DdiPortBConfig = config->ddi_port_B_config; + for (i = 0; i < ARRAY_SIZE(ddi_port_upds); i++) { + *ddi_port_upds[i].ddc = !!(config->ddi_ports_config[i] & + DDI_ENABLE_DDC); + *ddi_port_upds[i].hpd = !!(config->ddi_ports_config[i] & + DDI_ENABLE_HPD); + } + } else { + /* IGD is disabled, skip IGD init in FSP. */ + m_cfg->IgdDvmt50PreAlloc = 0; + /* DP port config */ + m_cfg->DdiPortAConfig = 0; + m_cfg->DdiPortBConfig = 0; + for (i = 0; i < ARRAY_SIZE(ddi_port_upds); i++) { + *ddi_port_upds[i].ddc = 0; + *ddi_port_upds[i].hpd = 0; + } + } +} + +static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_lnl_dev_config *config) +{ + m_cfg->SaGv = config->sagv; + m_cfg->RMT = config->rmt; + m_cfg->DdrFreqLimit = 0x1900; + for (int i = 0; i < 6; i++) + m_cfg->EnableFastVmode[i] = 0; + m_cfg->MrcFastBoot = 1; +} + +static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_lnl_dev_config *config) +{ + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; + /* CpuRatio Settings */ + if (config->cpu_ratio_override) + m_cfg->CpuRatio = config->cpu_ratio_override; + else + /* Set CpuRatio to match existing MSR value */ + m_cfg->CpuRatio = (rdmsr(MSR_FLEX_RATIO).lo >> 8) & 0xff; + + m_cfg->PrmrrSize = get_valid_prmrr_size(); + /* Enable Hyper Threading */ + m_cfg->HyperThreading = 1; +} + +static void fill_fspm_security_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_lnl_dev_config *config) +{ + /* Disable BIOS Guard */ + m_cfg->BiosGuard = 0; + m_cfg->TmeEnable = CONFIG(INTEL_TME) && is_tme_supported(); +} + +static void fill_fspm_uart_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_lnl_dev_config *config) +{ + /* UART Debug Log */ + m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? + DEBUG_INTERFACE_UART_8250IO : DEBUG_INTERFACE_LPSS_SERIAL_IO; + if (CONFIG(DRIVERS_UART_8250IO)) + m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_3F8; + m_cfg->SerialIoUartDebugMode = PchSerialIoSkipInit; + m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; +} + +static void fill_fspm_ipu_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_lnl_dev_config *config) +{ + /* Image clock: disable all clocks for bypassing FSP pin mux */ + memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn)); + /* IPU */ + m_cfg->SaIpuEnable = is_devfn_enabled(PCI_DEVFN_IPU); +} + +static void fill_fspm_smbus_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_lnl_dev_config *config) +{ + m_cfg->SmbusEnable = is_devfn_enabled(PCI_DEVFN_SMBUS); +} + +static void fill_fspm_misc_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_lnl_dev_config *config) +{ + /* Skip CPU replacement check */ + m_cfg->SkipCpuReplacementCheck = !config->cpu_replacement_check; + + /* Skip GPIO configuration from FSP */ + m_cfg->GpioOverride = 0x1; + + /* Skip MBP HOB */ + m_cfg->SkipMbpHob = !CONFIG(FSP_PUBLISH_MBP_HOB); + + m_cfg->SkipExtGfxScan = config->skip_ext_gfx_scan; +} + +static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_lnl_dev_config *config) +{ + /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ + m_cfg->PchHdaEnable = is_devfn_enabled(PCI_DEVFN_HDA); + m_cfg->PchHdaDspEnable = config->pch_hda_dsp_enable; + m_cfg->PchHdaIDispLinkTmode = config->pch_hda_idisp_link_tmode; + m_cfg->PchHdaIDispLinkFrequency = config->pch_hda_idisp_link_frequency; + m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable; + /* + * All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to + * configure GPIO pads for audio. Mainboard is expected to perform all GPIO + * configuration in coreboot and hence these UPDs are set to 0 to skip FSP GPIO + * configuration for audio pads. + */ + m_cfg->PchHdaAudioLinkHdaEnable = 1; + memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); + memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable)); + memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); +} + +static void fill_fspm_ish_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_lnl_dev_config *config) +{ + m_cfg->PchIshEnable = is_devfn_enabled(PCI_DEVFN_ISH); +} + +static void fill_fspm_tcss_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_lnl_dev_config *config) +{ + int i, max_port; + + /* Tcss USB */ + m_cfg->TcssXhciEn = is_devfn_enabled(PCI_DEVFN_TCSS_XHCI); + + /* TCSS DMA */ + m_cfg->TcssDma0En = is_devfn_enabled(PCI_DEVFN_TCSS_DMA0); + m_cfg->TcssDma1En = is_devfn_enabled(PCI_DEVFN_TCSS_DMA1); + + /* Enable TCSS port */ + max_port = get_max_tcss_port(); + m_cfg->UsbTcPortEnPreMem = 0; + for (i = 0; i < max_port; i++) + if (config->tcss_ports[i].enable) + m_cfg->UsbTcPortEnPreMem |= BIT(i); + + m_cfg->TcssPort0 = (is_devfn_enabled(PCI_DEVFN_TBT0)) ? 0x7 : 0; + m_cfg->TcssPort1 = (is_devfn_enabled(PCI_DEVFN_TBT1)) ? 0x7 : 0; + m_cfg->TcssPort2 = (is_devfn_enabled(PCI_DEVFN_TBT2)) ? 0x7 : 0; +} + +static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_lnl_dev_config *config) +{ + m_cfg->VtdDisable = 1; + m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; + m_cfg->VtdBaseAddress[1] = NONGFXVT_BASE_ADDRESS; + m_cfg->VtdBaseAddress[2] = IOCVTD_BASE_ADDRESS; + + /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ + m_cfg->VmxEnable = CONFIG(ENABLE_VMX); +} + +static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_lnl_dev_config *config) +{ + /* Set debug probe type */ + m_cfg->PlatformDebugOption = CONFIG(SOC_INTEL_DEBUG_CONSENT_2); + /* CrashLog config */ + if (CONFIG(SOC_INTEL_CRASHLOG)) { + m_cfg->CpuCrashLogEnable = 1; + } +} + +static void fill_fspm_dlvrrfi_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_lnl_dev_config *config) +{ + m_cfg->DlvrRfiEnable = 1; +} + +static void fill_fspm_thermal_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_lnl_dev_config *config) +{ + /* Set TccActivationOffset */ + m_cfg->TccActivationOffset = config->tcc_offset; +} + +static void fill_fspm_ibecc_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_lnl_dev_config *config) +{ + /* In-Band ECC configuration */ + if (config->ibecc.enable) { + m_cfg->Ibecc = config->ibecc.enable; + m_cfg->IbeccOperationMode = config->ibecc.mode; + if (m_cfg->IbeccOperationMode == IBECC_MODE_PER_REGION) { + m_cfg->IbeccProtectedRegionEnable[0] = 0x1; + m_cfg->IbeccProtectedRegionBase[0] = 0x0000; + m_cfg->IbeccProtectedRegionMask[0] = 0x3FC0; + } + } +} + +static void soc_memory_init_restrict_params(FSP_M_RESTRICTED_CONFIG *rest_cfg) +{ + rest_cfg->DisableResets = 1; +} + +static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_lnl_dev_config *config) +{ + /* Override settings per board if required. */ + //mainboard_update_premem_soc_chip_config(config); + + const void (*fill_fspm_params[])(FSP_M_CONFIG *m_cfg, + const struct soc_intel_lnl_dev_config *config) = { + fill_fspm_igd_params, + fill_fspm_mrc_params, + fill_fspm_cpu_params, + fill_fspm_security_params, + fill_fspm_uart_params, + fill_fspm_ipu_params, + fill_fspm_smbus_params, + fill_fspm_misc_params, + fill_fspm_audio_params, + fill_fspm_pcie_rp_params, + fill_fspm_ish_params, + fill_fspm_tcss_params, + fill_fspm_vtd_params, + fill_fspm_trace_params, + fill_fspm_dlvrrfi_params, + fill_fspm_thermal_params, + fill_fspm_cnvi_params, + fill_fspm_ibecc_params, + }; + + for (size_t i = 0; i < ARRAY_SIZE(fill_fspm_params); i++) + fill_fspm_params[i](m_cfg, config); +} + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + const struct soc_intel_lnl_dev_config *config; + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + FSPM_ARCH2_UPD *arch_upd = &mupd->FspmArchUpd; + FSP_M_RESTRICTED_CONFIG *rest_cfg = &mupd->FspmRestrictedConfig; + if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)) { + if (CONFIG(CONSOLE_SERIAL) && CONFIG(FSP_ENABLE_SERIAL_DEBUG)) { + enum fsp_log_level log_level = fsp_map_console_log_level(); + arch_upd->FspEventHandler = (uintptr_t)((FSP_EVENT_HANDLER *) + fsp_debug_event_handler); + /* Set Serial debug message level */ + m_cfg->PcdSerialDebugLevel = log_level; + /* Set MRC debug level */ + m_cfg->SerialDebugMrcLevel = log_level; + } else { + /* Disable Serial debug message */ + m_cfg->PcdSerialDebugLevel = 0; + /* Disable MRC debug message */ + m_cfg->SerialDebugMrcLevel = 0; + } + } + config = config_of_soc(); + + soc_memory_init_params(m_cfg, config); + mainboard_memory_init_params(mupd); + soc_memory_init_restrict_params(rest_cfg); +} + +__weak void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + diff --git a/src/soc/intel/lnl_dev/lunarlake/romstage/systemagent.c b/src/soc/intel/lnl_dev/lunarlake/romstage/systemagent.c new file mode 100644 index 0000000..be8a567 --- /dev/null +++ b/src/soc/intel/lnl_dev/lunarlake/romstage/systemagent.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/systemagent.h> +#include <soc/iomap.h> +#include <soc/romstage.h> +#include <soc/systemagent.h> + +void systemagent_early_init(void) +{ + static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = { + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, + }; + + static const struct sa_mmio_descriptor soc_fixed_mch_resources[] = { + { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, + }; + + /* Set Fixed MMIO address into PCI configuration space */ + sa_set_pci_bar(soc_fixed_pci_resources, + ARRAY_SIZE(soc_fixed_pci_resources)); + /* Set Fixed MMIO address into MCH base address */ + sa_set_mch_bar(soc_fixed_mch_resources, + ARRAY_SIZE(soc_fixed_mch_resources)); + /* Enable PAM registers */ + enable_pam_region(); +} diff --git a/src/soc/intel/lnl_dev/p2sb.c b/src/soc/intel/lnl_dev/p2sb.c new file mode 100644 index 0000000..c803df8 --- /dev/null +++ b/src/soc/intel/lnl_dev/p2sb.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <intelblocks/p2sb.h> +#include <soc/iomap.h> + +void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count) +{ + uint32_t mask; + + if (count != P2SB_EP_MASK_MAX_REG) { + printk(BIOS_ERR, "Unable to program EPMASK registers\n"); + return; + } + + /* Remove the host accessing right to PSF register range. + * Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to disable Sideband + * access for PCI Root Bridge. + */ + mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26); + + ep_mask[P2SB_EP_MASK_5_REG] = mask; + + /* + * Set p2sb PCI offset EPMASK7 [31, 30] to disable Sideband + * access for Broadcast and Multicast. + */ + mask = (1 << 31) | (1 << 30); + + ep_mask[P2SB_EP_MASK_7_REG] = mask; +} + +static void p2sb_read_resources(struct device *dev) +{ + /* + * There's only one resource on the P2SB device. It's also already + * manually set to a fixed address in earlier boot stages. + * The following code makes sure that it doesn't change even the + * resource allocator is being run. + */ + mmio_range(dev, PCI_BASE_ADDRESS_0, P2SB_BAR, P2SB_SIZE); +} + +struct device_operations soc_p2sb_ops = { + .read_resources = p2sb_read_resources, + .set_resources = noop_set_resources, + .scan_bus = scan_static_bus, +}; diff --git a/src/soc/intel/lnl_dev/reset.c b/src/soc/intel/lnl_dev/reset.c new file mode 100644 index 0000000..bc5815a --- /dev/null +++ b/src/soc/intel/lnl_dev/reset.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cf9_reset.h> +#include <intelblocks/cse.h> +#include <intelblocks/pmclib.h> +#include <soc/intel/common/reset.h> + +void do_global_reset(void) +{ + /* Ask CSE to do the global reset */ + if (cse_request_global_reset()) + return; + + /* global reset if CSE fail to reset */ + pmc_global_reset_enable(1); + do_full_reset(); +} diff --git a/src/soc/intel/lnl_dev/romstage.c b/src/soc/intel/lnl_dev/romstage.c new file mode 100644 index 0000000..d666c2e --- /dev/null +++ b/src/soc/intel/lnl_dev/romstage.c @@ -0,0 +1,155 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/romstage.h> +#include <cbmem.h> +#include <console/console.h> +#include <fsp/util.h> +#include <intelblocks/cfg.h> +#include <intelblocks/cse.h> +#include <intelblocks/pmclib.h> +#include <intelblocks/smbus.h> +#include <intelblocks/thermal.h> +#include <memory_info.h> +#include <soc/intel/common/smbios.h> +#include <soc/iomap.h> +#include <soc/pm.h> +#include <soc/romstage.h> +#include <soc/soc_chip.h> +#include <timestamp.h> +#include <string.h> + +#define FSP_SMBIOS_MEMORY_INFO_GUID \ +{ \ + 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ + 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ +} + +/* Save the DIMM information for SMBIOS table 17 */ +static void save_dimm_info(void) +{ + int node, channel, dimm, dimm_max, index; + size_t hob_size; + const CONTROLLER_INFO *ctrlr_info; + const CHANNEL_INFO *channel_info; + const DIMM_INFO *src_dimm; + struct dimm_info *dest_dimm; + struct memory_info *mem_info; + const MEMORY_INFO_DATA_HOB *meminfo_hob; + const uint8_t smbios_memory_info_guid[sizeof(EFI_GUID)] = FSP_SMBIOS_MEMORY_INFO_GUID; + const uint8_t *serial_num; + const char *dram_part_num = NULL; + size_t dram_part_num_len = 0; + + /* Locate the memory info HOB, presence validated by raminit */ + meminfo_hob = fsp_find_extension_hob_by_guid( + smbios_memory_info_guid, + &hob_size); + if (!meminfo_hob || hob_size == 0) { + printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); + return; + } + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (!mem_info) { + printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); + return; + } + memset(mem_info, 0, sizeof(*mem_info)); + + /* Allow mainboard to override DRAM part number. */ + dram_part_num = mainboard_get_dram_part_num(); + if (dram_part_num) + dram_part_num_len = strlen(dram_part_num); + + /* Save available DIMM information */ + index = 0; + dimm_max = ARRAY_SIZE(mem_info->dimm); + for (node = 0; node < MAX_NODE; node++) { + ctrlr_info = &meminfo_hob->Controller[node]; + for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) { + channel_info = &ctrlr_info->ChannelInfo[channel]; + if (channel_info->Status != CHANNEL_PRESENT) + continue; + + for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) { + src_dimm = &channel_info->DimmInfo[dimm]; + dest_dimm = &mem_info->dimm[index]; + if (src_dimm->Status != DIMM_PRESENT) + continue; + + /* If there is no DRAM part number overridden by + * mainboard then use original one. */ + if (!dram_part_num) { + dram_part_num_len = sizeof(src_dimm->ModulePartNum); + dram_part_num = (const char *) + &src_dimm->ModulePartNum[0]; + } + + uint8_t memProfNum = meminfo_hob->MemoryProfile; + serial_num = src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL; + + /* Populate the DIMM information */ + dimm_info_fill(dest_dimm, + src_dimm->DimmCapacity, + meminfo_hob->MemoryType, + meminfo_hob->ConfiguredMemoryClockSpeed, + src_dimm->RankInDimm, + channel_info->ChannelId, + src_dimm->DimmId, + dram_part_num, + dram_part_num_len, + serial_num, + meminfo_hob->DataWidth, + meminfo_hob->VddVoltage[memProfNum], + meminfo_hob->EccSupport, + src_dimm->MfgId, + src_dimm->SpdModuleType, + node, + meminfo_hob->MaximumMemoryClockSpeed); + index++; + } + } + } + mem_info->dimm_cnt = index; + if (mem_info->dimm_cnt == 0) + printk(BIOS_ERR, "No DIMMs found\n"); + else + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); +} + +void mainboard_romstage_entry(void) +{ + struct chipset_power_state *ps = pmc_get_power_state(); + bool s3wake = pmc_fill_power_state(ps) == ACPI_S3; + + /* Initialize HECI interface */ + cse_init(HECI1_BASE_ADDRESS); + + if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU)) { + timestamp_add_now(TS_CSE_FW_SYNC_START); + cse_fw_sync(); + timestamp_add_now(TS_CSE_FW_SYNC_END); + } + + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ + systemagent_early_init(); + /* Program SMBus base address and enable it */ + smbus_common_init(); + + /* + * Set low maximum temp threshold value used for dynamic thermal sensor + * shutdown consideration. + * + * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the + * thermal sensor when CPU is in a C-state and LTT >= DTS Temp. + */ + pch_thermal_configuration(); + fsp_memory_init(s3wake); + pmc_set_disb(); + if (!s3wake) + save_dimm_info(); +} diff --git a/src/soc/intel/lnl_dev/systemagent.c b/src/soc/intel/lnl_dev/systemagent.c new file mode 100644 index 0000000..d926902 --- /dev/null +++ b/src/soc/intel/lnl_dev/systemagent.c @@ -0,0 +1,254 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/ioapic.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <delay.h> +#include <intelblocks/cpulib.h> +#include <intelblocks/msr.h> +#include <intelblocks/power_limit.h> +#include <intelblocks/systemagent.h> +#include <soc/iomap.h> +#include <soc/soc_chip.h> +#include <soc/systemagent.h> + +/* + * SoC implementation + * + * Add all known fixed memory ranges for Host Controller/Memory + * controller. + */ +__attribute__((weak)) void soc_add_fixed_mmio_resources(struct device *dev, int *index) +{ +} + +/* + * set MMIO resource's fields + */ +static void set_mmio_resource( + struct sa_mmio_descriptor *resource, + uint64_t base, + uint64_t size, + const char *description) +{ + if (resource == NULL) { + printk(BIOS_ERR, "%s: argument resource is NULL for %s\n", + __func__, description); + return; + } + resource->base = base; + resource->size = size; + resource->description = description; +} + +int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base, + uint64_t *prmrr_mask) +{ + msr_t msr; + msr = rdmsr(MSR_PRMRR_BASE_0); + *prmrr_base = (uint64_t)msr.hi << 32 | msr.lo; + msr = rdmsr(MSR_PRMRR_PHYS_MASK); + *prmrr_mask = (uint64_t)msr.hi << 32 | msr.lo; + return 0; +} + +/* + * SoC implementation + * + * Add all known configurable memory ranges for Host Controller/Memory + * controller. + */ +void soc_add_configurable_mmio_resources(struct device *dev, int *resource_cnt) +{ + uint64_t size, base, tseg_base; + int count = 0; + struct sa_mmio_descriptor cfg_rsrc[6]; /* Increase size when adding more resources */ + + /* MMCONF */ + size = get_mmcfg_size(dev); + if (size > 0) + set_mmio_resource(&(cfg_rsrc[count++]), CONFIG_ECAM_MMCONF_BASE_ADDRESS, + size, "MMCONF"); + + /* DSM */ + size = get_dsm_size(dev); + if (size > 0) { + base = pci_read_config32(dev, DSM_BASE_ADDR_REG) & 0xFFF00000; + set_mmio_resource(&(cfg_rsrc[count++]), base, size, "DSM"); + } + + /* TSEG */ + size = sa_get_tseg_size(); + tseg_base = sa_get_tseg_base(); + if (size > 0) + set_mmio_resource(&(cfg_rsrc[count++]), tseg_base, size, "TSEG"); + + /* PMRR */ + size = get_valid_prmrr_size(); + if (size > 0) { + uint64_t mask; + if (soc_get_uncore_prmmr_base_and_mask(&base, &mask) == 0) { + base &= mask; + set_mmio_resource(&(cfg_rsrc[count++]), base, size, "PMRR"); + } else { + printk(BIOS_ERR, "SA: Failed to get PRMRR base and mask\n"); + } + } + + /* GSM */ + size = get_gsm_size(dev); + if (size > 0) { + base = sa_get_gsm_base(); + set_mmio_resource(&(cfg_rsrc[count++]), base, size, "GSM"); + } + + /* DPR */ + size = get_dpr_size(dev); + if (size > 0) { + /* DPR just below TSEG: */ + base = tseg_base - size; + set_mmio_resource(&(cfg_rsrc[count++]), base, size, "DPR"); + } + + /* Add all the above */ + sa_add_fixed_mmio_resources(dev, resource_cnt, cfg_rsrc, count); +} + +/* + * SoC implementation + * + * Perform System Agent Initialization during Ramstage phase. + */ +__attribute__((weak)) void soc_systemagent_init(struct device *dev) +{ +} + +uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz) +{ + switch (capid0_a_ddrsz) { + case 1: + return 8192; + case 2: + return 4096; + case 3: + return 2048; + default: + return 65536; + } +} + +uint64_t get_mmcfg_size(const struct device *dev) +{ + uint32_t pciexbar_reg; + uint64_t mmcfg_length; + + if (!dev) { + printk(BIOS_DEBUG, "%s : device is null\n", __func__); + return 0; + } + + pciexbar_reg = pci_read_config32(dev, PCIEXBAR); + + if (!(pciexbar_reg & (1 << 0))) { + printk(BIOS_DEBUG, "%s : PCIEXBAR disabled\n", __func__); + return 0; + } + + switch ((pciexbar_reg & MASK_PCIEXBAR_LENGTH) >> PCIEXBAR_LENGTH_LSB) { + case PCIEXBAR_LENGTH_4096MB: + mmcfg_length = 4 * ((uint64_t)GiB); + break; + case PCIEXBAR_LENGTH_2048MB: + mmcfg_length = 2 * ((uint64_t)GiB); + break; + case PCIEXBAR_LENGTH_1024MB: + mmcfg_length = 1 * GiB; + break; + case PCIEXBAR_LENGTH_512MB: + mmcfg_length = 512 * MiB; + break; + case PCIEXBAR_LENGTH_256MB: + mmcfg_length = 256 * MiB; + break; + case PCIEXBAR_LENGTH_128MB: + mmcfg_length = 128 * MiB; + break; + case PCIEXBAR_LENGTH_64MB: + mmcfg_length = 64 * MiB; + break; + default: + printk(BIOS_DEBUG, "%s : PCIEXBAR - invalid length (0x%x)\n", __func__, + pciexbar_reg & MASK_PCIEXBAR_LENGTH); + mmcfg_length = 0x0; + break; + } + + return mmcfg_length; +} + +uint64_t get_dsm_size(const struct device *dev) +{ + // - size : B0/D0/F0:R 50h [15:8] + uint32_t reg32 = pci_read_config32(dev, GGC); + uint64_t size; + uint32_t size_field = (reg32 & MASK_DSM_LENGTH) >> MASK_DSM_LENGTH_LSB; + if (size_field <= 0x10) { // 0x0 - 0x10 + size = size_field * 32 * MiB; + } else if ((size_field >= 0xF0) && (size_field >= 0xFE)) { + size = ((uint64_t)size_field - 0xEF) * 4 * MiB; + } else { + switch (size_field) { + case 0x20: + size = 1 * GiB; + break; + case 0x30: + size = 1536 * MiB; + break; + case 0x40: + size = 2 * (uint64_t)GiB; + break; + default: + printk(BIOS_DEBUG, "%s : DSM - invalid length (0x%x)\n", + __func__, size_field); + size = 0x0; + break; + } + } + return size; +} + +uint64_t get_gsm_size(const struct device *dev) +{ + const u32 gsm_size = pci_read_config32(dev, GGC); + uint64_t size; + uint32_t size_field = (gsm_size & MASK_GSM_LENGTH) >> MASK_GSM_LENGTH_LSB; + switch (size_field) { + case 0x0: + size = 0; + break; + case 0x1: + size = 2 * MiB; + break; + case 0x2: + size = 4 * MiB; + break; + case 0x3: + size = 8 * MiB; + break; + default: + size = 0; + break; + } + return size; +} +uint64_t get_dpr_size(const struct device *dev) +{ + uint64_t size; + uint32_t dpr_reg = pci_read_config32(dev, DPR_REG); + uint32_t size_field = (dpr_reg & MASK_DPR_LENGTH) >> MASK_DPR_LENGTH_LSB; + size = (uint64_t)size_field * MiB; + return size; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/81872?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id6a01284018c3dcaa80ad1b2e92d6b88ddb83018 Gerrit-Change-Number: 81872 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-MessageType: newchange

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[XL] Change in coreboot[main]: soc/intel/lnl: Do initial Lunar Lake SoC commit till bootblock
by Saurabh Mishra (Code Review) 12 Apr '24

12 Apr '24

Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81851?usp=email ) Change subject: soc/intel/lnl: Do initial Lunar Lake SoC commit till bootblock ...................................................................... soc/intel/lnl: Do initial Lunar Lake SoC commit till bootblock List of changes: 1. Add required Lunar Lake SoC programming till bootblock 2. Include only required headers into include/soc 3. Include LNL-M related DID, BDF 4. Ref: Processor EDS documents vol1 #734362, vol2 #749160 Change-Id: I90d00628b5342efd9e1d325c12bd6e28f1f47952 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- A src/soc/intel/lnl_dev/Kconfig A src/soc/intel/lnl_dev/Makefile.mk A src/soc/intel/lnl_dev/bootblock/bootblock.c A src/soc/intel/lnl_dev/bootblock/pch.c A src/soc/intel/lnl_dev/bootblock/report_platform.c A src/soc/intel/lnl_dev/include/soc/bootblock.h A src/soc/intel/lnl_dev/include/soc/espi.h A src/soc/intel/lnl_dev/include/soc/iomap.h A src/soc/intel/lnl_dev/include/soc/p2sb.h A src/soc/intel/lnl_dev/include/soc/pci_devs.h A src/soc/intel/lnl_dev/include/soc/pcr_ids.h A src/soc/intel/lnl_dev/include/soc/pm.h A src/soc/intel/lnl_dev/include/soc/report_platform.h A src/soc/intel/lnl_dev/include/soc/smbus.h A src/soc/intel/lnl_dev/lunarlake/Makefile.mk A src/soc/intel/lnl_dev/lunarlake/bootstage/report_platform.c A src/soc/intel/lnl_dev/lunarlake/include/platform_soc_defs.h 17 files changed, 1,542 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/81851/1 diff --git a/src/soc/intel/lnl_dev/Kconfig b/src/soc/intel/lnl_dev/Kconfig new file mode 100644 index 0000000..00cedc2 --- /dev/null +++ b/src/soc/intel/lnl_dev/Kconfig @@ -0,0 +1,372 @@ +config SOC_INTEL_LNL_BASE + bool + +config SOC_INTEL_LUNARLAKE + bool + select SOC_INTEL_LNL_BASE + help + Intel Lunarlake support + +if SOC_INTEL_LNL_BASE + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ARCH_X86 + select BOOT_DEVICE_SUPPORTS_WRITES + select CACHE_MRC_SETTINGS + select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_VOLTAGE + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CPU_SUPPORTS_PM_TIMER_EMULATION + select DEFAULT_SOFTWARE_CONNECTION_MANAGER if MAINBOARD_HAS_CHROMEOS + select DEFAULT_X2APIC_LATE_WORKAROUND + select DISPLAY_FSP_VERSION_INFO_2 + select DRIVERS_USB_ACPI + select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 + select FSP_COMPRESS_FSP_S_LZ4 + select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW + select FSP_M_XIP + select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 + select FSP_USES_CB_DEBUG_EVENT_HANDLER + select GENERIC_GPIO_LIB + select HAVE_DEBUG_RAM_SETUP + select HAVE_FSP_GOP + select INTEL_DESCRIPTOR_MODE_CAPABLE + select HAVE_SMI_HANDLER + select IDT_IN_EVERY_STAGE + select LNL_CAR_ENHANCED_NEM + select INTEL_GMA_ACPI + select INTEL_GMA_ADD_VBT if RUN_FSP_GOP + select IOAPIC + select MP_SERVICES_PPI_V2 + select MRC_SETTINGS_PROTECT + select PARALLEL_MP_AP_WORK + select MICROCODE_BLOB_UNDISCLOSED + select PLATFORM_USES_FSP2_4 + select REG_SCRIPT + select PMC_GLOBAL_RESET_ENABLE_LOCK + select PMC_EPOC + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC + select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO + select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT + select SOC_INTEL_COMMON_BLOCK_ACPI_PEP + select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ + select SOC_INTEL_COMMON_BLOCK_CAR + select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG + select SOC_INTEL_COMMON_BLOCK_CNVI + select SOC_INTEL_COMMON_BLOCK_CPU + select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT + select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE + select SOC_INTEL_COMMON_BLOCK_DTT + select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT + select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY + select SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR + select SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS + select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 + select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC + select SOC_INTEL_COMMON_BLOCK_IAA + select SOC_INTEL_COMMON_BLOCK_IPU + select SOC_INTEL_COMMON_BLOCK_IRQ + select SOC_INTEL_COMMON_BLOCK_ME_SPEC_18 + select SOC_INTEL_COMMON_BLOCK_MEMINIT + select SOC_INTEL_COMMON_BLOCK_OSSE + select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT + select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK_SMM + select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_BLOCK_TCSS + select SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_SBI + select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC + select SOC_INTEL_COMMON_BLOCK_USB4 + select SOC_INTEL_COMMON_BLOCK_USB4_PCIE + select SOC_INTEL_COMMON_BLOCK_USB4_XHCI + select SOC_INTEL_COMMON_BLOCK_XHCI + select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG + select SOC_INTEL_COMMON_BASECODE + select SOC_INTEL_COMMON_BASECODE_RAMTOP + select SOC_INTEL_COMMON_FSP_RESET + select SOC_INTEL_COMMON_PCH_CLIENT + select SOC_INTEL_COMMON_RESET + select SOC_INTEL_COMMON_BLOCK_IOC + select SOC_INTEL_CSE_SEND_EOP_LATE if !MAINBOARD_HAS_CHROMEOS + select SOC_INTEL_CSE_SET_EOP + select SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO + select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION + select SSE2 + select SUPPORT_CPU_UCODE_IN_CBFS + select TSC_MONOTONIC_TIMER + select UDELAY_TSC + select UDK_202404_BINDING + select HAVE_X86_64_SUPPORT + select SOC_INTEL_COMMON_BLOCK_PMC_EPOC + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select LUNARLAKE_ENABLE_IBECC + +config LNL_CAR_ENHANCED_NEM + bool + default y if !INTEL_CAR_NEM + select INTEL_CAR_NEM_ENHANCED + select CAR_HAS_SF_MASKS + select COS_MAPPED_TO_MSB + select CAR_HAS_L3_PROTECTED_WAYS + +config MAX_CPUS + int + default 22 + +config DCACHE_RAM_BASE + default 0xfa000000 + +config DCACHE_RAM_SIZE + default 0x200000 + help + The size of the cache-as-ram region required during bootblock + and/or romstage. + +config DCACHE_BSP_STACK_SIZE + hex + default 0x80400 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. In the case of FSP_USES_CB_STACK default value will be + sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement + (~1KiB). + +config FSP_TEMP_RAM_SIZE + hex + default 0x80100 + help + The amount of anticipated heap usage in CAR by FSP. + Refer to Platform FSP integration guide document to know + the exact FSP requirement for Heap setup. + +config CHIPSET_DEVICETREE + string + default "soc/intel/lnl_dev/lunarlake/chipset.cb" + +config EXT_BIOS_WIN_BASE + default 0xf8000000 + +config EXT_BIOS_WIN_SIZE + default 0x2000000 + +config IFD_CHIPSET + string + default "ifd2" + +config IED_REGION_SIZE + hex + default 0x400000 + +config HEAP_SIZE + hex + default 0x10000 + +# Intel recommends reserving the PCIe TBT root port resources as below: +# - 42 buses +# - 194 MiB Non-prefetchable memory +# - 448 MiB Prefetchable memory +if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + +config PCIEXP_HOTPLUG_BUSES + int + default 42 + +config PCIEXP_HOTPLUG_MEM + hex + default 0x6000000 + +config PCIEXP_HOTPLUG_PREFETCH_MEM + hex + default 0x800000000 + +endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + +config MAX_TBT_ROOT_PORTS + int + default 3 + +config MAX_ROOT_PORTS + int + default 12 + +config MAX_PCIE_CLOCK_SRC + int + default 9 + +config SMM_TSEG_SIZE + hex + default 0x2000000 + +config SMM_RESERVED_SIZE + hex + default 0x200000 + +config PCR_BASE_ADDRESS + hex + default 0xe0000000 + help + This option allows you to select MMIO Base Address of sideband bus. + +config ECAM_MMCONF_BASE_ADDRESS + default 0xc0000000 + +config CPU_BCLK_MHZ + int + default 100 + +config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ + int + default 120 + +config CPU_XTAL_HZ + default 38400000 + +config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ + int + default 133 + +config SOC_INTEL_COMMON_BLOCK_GSPI_MAX + int + default 2 + +config SOC_INTEL_I2C_DEV_MAX + int + default 6 + +config SOC_INTEL_I3C_DEV_MAX + int + default 2 + +config SOC_INTEL_UART_DEV_MAX + int + default 3 + +config SOC_INTEL_USB2_DEV_MAX + int + default 10 + +config SOC_INTEL_USB3_DEV_MAX + int + default 2 + +config CONSOLE_UART_BASE_ADDRESS + hex + default 0xfe03e000 + depends on INTEL_LPSS_UART_FOR_CONSOLE + +config VBT_DATA_SIZE_KB + int + default 9 + +# Clock divider parameters for 115200 baud rate +# Baudrate = (UART source clcok * M) /(N *16) +# LNL UART source clock: 120MHz +config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL + hex + default 0x25a + +config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL + hex + default 0x7fff + +config VBOOT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_VBNV_CMOS + select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH + select VBOOT_X86_SHA256_ACCELERATION + +# Default hash block size is 1KiB. Increasing it to 4KiB to improve +# hashing time as well as read time. +config VBOOT_HASH_BLOCK_SIZE + hex + default 0x1000 + +config CBFS_SIZE + hex + default 0x200000 + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0x2000 + +config CONSOLE_CBMEM_BUFFER_SIZE + hex + default 0x40000 + +config FSP_HEADER_PATH + string "Location of FSP headers" + default "src/vendorcode/intel/fsp/fsp2_4/lunarlake/" + +config FSP_FD_PATH + string + depends on FSP_USE_REPO + default "3rdparty/fsp/LunarLakeFspBinPkg/Fsp.fd" + +config SOC_INTEL_DEBUG_CONSENT_2 + int "Debug Consent" + # USB DBC is more common for developers so make this default to 3 if + # SOC_INTEL_DEBUG_CONSENT=y + default 3 if SOC_INTEL_DEBUG_CONSENT + default 0 + help + This is to control debug interface on SOC. + Setting non-zero value will allow to use DBC or DCI to debug SOC. + PlatformDebugConsent in FspmUpd.h has the details. + + Desired platform debug type are + 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), + 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), + 6:Enable (2-wire DCI OOB), 7:Manual + +config DATA_BUS_WIDTH + int + default 128 + +config DIMMS_PER_CHANNEL + int + default 2 + +config MRC_CHANNEL_WIDTH + int + default 16 + +config SOC_INTEL_CRASHLOG + def_bool n + select SOC_INTEL_COMMON_BLOCK_CRASHLOG + select ACPI_BERT + help + Enables CrashLog. + +config SOC_INTEL_GFX_FRAMEBUFFER_OFFSET + hex + default 0x800000 + +config FSP_PUBLISH_MBP_HOB + bool + default n if CHROMEOS + default y + help + This is to control creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. + Disabling it for the platforms, which do not use MBP HOB, can improve the boot time. + +config SOC_INTEL_UFS_CLK_FREQ_HZ + int + default 38400000 + +config LUNARLAKE_ENABLE_IBECC + bool "Enable IBECC" + help + Enables In Band Error Correction Code. It's only needed for endurance testing + and therefore not always required. + default n + +endif diff --git a/src/soc/intel/lnl_dev/Makefile.mk b/src/soc/intel/lnl_dev/Makefile.mk new file mode 100644 index 0000000..e080444 --- /dev/null +++ b/src/soc/intel/lnl_dev/Makefile.mk @@ -0,0 +1,62 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_INTEL_LNL_BASE),y) + +subdirs-$(CONFIG_SOC_INTEL_LUNARLAKE) += lunarlake +subdirs-y += ../../../cpu/intel/microcode +subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../cpu/x86/mtrr +subdirs-y += ../../../cpu/x86/tsc + +# all (bootblock, verstage, romstage, postcar, ramstage) +all-y += gspi.c +all-y += i2c.c +all-y += pmutil.c +all-y += spi.c +all-y += uart.c + +bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock/pch.c +bootblock-y += bootblock/report_platform.c +bootblock-y += espi.c +bootblock-y += p2sb.c +bootblock-y += soc_info.c +bootblock-y += systemagent.c + +romstage-y += espi.c +romstage-y += reset.c +romstage-y += soc_info.c +romstage-y += ../../../cpu/intel/car/romstage.c +romstage-y += romstage.c + +ramstage-y += acpi.c +ramstage-y += chip.c +ramstage-y += cpu.c +ramstage-y += elog.c +ramstage-y += espi.c +ramstage-y += finalize.c +ramstage-y += lockdown.c +ramstage-y += me.c +ramstage-y += p2sb.c +ramstage-y += pmc.c +ramstage-y += reset.c +ramstage-y += retimer.c +ramstage-y += soundwire.c +ramstage-y += systemagent.c +ramstage-y += tcss.c +ramstage-y += xhci.c +ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c +ramstage-y += soc_info.c + +smm-y += elog.c +smm-y += p2sb.c +smm-y += pmutil.c +smm-y += smihandler.c +smm-y += uart.c +smm-y += xhci.c +smm-y += soc_info.c + +CPPFLAGS_common += -I$(src)/soc/intel/lnl_dev +CPPFLAGS_common += -I$(src)/soc/intel/lnl_dev/include + +CFLAGS_common += -Wno-error=int-conversion +endif diff --git a/src/soc/intel/lnl_dev/bootblock/bootblock.c b/src/soc/intel/lnl_dev/bootblock/bootblock.c new file mode 100644 index 0000000..9f113ef --- /dev/null +++ b/src/soc/intel/lnl_dev/bootblock/bootblock.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <soc/bootblock.h> + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + /* Call lib/bootblock.c main */ + bootblock_main_with_basetime(base_timestamp); +} + +void bootblock_soc_early_init(void) +{ + bootblock_soc_die_early_init(); +} + +void bootblock_soc_init(void) +{ + report_platform_info(); + bootblock_pch_init(); +} diff --git a/src/soc/intel/lnl_dev/bootblock/pch.c b/src/soc/intel/lnl_dev/bootblock/pch.c new file mode 100644 index 0000000..9d7c359 --- /dev/null +++ b/src/soc/intel/lnl_dev/bootblock/pch.c @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/mmio.h> +#include <device/device.h> +#include <device/pci_ops.h> +#include <intelblocks/fast_spi.h> +#include <intelblocks/gspi.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/p2sb.h> +#include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> +#include <intelblocks/rtc.h> +#include <intelblocks/systemagent.h> +#include <intelblocks/tco.h> +#include <intelblocks/uart.h> +#include <soc/bootblock.h> +#include <soc/espi.h> +#include <soc/iomap.h> +#include <soc/p2sb.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <soc/pm.h> +#include <soc/romstage.h> +#include <soc/pch.h> + +static void soc_config_pwrmbase(void) +{ + /* + * Assign Resources to PWRMBASE + * Clear BIT 1-2 Command Register + */ + pci_and_config16(PCI_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); + + /* Program PWRM Base */ + pci_write_config32(PCI_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); + + /* Enable Bus Master and MMIO Space */ + pci_or_config16(PCI_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); + + /* Enable PWRM in PMC */ + setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); +} + +void pch_early_iorange_init(void) +{ + uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | + LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; + + /* IO Decode Range */ + if (CONFIG(DRIVERS_UART_8250IO)) + lpc_io_setup_comm_a_b(); + + /* IO Decode Enable */ + lpc_enable_fixed_io_ranges(io_enables); + + /* Program generic IO Decode Range */ + pch_enable_lpc(); +} + +void bootblock_pch_early_init(void) +{ + soc_die_early_sa_init(); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ + p2sb_enable_bar(); + p2sb2_enable_bar(); + p2sb_configure_hpet(); + + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + + /* + * Enabling SoC PMC PWRM Base for accessing + * Global Reset Cause Register. + */ + soc_config_pwrmbase(); +} + +void soc_die_early_sa_init(void) +{ + const struct sa_mmio_descriptor soc_fixed_pci_resources[] = { + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, + }; + + bootblock_systemagent_early_init(); + + /* Enable MCHBAR early, needed by IOC driver */ + sa_set_pci_bar(soc_fixed_pci_resources, ARRAY_SIZE(soc_fixed_pci_resources)); +} + +void bootblock_soc_die_early_init(void) +{ + /* + * Ensure performing SA related programming including MCHBAR prior to accessing + * IOC driver. + */ + soc_die_early_sa_init(); + + bootblock_pch_early_init(); + + fast_spi_cache_bios_region(); + pch_early_iorange_init(); + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) + uart_bootblock_init(); +} + +static void soc_config_acpibase(void) +{ + uint32_t pmc_reg_value; + uint32_t pmc_base_reg = PCR_PSF8_TO_SHDW_PMC_REG_BASE; + + pmc_reg_value = pcr_read32(PID_PSF8, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4); + + if (pmc_reg_value != 0xffffffff) { + /* Disable Io Space before changing the address */ + pcr_rmw32(PID_PSF8, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, + ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0); + /* Program ABASE in PSF8 PMC space BAR4*/ + pcr_write32(PID_PSF8, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4, + ACPI_BASE_ADDRESS); + /* Enable IO Space */ + pcr_rmw32(PID_PSF8, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, + ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN); + } +} + +void bootblock_pch_init(void) +{ + /* + * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, + * GPE0_STS, GPE0_EN registers. + */ + soc_config_acpibase(); + + /* Set up GPE configuration */ + pmc_gpe_init(); + + enable_rtc_upper_bank(); + + /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ + tco_configure(); +} diff --git a/src/soc/intel/lnl_dev/bootblock/report_platform.c b/src/soc/intel/lnl_dev/bootblock/report_platform.c new file mode 100644 index 0000000..0082c28 --- /dev/null +++ b/src/soc/intel/lnl_dev/bootblock/report_platform.c @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/cpu.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/intel/microcode.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/name.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <intelblocks/cpulib.h> +#include <soc/bootblock.h> +#include <soc/pci_devs.h> +#include <soc/report_platform.h> + +static inline uint8_t get_dev_revision(pci_devfn_t dev) +{ + return pci_read_config8(dev, PCI_REVISION_ID); +} + +static inline uint16_t get_dev_id(pci_devfn_t dev) +{ + return pci_read_config16(dev, PCI_DEVICE_ID); +} + +static void report_cache_info(void) +{ + int cache_level = CACHE_L3; + struct cpu_cache_info info; + + if (!fill_cpu_cache_info(cache_level, &info)) + return; + + printk(BIOS_INFO, "Cache: Level %d: ", cache_level); + printk(BIOS_INFO, "Associativity = %zd Partitions = %zd Line Size = %zd Sets = %zd\n", + info.num_ways, info.physical_partitions, info.line_size, info.num_sets); + + printk(BIOS_INFO, "Cache size = %zu MiB\n", get_cache_size(&info)/MiB); +} + +static enum core_type get_soc_cpu_type(void) +{ + if (cpu_is_hybrid_supported()) + return cpu_get_cpu_type(); + else + return CPUID_CORE_TYPE_INTEL_CORE; +} + +static void report_cpu_info(void) +{ + u32 i, cpu_id, cpu_feature_flag; + char cpu_name[49]; + int vt, txt, aes; + static const char *const mode[] = {"NOT ", ""}; + const char *cpu_type = "Unknown"; + + fill_processor_name(cpu_name); + cpu_id = cpu_get_cpuid(); + + /* Look for string to match the name */ + for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { + if (cpu_table[i].cpuid == cpu_id) { + cpu_type = cpu_table[i].name; + break; + } + } + + printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); + printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", + cpu_id, cpu_type, get_current_microcode_rev()); + + printk(BIOS_DEBUG, "CPU Type: %s\n", get_soc_cpu_type() == CPUID_CORE_TYPE_INTEL_CORE ? "core" : "atom"); + + cpu_feature_flag = cpu_get_feature_flags_ecx(); + aes = !!(cpu_feature_flag & CPUID_AES); + txt = !!(cpu_feature_flag & CPUID_SMX); + vt = !!(cpu_feature_flag & CPUID_VMX); + printk(BIOS_DEBUG, + "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", + mode[aes], mode[txt], mode[vt]); + + report_cache_info(); +} + +static void report_mch_info(void) +{ + int i; + pci_devfn_t dev = PCI_DEV_ROOT; + uint16_t mchid = get_dev_id(dev); + const char *mch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(mch_table); i++) { + if (mch_table[i].mchid == mchid) { + mch_type = mch_table[i].name; + break; + } + } + + printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n", + mchid, get_dev_revision(dev), mch_type); +} + +static void report_pch_info(void) +{ + int i; + pci_devfn_t dev = PCI_DEV_ESPI; + uint16_t espiid = get_dev_id(dev); + const char *pch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(pch_table); i++) { + if (pch_table[i].espiid == espiid) { + pch_type = pch_table[i].name; + break; + } + } + printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n", + espiid, get_dev_revision(dev), pch_type); +} + +static void report_igd_info(void) +{ + int i; + pci_devfn_t dev = PCI_DEV_IGD; + uint16_t igdid = get_dev_id(dev); + const char *igd_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(igd_table); i++) { + if (igd_table[i].igdid == igdid) { + igd_type = igd_table[i].name; + break; + } + } + printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n", + igdid, get_dev_revision(dev), igd_type); +} + +void report_platform_info(void) +{ + report_cpu_info(); + report_mch_info(); + report_pch_info(); + report_igd_info(); +} diff --git a/src/soc/intel/lnl_dev/include/soc/bootblock.h b/src/soc/intel/lnl_dev/include/soc/bootblock.h new file mode 100644 index 0000000..89e3e8f --- /dev/null +++ b/src/soc/intel/lnl_dev/include/soc/bootblock.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_LNL_BOOTBLOCK_H_ +#define _SOC_INTEL_LNL_BOOTBLOCK_H_ + +/* Bootblock pre console init programming */ +void bootblock_soc_die_early_init(void); +void bootblock_pch_early_init(void); + +/* Bootblock post console init programming */ +void bootblock_pch_init(void); +void pch_early_iorange_init(void); +void report_platform_info(void); + +#endif //_SOC_INTEL_LNL_BOOTBLOCK_H_ diff --git a/src/soc/intel/lnl_dev/include/soc/espi.h b/src/soc/intel/lnl_dev/include/soc/espi.h new file mode 100644 index 0000000..ea2f822 --- /dev/null +++ b/src/soc/intel/lnl_dev/include/soc/espi.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_LNL_ESPI_H_ +#define _SOC_INTEL_LNL_ESPI_H_ + +/* PCI Configuration Space (D31:F0): ESPI */ +#define SCI_IRQ_SEL (7 << 0) +#define SCIS_IRQ9 0 +#define SCIS_IRQ10 1 +#define SCIS_IRQ11 2 +#define SCIS_IRQ20 4 +#define SCIS_IRQ21 5 +#define SCIS_IRQ22 6 +#define SCIS_IRQ23 7 +#define SERIRQ_CNTL 0x64 +#define ESPI_IO_DEC 0x80 /* IO Decode Ranges Register */ +#define COMA_RANGE 0x0 /* 0x3F8 - 0x3FF COM1*/ +#define COMB_RANGE 0x1 /* 0x2F8 - 0x2FF COM2*/ +#define ESPI_GEN1_DEC 0x84 /* ESPI IF Generic Decode Range 1 */ +#define ESPI_GEN2_DEC 0x88 /* ESPI IF Generic Decode Range 2 */ +#define ESPI_GEN3_DEC 0x8c /* ESPI IF Generic Decode Range 3 */ +#define ESPI_GEN4_DEC 0x90 /* ESPI IF Generic Decode Range 4 */ +#define LGMR 0x98 /* ESPI Generic Memory Range */ +#define PCCTL 0xE0 /* PCI Clock Control */ +#define CLKRUN_EN (1 << 0) + +#endif //_SOC_LUNARLAKE_SOC_INTEL_LNL diff --git a/src/soc/intel/lnl_dev/include/soc/iomap.h b/src/soc/intel/lnl_dev/include/soc/iomap.h new file mode 100644 index 0000000..bd72e2e --- /dev/null +++ b/src/soc/intel/lnl_dev/include/soc/iomap.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_LNL_IOMAP_H_ +#define _SOC_INTEL_LNL_IOMAP_H_ + +#include <soc/pcr_ids.h> +#include <platform_soc_defs.h> + +/* + * Memory-mapped I/O registers. + */ +#define PCH_PRESERVED_BASE_ADDRESS 0xFD800000 +#define PCH_PRESERVED_BASE_SIZE 0x01000000 + +#define MCH_BASE_ADDRESS 0xFEDC0000 +#define MCH_BASE_SIZE 0x20000 + +#define EP_BASE_ADDRESS 0xFEDA1000 +#define EP_BASE_SIZE 0x1000 + +#define EDRAM_BASE_ADDRESS 0xFED80000 +#define EDRAM_BASE_SIZE 0x4000 + +#define HPET_BASE_ADDRESS 0xFED00000 + +//PMC MBAR 64KB +#define PCH_PWRM_BASE_ADDRESS 0xFE000000 +#define PCH_PWRM_BASE_SIZE 0x10000 + +#define GPIO_BASE_SIZE 0x10000 + +#define HECI1_BASE_ADDRESS 0xFEDA2000 + + +#define UART_BASE_SIZE 0x1000 +#define UART_BASE_0_ADDRESS 0xFE03E000 +/* Both UART BAR 0 and 1 are 4KB in size */ +#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \ + UART_BASE_SIZE * (x))) +#define UART_BASE(x) UART_BASE_0_ADDR(x) + +#define EARLY_GSPI_BASE_ADDRESS 0xFE030000 + +#define EARLY_I2C_BASE_ADDRESS 0xFE020000 +#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x))) + +#define SPI_BASE_ADDRESS 0xFE010000 + +#define PCH_SECOND_PCR_ABOVE_4G_BASE_ADDR 0x3FFF0000000 + +/* + * I/O port address space + */ +#define ACPI_BASE_ADDRESS 0x1800 +#define ACPI_BASE_SIZE 0x100 + +#define TCO_BASE_ADDRESS 0x400 +#define TCO_BASE_SIZE 0x20 +#endif //_SOC_INTEL_LNL_IOMAP_H_ diff --git a/src/soc/intel/lnl_dev/include/soc/p2sb.h b/src/soc/intel/lnl_dev/include/soc/p2sb.h new file mode 100644 index 0000000..6a8610f --- /dev/null +++ b/src/soc/intel/lnl_dev/include/soc/p2sb.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_LNL_P2SB_H_ +#define _SOC_INTEL_LNL_P2SB_H_ + +#define HPTC_OFFSET 0x60 +#define HPTC_ADDR_ENABLE_BIT (1 << 7) + +#define PCH_P2SB_EPMASK0 0x220 + +extern struct device_operations soc_p2sb_ops; + +#endif //_SOC_INTEL_LNL_P2SB_H_ diff --git a/src/soc/intel/lnl_dev/include/soc/pci_devs.h b/src/soc/intel/lnl_dev/include/soc/pci_devs.h new file mode 100644 index 0000000..80ee26a --- /dev/null +++ b/src/soc/intel/lnl_dev/include/soc/pci_devs.h @@ -0,0 +1,269 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_LNL_PCI_DEVS_H_ +#define _SOC_INTEL_LNL_PCI_DEVS_H_ + +#include <device/pci_def.h> + +#define _PCI_DEVFN(slot, func) PCI_DEVFN(PCI_DEV_SLOT_ ## slot, func) +#if !defined(__SIMPLE_DEVICE__) +#include <device/device.h> +#define _PCI_DEV(slot, func) pcidev_path_on_root_debug(_PCI_DEVFN(slot, func), __func__) +#else +#define _PCI_DEV(slot, func) PCI_DEV(0, PCI_DEV_SLOT_ ## slot, func) +#endif + +/* System Agent Devices */ +#define PCI_DEV_SLOT_ROOT 0x00 +#define PCI_DEVFN_ROOT _PCI_DEVFN(ROOT, 0) +#if defined(__SIMPLE_DEVICE__) +#define PCI_DEV_ROOT _PCI_DEV(ROOT, 0) +#endif + +#define PCI_DEV_SLOT_IGD 0x02 +#define PCI_DEVFN_IGD _PCI_DEVFN(IGD, 0) +#define PCI_DEV_IGD _PCI_DEV(IGD, 0) + +#define PCI_DEV_SLOT_DPTF 0x04 +#define PCI_DEVFN_DPTF _PCI_DEVFN(DPTF, 0) +#define PCI_DEV_DPTF _PCI_DEV(DPTF, 0) + +#define PCI_DEV_SLOT_IPU 0x05 +#define PCI_DEVFN_IPU _PCI_DEVFN(IPU, 0) +#define PCI_DEV_IPU _PCI_DEV(IPU, 0) + +#define PCI_DEV_SLOT_TBT 0x07 +#define PCI_DEVFN_TBT(x) _PCI_DEVFN(TBT, (x)) +#if CONFIG(SOC_INTEL_LUNARLAKE) +#define NUM_TBT_FUNCTIONS 3 +#endif +#if CONFIG(SOC_INTEL_PANTHERLAKE) +#define NUM_TBT_FUNCTIONS 4 +#define PCI_DEVFN_TBT3 _PCI_DEVFN(TBT, 3) +#define PCI_DEV_TBT3 _PCI_DEV(TBT, 3) +#endif +#define PCI_DEVFN_TBT0 _PCI_DEVFN(TBT, 0) +#define PCI_DEVFN_TBT1 _PCI_DEVFN(TBT, 1) +#define PCI_DEVFN_TBT2 _PCI_DEVFN(TBT, 2) +#define PCI_DEV_TBT0 _PCI_DEV(TBT, 0) +#define PCI_DEV_TBT1 _PCI_DEV(TBT, 1) +#define PCI_DEV_TBT2 _PCI_DEV(TBT, 2) + +#define PCI_DEV_SLOT_NPU 0xb +#define PCI_DEVFN_NPU _PCI_DEVFN(NPU, 0) +#define PCI_DEV_NPU _PCI_DEV(NPU, 0) + +#if CONFIG(SOC_INTEL_PANTHERLAKE) +#define PCI_DEV_SLOT_IAA 0xc +#define PCI_DEVFN_IAA _PCI_DEVFN(IAA, 0) +#define PCI_DEV_IAA _PCI_DEV(IAA, 0) +#endif + +#define PCI_DEV_SLOT_TCSS 0x0d +#define NUM_TCSS_DMA_FUNCTIONS 2 +#define PCI_DEVFN_TCSS_DMA(x) _PCI_DEVFN(TCSS, ((x) + 2)) +#define PCI_DEVFN_TCSS_XHCI _PCI_DEVFN(TCSS, 0) +#if CONFIG(SOC_INTEL_PANTHERLAKE) +#define PCI_DEVFN_TCSS_XDCI _PCI_DEVFN(TCSS, 1) +#define PCI_DEV_TCSS_XDCI _PCI_DEV(TCSS, 1) +#endif +#define PCI_DEVFN_TCSS_DMA0 _PCI_DEVFN(TCSS, 2) +#define PCI_DEVFN_TCSS_DMA1 _PCI_DEVFN(TCSS, 3) +#define PCI_DEV_TCSS_XHCI _PCI_DEV(TCSS, 0) +#define PCI_DEV_TCSS_DMA0 _PCI_DEV(TCSS, 2) +#define PCI_DEV_TCSS_DMA1 _PCI_DEV(TCSS, 3) + +#define PCI_DEV_SLOT_VMD 0x0e +#define PCI_DEVFN_VMD _PCI_DEVFN(VMD, 0) +#define PCI_DEV_VMD _PCI_DEV(VMD, 0) + +#define PCI_DEV_SLOT_THC 0x10 +#define PCI_DEVFN_THC0 _PCI_DEVFN(THC, 0) +#define PCI_DEVFN_THC1 _PCI_DEVFN(THC, 1) +#define PCI_DEV_THC0 _PCI_DEV(THC, 0) +#define PCI_DEV_THC1 _PCI_DEV(THC, 1) + +#define PCI_DEV_SLOT_I3C 0x11 +#define PCI_DEVFN_I3C1 _PCI_DEVFN(I3C, 0) +#define PCI_DEVFN_I3C2 _PCI_DEVFN(I3C, 2) +#define PCI_DEV_I3C1 _PCI_DEV(I3C, 0) +#define PCI_DEV_I3C2 _PCI_DEV(I3C, 2) + +#define PCI_DEV_SLOT_ISH 0x12 +#define PCI_DEVFN_ISH _PCI_DEVFN(ISH, 0) +#define PCI_DEVFN_P2SB2 _PCI_DEVFN(ISH, 1) +#if CONFIG(SOC_INTEL_LUNARLAKE) +#define PCI_DEVFN_GSPI2 _PCI_DEVFN(ISH, 6) +#define PCI_DEVFN_UFS _PCI_DEVFN(ISH, 7) +#define PCI_DEV_GSPI2 _PCI_DEV(ISH, 6) +#define PCI_DEV_UFS _PCI_DEV(ISH, 7) +#endif +#define PCI_DEV_ISH _PCI_DEV(ISH, 0) +#define PCI_DEV_P2SB2 _PCI_DEV(ISH, 1) + +#define PCI_DEV_SLOT_OSSE 0x13 +#define PCI_DEVFN_OSSE1 _PCI_DEVFN(OSSE, 0) +#define PCI_DEVFN_OSSE2 _PCI_DEVFN(OSSE, 1) +#define PCI_DEVFN_OSSE3 _PCI_DEVFN(OSSE, 2) +#define PCI_DEV_OSSE1 _PCI_DEV(OSSE, 0) +#define PCI_DEV_OSSE2 _PCI_DEV(OSSE, 1) +#define PCI_DEV_OSSE3 _PCI_DEV(OSSE, 2) + +#define PCI_DEV_SLOT_XHCI 0x14 +#define PCI_DEVFN_XHCI _PCI_DEVFN(XHCI, 0) +#define PCI_DEVFN_USBOTG _PCI_DEVFN(XHCI, 1) +#define PCI_DEVFN_SRAM _PCI_DEVFN(XHCI, 2) +#define PCI_DEVFN_CNVI_WIFI _PCI_DEVFN(XHCI, 3) +#if CONFIG(SOC_INTEL_PANTHERLAKE) +#define PCI_DEVFN_IEH _PCI_DEVFN(XHCI, 5) +#define PCI_DEVFN_CNVI_BT _PCI_DEVFN(XHCI, 7) +#define PCI_DEV_IEH _PCI_DEV(XHCI, 5) +#define PCI_DEV_CNVI_BT _PCI_DEV(XHCI, 7) +#endif +#define PCI_DEV_XHCI _PCI_DEV(XHCI, 0) +#define PCI_DEV_USBOTG _PCI_DEV(XHCI, 1) +#define PCI_DEV_SRAM _PCI_DEV(XHCI, 2) +#define PCI_DEV_CNVI_WIFI _PCI_DEV(XHCI, 3) + +#define PCI_DEV_SLOT_SIO0 0x15 +#define PCI_DEVFN_I2C0 _PCI_DEVFN(SIO0, 0) +#define PCI_DEVFN_I2C1 _PCI_DEVFN(SIO0, 1) +#define PCI_DEVFN_I2C2 _PCI_DEVFN(SIO0, 2) +#define PCI_DEVFN_I2C3 _PCI_DEVFN(SIO0, 3) +#define PCI_DEV_I2C0 _PCI_DEV(SIO0, 0) +#define PCI_DEV_I2C1 _PCI_DEV(SIO0, 1) +#define PCI_DEV_I2C2 _PCI_DEV(SIO0, 2) +#define PCI_DEV_I2C3 _PCI_DEV(SIO0, 3) + +#define PCI_DEV_SLOT_CSE 0x16 +#define PCI_DEVFN_CSE _PCI_DEVFN(CSE, 0) +#define PCI_DEVFN_CSE_2 _PCI_DEVFN(CSE, 1) +#define PCI_DEVFN_CSE_IDER _PCI_DEVFN(CSE, 2) +#define PCI_DEVFN_CSE_KT _PCI_DEVFN(CSE, 3) +#define PCI_DEVFN_CSE_3 _PCI_DEVFN(CSE, 4) +#define PCI_DEVFN_CSE_4 _PCI_DEVFN(CSE, 5) +#define PCI_DEV_CSE _PCI_DEV(CSE, 0) +#define PCI_DEV_CSE_2 _PCI_DEV(CSE, 1) +#define PCI_DEV_CSE_IDER _PCI_DEV(CSE, 2) +#define PCI_DEV_CSE_KT _PCI_DEV(CSE, 3) +#define PCI_DEV_CSE_3 _PCI_DEV(CSE, 4) +#define PCI_DEV_CSE_4 _PCI_DEV(CSE, 5) +#if CONFIG(SOC_INTEL_PANTHERLAKE) +#define PCI_DEV_CSE_WLAN _PCI_DEV(CSE, 7) +#endif + +#if CONFIG(SOC_INTEL_PANTHERLAKE) +#define PCI_DEV_SLOT_UFS 0x17 +#define PCI_DEVFN_UFS _PCI_DEVFN(UFS, 0) +#define PCI_DEV_UFS _PCI_DEV(UFS, 0) +#endif +#define PCI_DEV_SLOT_ESE 0x18 +#define PCI_DEVFN_ESE1 _PCI_DEVFN(ESE, 0) +#define PCI_DEVFN_ESE2 _PCI_DEVFN(ESE, 1) +#define PCI_DEVFN_ESE3 _PCI_DEVFN(ESE, 2) +#define PCI_DEV_ESE1 _PCI_DEV(ESE, 0) +#define PCI_DEV_ESE2 _PCI_DEV(ESE, 1) +#define PCI_DEV_ESE3 _PCI_DEV(ESE, 2) + +#define PCI_DEV_SLOT_SIO1 0x19 +#define PCI_DEVFN_I2C4 _PCI_DEVFN(SIO1, 0) +#define PCI_DEVFN_I2C5 _PCI_DEVFN(SIO1, 1) +#define PCI_DEVFN_UART2 _PCI_DEVFN(SIO1, 2) +#define PCI_DEV_I2C4 _PCI_DEV(SIO1, 0) +#define PCI_DEV_I2C5 _PCI_DEV(SIO1, 1) +#define PCI_DEV_UART2 _PCI_DEV(SIO1, 2) + +#define PCI_DEV_SLOT_PCIE_1 0x1c +#define PCI_DEVFN_PCIE1 _PCI_DEVFN(PCIE_1, 0) +#define PCI_DEVFN_PCIE2 _PCI_DEVFN(PCIE_1, 1) +#define PCI_DEVFN_PCIE3 _PCI_DEVFN(PCIE_1, 2) +#define PCI_DEVFN_PCIE4 _PCI_DEVFN(PCIE_1, 3) +#define PCI_DEVFN_PCIE5 _PCI_DEVFN(PCIE_1, 4) +#define PCI_DEVFN_PCIE6 _PCI_DEVFN(PCIE_1, 5) +#define PCI_DEV_PCIE1 _PCI_DEV(PCIE_1, 0) +#define PCI_DEV_PCIE2 _PCI_DEV(PCIE_1, 1) +#define PCI_DEV_PCIE3 _PCI_DEV(PCIE_1, 2) +#define PCI_DEV_PCIE4 _PCI_DEV(PCIE_1, 3) +#define PCI_DEV_PCIE5 _PCI_DEV(PCIE_1, 4) +#define PCI_DEV_PCIE6 _PCI_DEV(PCIE_1, 5) + +#if CONFIG(SOC_INTEL_PANTHERLAKE) +#define PCI_DEV_SLOT_PCIE_2 0x6 +#define PCI_DEVFN_PCIE9 _PCI_DEVFN(PCIE_2, 0) +#define PCI_DEVFN_PCIE10 _PCI_DEVFN(PCIE_2, 1) +#define PCI_DEVFN_PCIE11 _PCI_DEVFN(PCIE_2, 2) +#define PCI_DEV_PCIE9 _PCI_DEV(PCIE_2, 0) +#define PCI_DEV_PCIE10 _PCI_DEV(PCIE_2, 1) +#define PCI_DEV_PCIE11 _PCI_DEV(PCIE_2, 2) + +#define PCI_DEV_SLOT_PCIE_3 0x1 +#define PCI_DEVFN_PCIE12 _PCI_DEVFN(PCIE_3, 0) +#define PCI_DEV_PCIE12 _PCI_DEV(PCIE_3, 0) +#endif + +#define PCI_DEV_SLOT_SIO2 0x1e +#define PCI_DEVFN_UART0 _PCI_DEVFN(SIO2, 0) +#define PCI_DEVFN_UART1 _PCI_DEVFN(SIO2, 1) +#define PCI_DEVFN_GSPI0 _PCI_DEVFN(SIO2, 2) +#define PCI_DEVFN_GSPI1 _PCI_DEVFN(SIO2, 3) +#define PCI_DEVFN_TSN1 _PCI_DEVFN(SIO2, 4) +#define PCI_DEVFN_TSN2 _PCI_DEVFN(SIO2, 5) +#define PCI_DEV_UART0 _PCI_DEV(SIO2, 0) +#define PCI_DEV_UART1 _PCI_DEV(SIO2, 1) +#define PCI_DEV_GSPI0 _PCI_DEV(SIO2, 2) +#define PCI_DEV_GSPI1 _PCI_DEV(SIO2, 3) +#define PCI_DEV_TSN1 _PCI_DEV(SIO2, 4) +#define PCI_DEV_TSN2 _PCI_DEV(SIO2, 5) + +#define PCI_DEV_SLOT_ESPI 0x1f +#define PCI_DEVFN_ESPI _PCI_DEVFN(ESPI, 0) +#define PCI_DEVFN_P2SB _PCI_DEVFN(ESPI, 1) +#define PCI_DEVFN_PMC _PCI_DEVFN(ESPI, 2) +#define PCI_DEVFN_HDA _PCI_DEVFN(ESPI, 3) +#define PCI_DEVFN_SMBUS _PCI_DEVFN(ESPI, 4) +#define PCI_DEVFN_SPI _PCI_DEVFN(ESPI, 5) +#define PCI_DEVFN_GBE _PCI_DEVFN(ESPI, 6) +#define PCI_DEVFN_NPK _PCI_DEVFN(ESPI, 7) +#define PCI_DEV_ESPI _PCI_DEV(ESPI, 0) +#define PCI_DEV_P2SB _PCI_DEV(ESPI, 1) + +#if !ENV_RAMSTAGE +/* + * PCI_DEV_PMC is intentionally not defined in RAMSTAGE since PMC device gets + * hidden from PCI bus after call to FSP-S. This leads to resource allocator + * dropping it from the root bus as unused device. All references to PCI_DEV_PMC + * would then return NULL and can go unnoticed if not handled properly. Since, + * this device does not have any special chip config associated with it, it is + * okay to not provide the definition for it in ramstage. + */ +#define PCI_DEV_PMC _PCI_DEV(ESPI, 2) +#endif + +#define PCI_DEV_HDA _PCI_DEV(ESPI, 3) +#define PCI_DEV_SMBUS _PCI_DEV(ESPI, 4) +#define PCI_DEV_SPI _PCI_DEV(ESPI, 5) +#define PCI_DEV_GBE _PCI_DEV(ESPI, 6) +#define PCI_DEV_NPK _PCI_DEV(ESPI, 7) + +#endif + +/* for common code */ +#define MIN_PCH_SLOT PCI_DEV_SLOT_THC +#define PCH_DEV_SLOT_CSE PCI_DEV_SLOT_CSE +#define PCH_DEVFN_CSE PCI_DEVFN_CSE +#define PCH_DEV_CSE PCI_DEV_CSE +#define PCH_DEV_SPI PCI_DEV_SPI +#define PCH_DEV_LPC PCI_DEV_ESPI +#define PCH_DEV_P2SB PCI_DEV_P2SB +#define PCH_DEV_P2SB2 PCI_DEV_P2SB2 +#define PCH_DEV_SMBUS PCI_DEV_SMBUS +#define PCH_DEV_XHCI PCI_DEV_XHCI +#define PCH_DEVFN_XHCI PCI_DEVFN_XHCI +#define PCH_DEVFN_PMC PCI_DEVFN_PMC +#define PCH_DEV_SLOT_ISH PCI_DEV_SLOT_ISH +#define SA_DEV_ROOT PCI_DEV_ROOT +#define SA_DEVFN_ROOT PCI_DEVFN_ROOT +#define SA_DEVFN_TCSS_DMA0 PCI_DEVFN_TCSS_DMA0 +#define SA_DEVFN_TCSS_DMA1 PCI_DEVFN_TCSS_DMA1 +#define SA_DEV_IGD PCI_DEV_IGD +#define SA_DEVFN_IGD PCI_DEVFN_IGD diff --git a/src/soc/intel/lnl_dev/include/soc/pcr_ids.h b/src/soc/intel/lnl_dev/include/soc/pcr_ids.h new file mode 100644 index 0000000..7c87877 --- /dev/null +++ b/src/soc/intel/lnl_dev/include/soc/pcr_ids.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_LNL_PCR_H +#define _SOC_INTEL_LNL_PCR_H +/* + * Port ids + */ +#include <platform_soc_defs.h> + +#endif //_SOC_INTEL_LNL_PCR_H diff --git a/src/soc/intel/lnl_dev/include/soc/pm.h b/src/soc/intel/lnl_dev/include/soc/pm.h new file mode 100644 index 0000000..baf4956 --- /dev/null +++ b/src/soc/intel/lnl_dev/include/soc/pm.h @@ -0,0 +1,162 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_LNL_PM_H_ +#define _SOC_INTEL_LNL_PM_H_ + +#define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) +#define PM1_EN 0x02 +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) +#define PM1_CNT 0x04 +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) +#define PM1_TMR 0x08 +#define SMI_EN 0x30 +#define XHCI_SMI_EN (1 << 31) +#define ME_SMI_EN (1 << 30) +#define ESPI_SMI_EN (1 << 28) +#define GPIO_UNLOCK_SMI_EN (1 << 27) +#define INTEL_USB2_EN (1 << 18) +#define LEGACY_USB2_EN (1 << 17) +#define PERIODIC_EN (1 << 14) +#define TCO_SMI_EN (1 << 13) +#define MCSMI_EN (1 << 11) +#define BIOS_RLS (1 << 7) +#define SWSMI_TMR_EN (1 << 6) +#define APMC_EN (1 << 5) +#define SLP_SMI_EN (1 << 4) +#define LEGACY_USB_EN (1 << 3) +#define BIOS_EN (1 << 2) +#define EOS (1 << 1) +#define GBL_SMI_EN (1 << 0) +#define SMI_STS 0x34 +#define SMI_STS_BITS 32 +#define XHCI_SMI_STS_BIT 31 +#define ME_SMI_STS_BIT 30 +#define ESPI_SMI_STS_BIT 28 +#define GPIO_UNLOCK_SMI_STS_BIT 27 +#define SPI_SMI_STS_BIT 26 +#define SCC_SMI_STS_BIT 25 +#define MONITOR_STS_BIT 21 +#define PCI_EXP_SMI_STS_BIT 20 +#define SMBUS_SMI_STS_BIT 16 +#define SERIRQ_SMI_STS_BIT 15 +#define PERIODIC_STS_BIT 14 +#define TCO_STS_BIT 13 +#define DEVMON_STS_BIT 12 +#define MCSMI_STS_BIT 11 +#define GPIO_STS_BIT 10 +#define GPE0_STS_BIT 9 +#define PM1_STS_BIT 8 +#define SWSMI_TMR_STS_BIT 6 +#define APM_STS_BIT 5 +#define SMI_ON_SLP_EN_STS_BIT 4 +#define LEGACY_USB_STS_BIT 3 +#define BIOS_STS_BIT 2 +#define GPE_CNTL 0x42 +#define SWGPE_CTRL (1 << 1) +#define DEVACT_STS 0x44 +#define PM2_CNT 0x50 + +#define GPE0_REG_MAX 4 +#define GPE0_REG_SIZE 32 +#define GPE0_STS(x) (0x60 + ((x) * 4)) +#define GPE_31_0 0 /* 0x60/0x70 = GPE[31:0] */ +#define GPE_63_32 1 /* 0x64/0x74 = GPE[63:32] */ +#define GPE_95_64 2 /* 0x68/0x78 = GPE[95:64] */ +#define GPE_STD 3 /* 0x6c/0x7c = Standard GPE */ +#define GPE_STS_RSVD GPE_STD +#define WADT_STS (1 << 18) +#define GPIO_T2_STS (1 << 15) +#define ESPI_STS (1 << 14) +#define PME_B0_STS (1 << 13) +#define ME_SCI_STS (1 << 12) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) +#define GPE0_EN(x) (0x70 + ((x) * 4)) +#define WADT_EN (1 << 18) +#define GPIO_T2_EN (1 << 15) +#define ESPI_EN (1 << 14) +#define PME_B0_EN_BIT 13 +#define PME_B0_EN (1 << PME_B0_EN_BIT) +#define ME_SCI_EN (1 << 12) +#define PME_EN (1 << 11) +#define BATLOW_EN (1 << 10) +#define PCI_EXP_EN (1 << 9) +#define TCOSCI_EN (1 << 6) +#define SWGPE_EN (1 << 2) +#define HOT_PLUG_EN (1 << 1) + +#define EN_BLOCK 3 + +/* + * Enable SMI generation: + * - on APMC writes (io 0xb2) + * - on writes to SLP_EN (sleep states) + * - on writes to GBL_RLS (bios commands) + * - on eSPI events (does nothing on LPC systems) + * No SMIs: + * - on TCO events, unless enabled in common code + * - on microcontroller writes (io 0x62/0x66) + */ +#define ENABLE_SMI_PARAMS \ + (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS) + +#define PSS_RATIO_STEP 2 +#define PSS_MAX_ENTRIES 8 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + +#if !defined(__ACPI__) + +#include <acpi/acpi.h> +#include <soc/gpe.h> +#include <soc/iomap.h> +#include <soc/smbus.h> +#include <soc/pmc.h> + +struct chipset_power_state { + uint16_t pm1_sts; + uint16_t pm1_en; + uint32_t pm1_cnt; + uint16_t tco1_sts; + uint16_t tco2_sts; + uint32_t gpe0_sts[4]; + uint32_t gpe0_en[4]; + uint32_t gen_pmcon_a; + uint32_t gen_pmcon_b; + uint32_t gblrst_cause[2]; + uint32_t hpr_cause0; + uint32_t prev_sleep_state; +} __packed; + +/* Get base address PMC memory mapped registers. */ +uint8_t *pmc_mmio_regs(void); + +/* Get base address of TCO I/O registers. */ +uint16_t smbus_tco_regs(void); + +/* Set the DISB after DRAM init */ +void pmc_set_disb(void); + +/* STM Support */ +uint16_t get_pmbase(void); +#endif /* !defined(__ACPI__) */ +#endif //_SOC_INTEL_LNL_PM_H_ diff --git a/src/soc/intel/lnl_dev/include/soc/report_platform.h b/src/soc/intel/lnl_dev/include/soc/report_platform.h new file mode 100644 index 0000000..6038355 --- /dev/null +++ b/src/soc/intel/lnl_dev/include/soc/report_platform.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_LNL_PLATFORM_H_ +#define _SOC_INTEL_LNL_PLATFORM_H_ + +#include <console/console.h> +#include <platform_soc_defs.h> + +enum core_type { + CPUID_RESERVED_1 = 0x10, + CPUID_CORE_TYPE_INTEL_ATOM = 0x20, + CPUID_RESERVED_2 = 0x30, + CPUID_CORE_TYPE_INTEL_CORE = 0x40, + CPUID_UNKNOWN = 0xff, +}; + +__attribute__((weak)) struct { + u32 cpuid; + const char *name; +} cpu_table[SOC_PLATFORM_CPUID_MAX] = { +}; + +__attribute__((weak)) struct { + u16 mchid; + const char *name; +} mch_table[SOC_PLATFORM_MCH_MAX] = { +}; + +__attribute__((weak)) struct { + u16 espiid; + const char *name; +} pch_table[SOC_PLATFORM_PCH_MAX] = { +}; + +__attribute__((weak)) struct { + u16 igdid; + const char *name; +} igd_table[SOC_PLATFORM_IGD_MAX] = { +}; + +#endif /* _SOC_INTEL_LNL_PLATFROM_H_ */ diff --git a/src/soc/intel/lnl_dev/include/soc/smbus.h b/src/soc/intel/lnl_dev/include/soc/smbus.h new file mode 100644 index 0000000..195e7c9 --- /dev/null +++ b/src/soc/intel/lnl_dev/include/soc/smbus.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_LNL_SMBUS_H_ +#define _SOC_INTEL_LNL_SMBUS_H_ + +#include <intelpch/smbus.h> + +#endif //_SOC_SMBUS_H_ diff --git a/src/soc/intel/lnl_dev/lunarlake/Makefile.mk b/src/soc/intel/lnl_dev/lunarlake/Makefile.mk new file mode 100644 index 0000000..000c566 --- /dev/null +++ b/src/soc/intel/lnl_dev/lunarlake/Makefile.mk @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_INTEL_LUNARLAKE),y) + +# all (bootblock, verstage, romstage, postcar, ramstage) +all-y += gpio.c + +bootblock-y += bootstage/report_platform.c +bootblock-y += elog.c +bootblock-y += gpio.c +bootblock-y += systemagent.c + +romstage-y += elog.c +romstage-y += gpio.c +romstage-y += meminit.c +romstage-y += pcie_rp.c + +romstage-y += romstage/fsp_params.c +romstage-y += romstage/systemagent.c + +ramstage-y += acpi.c +ramstage-y += chip.c +ramstage-y += cpu.c +ramstage-y += elog.c +ramstage-y += fsp_params.c +ramstage-y += gpio.c +ramstage-y += pcie_rp.c +ramstage-y += systemagent.c + +smm-y += elog.c +smm-y += gpio.c + +CPPFLAGS_common += -I$(src)/soc/intel/lnl_dev/lunarlake/include +endif diff --git a/src/soc/intel/lnl_dev/lunarlake/bootstage/report_platform.c b/src/soc/intel/lnl_dev/lunarlake/bootstage/report_platform.c new file mode 100644 index 0000000..4f5554b --- /dev/null +++ b/src/soc/intel/lnl_dev/lunarlake/bootstage/report_platform.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <cpu/intel/cpu_ids.h> +#include <device/pci_ids.h> + +struct { + u32 cpuid; + const char *name; +} cpu_table[] = { + { CPUID_LUNARLAKE_A0_1, "Lunarlake A0" }, + { CPUID_LUNARLAKE_A0_2, "Lunarlake A0" }, +}; + +struct { + u16 mchid; + const char *name; +} mch_table[] = { + { PCI_DID_INTEL_LNL_M_ID, "LunarLake M" }, +}; + +struct { + u16 espiid; + const char *name; +} pch_table[] = { + { PCI_DID_INTEL_LNL_ESPI_0, "Lunarlake SOC" }, + { PCI_DID_INTEL_LNL_ESPI_1, "Lunarlake SOC-P SuperSKU" }, + { PCI_DID_INTEL_LNL_ESPI_2, "Lunarlake SOC-P Premium" }, + { PCI_DID_INTEL_LNL_ESPI_3, "Lunarlake SOC-P Base" }, + { PCI_DID_INTEL_LNL_ESPI_4, "Lunarlake SOC" }, + { PCI_DID_INTEL_LNL_ESPI_5, "Lunarlake SOC" }, + { PCI_DID_INTEL_LNL_ESPI_6, "Lunarlake SOC-M SuperSKU" }, + { PCI_DID_INTEL_LNL_ESPI_7, "Lunarlake SOC-M Premium" }, +}; + +struct { + u16 igdid; + const char *name; +} igd_table[] = { + { PCI_DID_INTEL_LNL_M_GT2, "Lunarlake-M GT2" }, +}; diff --git a/src/soc/intel/lnl_dev/lunarlake/include/platform_soc_defs.h b/src/soc/intel/lnl_dev/lunarlake/include/platform_soc_defs.h new file mode 100644 index 0000000..fcbc5a3 --- /dev/null +++ b/src/soc/intel/lnl_dev/lunarlake/include/platform_soc_defs.h @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_LUNARLAKE_PLATFORM_SOC_DEFS_H_ +#define _SOC_LUNARLAKE_PLATFORM_SOC_DEFS_H_ + +/* + * SoC SSDT Info. + */ +#define PMC_FILL_SSDT "Intel(R) Lunar Lake IPC Controller" + +/* + * PCH INFO. + */ +#define PCR_PSF8_TO_SHDW_PMC_REG_BASE 0xB00 + +/* + * SoC Report Info. + */ +#define MAX_USB2_PORT 6 +#define MAX_TCSS_PORT 3 +#define MAX_TBT_PCIE_PORT 3 +#define MAX_PCIE_PORT 6 +#define MAX_PCIE_CLOCK 6 + +/* + * Platform Report Info. + */ +#define SOC_PLATFORM_CPUID_MAX 2 +#define SOC_PLATFORM_MCH_MAX 1 +#define SOC_PLATFORM_PCH_MAX 8 +#define SOC_PLATFORM_IGD_MAX 1 + +/* + * GPIO INFO. + */ +#define CROS_GPIO_NAME "INTC105D" +#define CROS_GPIO_DEVICE_NAME "INTC105D:00" + +/* + * Memory-mapped I/O registers. + */ +//SAF BAR 32MB + Unsused 96MB +#define SAF_BASE_ADDRESS 0xD8000000 +#define SAF_BASE_SIZE 0x8000000 + +//DMI3Bar 8KB +#define DMI_BASE_ADDRESS 0xFED90000 +#define DMI_BASE_SIZE 0x2000 + +//OneSiliconPkg/Fru/LnlCDie/Vtd/Library/PeiDxeSmmVtdInfoFruLib/VtdInfoFruLib.c +//VTD BAR 512KB +#define VTD_BASE_ADDRESS 0xFC800000 +#define VTD_BASE_SIZE 0x00080000 + +// GFX VT-d 64KB +#define GFXVT_BASE_ADDRESS VTD_BASE_ADDRESS +#define GFXVT_BASE_SIZE 0x00010000 + +// Non-GFX VT-d 64KB +#define NONGFXVT_BASE_ADDRESS 0xFC810000 +#define NONGFXVT_BASE_SIZE 0x00010000 + +//IOC VT-d 64KB +#define IOCVTD_BASE_ADDRESS 0xFC820000 +#define IOCVTD_BASE_SIZE 0x00010000 + +#define REGBAR 0x5400 + +//REGBAR 128MB +#define REG_BASE_ADDRESS 0xD0000000 +#define REG_BASE_SIZE (128 * MiB) //REGBAR 128MB + +#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS +#define P2SB_SIZE (256 * MiB) ///< 256MB + +//PCH P2SB2 256MB +#define P2SB2_BAR 0xDF000000 +#define P2SB2_SIZE (256 * MiB) ///< 256MB, used by SBREG_BAR 20-bit address platforms + +#define PID_IOM 0x80 +#define IOM_BASE_ADDR 0xE0000000 + (PID_IOM << 16) +#define IOM_BASE_SIZE 0x1600 +#define IOM_BASE_ADDR_MAX 0xE08015FF + +/* + * Port ids + */ +#define PID_GPIOCOM0 0x70 +#define PID_GPIOCOM1 0x71 +#define PID_GPIOCOM2 0x72 +#define PID_GPIOCOM3 0x73 +#define PID_GPIOCOM4 0x74 +#define PID_GPIOCOM5 0x75 + +#define PID_PSF8 0xB8 +#define PID_PSF7 0xB7 +#define PID_PSF6 0xB6 +#define PID_PSF5 0xB5 +#define PID_PSF4 0xB4 +#define PID_PSF3 0xB3 +#define PID_PSF2 0xB2 +#define PID_PSF1 0xB1 +#define PID_PSF0 0xB0 + +#define PID_CSME0 0x40 +#define PID_PSTH 0x6A +#define PID_ITSS 0x69 +#define PID_RTC 0x6C +#define PID_ISCLK 0x64 +#define PID_DMI 0x2F +#define PID_IOM 0x80 +#define PID_XHCI 0x09 + +/* + * Systemagent + */ +#define SAFBAR 0x68 +#define CRAB_ABORT_BASE_ADDR 0xFEB00000 +#define CRAB_ABORT_SIZE (1 * MiB) +#endif /* _SOC_LUNARLAKE_PLATFORM_SOC_DEFS_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81851?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I90d00628b5342efd9e1d325c12bd6e28f1f47952 Gerrit-Change-Number: 81851 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: soc/intel/common: Add Lunar Lake IAA & OSSE device IDs
by Saurabh Mishra (Code Review) 12 Apr '24

12 Apr '24

Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81850?usp=email ) Change subject: soc/intel/common: Add Lunar Lake IAA & OSSE device IDs ...................................................................... soc/intel/common: Add Lunar Lake IAA & OSSE device IDs Reference: Lunar Lake External Design Specification Volume 1 (734362) Change-Id: I92b65c946682387cbb841d558c6f0a7cb0fcd4ac Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/include/device/pci_ids.h 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/81850/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 5f7c178..8e1c876 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4678,6 +4678,7 @@ #define PCI_DID_INTEL_LNL_TBT_RP0 0xa84e #define PCI_DID_INTEL_LNL_TBT_RP1 0xa84f #define PCI_DID_INTEL_LNL_TBT_RP2 0xa860 +#define PCI_DID_INTEL_LNL_TBT_RP3 0xa837 #define PCI_DID_INTEL_LNL_TBT_DMA0 0xa833 #define PCI_DID_INTEL_LNL_TBT_DMA1 0xa834 #define PCI_DID_INTEL_PTL_TBT_DMA0 0xE433 @@ -4794,6 +4795,14 @@ #define PCI_DID_INTEL_LNL_PSE1 0xa863 #define PCI_DID_INTEL_LNL_PSE2 0xa864 +/* In-memory Analytics Accelerator device IDs */ +#define PCI_DID_INTEL_LNL_IAA 0x642d + +/* OS Security Engine */ +#define PCI_DID_INTEL_LNL_OSSE0 0xa862 +#define PCI_DID_INTEL_LNL_OSSE1 0xa863 +#define PCI_DID_INTEL_LNL_OSSE2 0xa864 + /* Intel Crashlog */ #define PCI_DID_INTEL_TGL_CPU_CRASHLOG_SRAM 0x9a0d #define PCI_DID_INTEL_ADL_CPU_CRASHLOG_SRAM 0x467d -- To view, visit https://review.coreboot.org/c/coreboot/+/81850?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92b65c946682387cbb841d558c6f0a7cb0fcd4ac Gerrit-Change-Number: 81850 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: soc/intel: Add Panther Lake device IDs
by Saurabh Mishra (Code Review) 12 Apr '24

12 Apr '24

Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81849?usp=email ) Change subject: soc/intel: Add Panther Lake device IDs ...................................................................... soc/intel: Add Panther Lake device IDs Added Panther Lake specific CPU and PCIE device IDs Reference: Panher Lake External Design Specification Volume 1 Change-Id: I82f47b6077e28a01f34c59b7e7697323b3d5f990 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/include/cpu/intel/cpu_ids.h M src/include/device/pci_ids.h 2 files changed, 92 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/81849/1 diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index e25e97f..76aded0 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -82,5 +82,6 @@ #define CPUID_RAPTORLAKE_Q0 0xb06a3 #define CPUID_LUNARLAKE_A0_1 0xb06d0 #define CPUID_LUNARLAKE_A0_2 0xb06d1 +#define CPUID_PANTHERLAKE_P 0xC06C0 #endif /* CPU_INTEL_CPU_IDS_H */ diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 4d106a7..5f7c178 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2185,6 +2185,7 @@ #define PCI_DID_INTEL_ADL_N_ISHB 0x54fc #define PCI_DID_INTEL_ADL_P_ISHB 0x51fc #define PCI_DID_INTEL_LNL_ISHB 0xa845 +#define PCI_DID_INTEL_PTL_ISHB 0xE445 /* Intel 82371FB (PIIX) */ #define PCI_DID_INTEL_82371FB_ISA 0x122e @@ -3166,6 +3167,38 @@ #define PCI_DID_INTEL_LNL_ESPI_5 0xa805 #define PCI_DID_INTEL_LNL_ESPI_6 0xa806 #define PCI_DID_INTEL_LNL_ESPI_7 0xa807 +#define PCI_DID_INTEL_PTL_ESPI_0 0xE400 +#define PCI_DID_INTEL_PTL_ESPI_1 0xE401 +#define PCI_DID_INTEL_PTL_ESPI_2 0xE402 +#define PCI_DID_INTEL_PTL_ESPI_3 0xE403 +#define PCI_DID_INTEL_PTL_ESPI_4 0xE404 +#define PCI_DID_INTEL_PTL_ESPI_5 0xE405 +#define PCI_DID_INTEL_PTL_ESPI_6 0xE406 +#define PCI_DID_INTEL_PTL_ESPI_7 0xE407 +#define PCI_DID_INTEL_PTL_ESPI_8 0xE408 +#define PCI_DID_INTEL_PTL_ESPI_9 0xE409 +#define PCI_DID_INTEL_PTL_ESPI_10 0xE40A +#define PCI_DID_INTEL_PTL_ESPI_11 0xE40B +#define PCI_DID_INTEL_PTL_ESPI_12 0xE40C +#define PCI_DID_INTEL_PTL_ESPI_13 0xE40D +#define PCI_DID_INTEL_PTL_ESPI_14 0xE40E +#define PCI_DID_INTEL_PTL_ESPI_15 0xE40F +#define PCI_DID_INTEL_PTL_ESPI_16 0xE410 +#define PCI_DID_INTEL_PTL_ESPI_17 0xE411 +#define PCI_DID_INTEL_PTL_ESPI_18 0xE412 +#define PCI_DID_INTEL_PTL_ESPI_19 0xE413 +#define PCI_DID_INTEL_PTL_ESPI_20 0xE414 +#define PCI_DID_INTEL_PTL_ESPI_21 0xE415 +#define PCI_DID_INTEL_PTL_ESPI_22 0xE416 +#define PCI_DID_INTEL_PTL_ESPI_23 0xE417 +#define PCI_DID_INTEL_PTL_ESPI_24 0xE418 +#define PCI_DID_INTEL_PTL_ESPI_25 0xE419 +#define PCI_DID_INTEL_PTL_ESPI_26 0xE41A +#define PCI_DID_INTEL_PTL_ESPI_27 0xE41B +#define PCI_DID_INTEL_PTL_ESPI_28 0xE41C +#define PCI_DID_INTEL_PTL_ESPI_29 0xE41D +#define PCI_DID_INTEL_PTL_ESPI_30 0xE41E +#define PCI_DID_INTEL_PTL_ESPI_31 0xE41F /* Intel PCIE device ids */ #define PCI_DID_INTEL_LPT_H_PCIE_RP1 0x8c10 @@ -3528,6 +3561,14 @@ #define PCI_DID_INTEL_LNL_PCIE_RP6 0xa83d #define PCI_DID_INTEL_LNL_PCIE_RP7 0xa83e #define PCI_DID_INTEL_LNL_PCIE_RP8 0xa83f +#define PCI_DID_INTEL_PTL_PCIE_RP1 0xE438 +#define PCI_DID_INTEL_PTL_PCIE_RP2 0xE439 +#define PCI_DID_INTEL_PTL_PCIE_RP3 0xE43A +#define PCI_DID_INTEL_PTL_PCIE_RP4 0xE43B +#define PCI_DID_INTEL_PTL_PCIE_RP5 0xE43C +#define PCI_DID_INTEL_PTL_PCIE_RP6 0xE43D +#define PCI_DID_INTEL_PTL_PCIE_RP7 0xE43E +#define PCI_DID_INTEL_PTL_PCIE_RP8 0xE43F #define PCI_DID_INTEL_RPP_S_PCIE_RP1 0x7a38 #define PCI_DID_INTEL_RPP_S_PCIE_RP2 0x7a39 @@ -3672,6 +3713,7 @@ #define PCI_DID_INTEL_RPP_P_PMC 0x51a1 #define PCI_DID_INTEL_RPP_S_PMC 0x7a21 #define PCI_DID_INTEL_LNL_PMC 0xa821 +#define PCI_DID_INTEL_PTL_PMC 0xE421 /* Intel I2C device Ids */ #define PCI_DID_INTEL_LPT_LP_I2C0 0x9c61 @@ -3803,6 +3845,13 @@ #define PCI_DID_INTEL_LNL_I2C4 0xa850 #define PCI_DID_INTEL_LNL_I2C5 0xa851 +#define PCI_DID_INTEL_PTL_I2C0 0xE478 +#define PCI_DID_INTEL_PTL_I2C1 0xE479 +#define PCI_DID_INTEL_PTL_I2C2 0xE47A +#define PCI_DID_INTEL_PTL_I2C3 0xE47B +#define PCI_DID_INTEL_PTL_I2C4 0xE450 +#define PCI_DID_INTEL_PTL_I2C5 0xE451 + /* Intel UART device Ids */ #define PCI_DID_INTEL_LPT_LP_UART0 0x9c63 #define PCI_DID_INTEL_LPT_LP_UART1 0x9c64 @@ -3886,6 +3935,10 @@ #define PCI_DID_INTEL_LNL_UART1 0xa826 #define PCI_DID_INTEL_LNL_UART2 0xa852 +#define PCI_DID_INTEL_PTL_UART0 0xE425 +#define PCI_DID_INTEL_PTL_UART1 0xE426 +#define PCI_DID_INTEL_PTL_UART2 0xE452 + /* Intel SPI device Ids */ #define PCI_DID_INTEL_LPT_LP_GSPI0 0x9c65 #define PCI_DID_INTEL_LPT_LP_GSPI1 0x9c66 @@ -3985,6 +4038,11 @@ #define PCI_DID_INTEL_LNL_GSPI1 0xa830 #define PCI_DID_INTEL_LNL_GSPI2 0xa846 +#define PCI_DID_INTEL_PTL_HWSEQ_SPI 0xE423 +#define PCI_DID_INTEL_PTL_SPI0 0xE427 +#define PCI_DID_INTEL_PTL_SPI1 0xE430 +#define PCI_DID_INTEL_PTL_SPI2 0xE446 + /* Intel IGD device Ids */ #define PCI_DID_INTEL_SKL_GT1F_DT2 0x1902 #define PCI_DID_INTEL_SKL_GT1_SULTM 0x1906 @@ -4147,6 +4205,8 @@ #define PCI_DID_INTEL_RPL_U_GT4 0xa7ac #define PCI_DID_INTEL_RPL_U_GT5 0xa7ad #define PCI_DID_INTEL_LNL_M_GT2 0x64a0 +#define PCI_DID_INTEL_PTL_P_GT2 0x64a0 +#define PCI_DID_INTEL_PTL_P_GT3 0xb080 /* Intel Northbridge Ids */ #define PCI_DID_INTEL_APL_NB 0x5af0 @@ -4290,6 +4350,7 @@ #define PCI_DID_INTEL_RPL_P_ID_8 0xa716 #define PCI_DID_INTEL_LNL_M_ID 0x6400 #define PCI_DID_INTEL_LNL_M_ID_1 0x6410 +#define PCI_DID_INTEL_PTL_P_ID 0xB001 /* Intel SMBUS device Ids */ #define PCI_DID_INTEL_LPT_H_SMBUS 0x8c22 @@ -4319,6 +4380,7 @@ #define PCI_DID_INTEL_RPP_P_SMBUS 0x51a3 #define PCI_DID_INTEL_RPP_S_SMBUS 0x7a23 #define PCI_DID_INTEL_LNL_SMBUS 0xa822 +#define PCI_DID_INTEL_PTL_SMBUS 0xE422 /* Intel EHCI device IDs */ #define PCI_DID_INTEL_LPT_H_EHCI_1 0x8c26 @@ -4361,6 +4423,8 @@ #define PCI_DID_INTEL_RPP_S_XHCI 0x7a60 #define PCI_DID_INTEL_LNL_XHCI 0xa87d #define PCI_DID_INTEL_LNL_TCSS_XHCI 0xa831 +#define PCI_DID_INTEL_PTL_XHCI 0xE47D +#define PCI_DID_INTEL_PTL_TCSS_XHCI 0xE431 /* Intel P2SB device Ids */ #define PCI_DID_INTEL_APL_P2SB 0x5a92 @@ -4389,6 +4453,8 @@ #define PCI_DID_INTEL_RPP_S_P2SB 0x7a20 #define PCI_DID_INTEL_LNL_P2SB 0xa820 #define PCI_DID_INTEL_LNL_P2SB2 0xa84c +#define PCI_DID_INTEL_PTL_P2SB 0xE420 +#define PCI_DID_INTEL_PTL_P2SB2 0xE44C /* Intel SRAM device Ids */ #define PCI_DID_INTEL_APL_SRAM 0x5aec @@ -4404,6 +4470,7 @@ #define PCI_DID_INTEL_MTL_IOE_M_SRAM 0x7ebf #define PCI_DID_INTEL_MTL_IOE_P_SRAM 0x7ecf #define PCI_DID_INTEL_LNL_SRAM 0xa87f +#define PCI_DID_INTEL_PTL_SRAM 0xE47F /* Intel AUDIO device Ids */ #define PCI_DID_INTEL_LPT_H_AUDIO 0x8c20 @@ -4470,6 +4537,15 @@ #define PCI_DID_INTEL_LNL_AUDIO_7 0xa82e #define PCI_DID_INTEL_LNL_AUDIO_8 0xa82f +#define PCI_DID_INTEL_PTL_AUDIO_1 0XE428 +#define PCI_DID_INTEL_PTL_AUDIO_2 0XE429 +#define PCI_DID_INTEL_PTL_AUDIO_3 0XE42A +#define PCI_DID_INTEL_PTL_AUDIO_4 0XE42B +#define PCI_DID_INTEL_PTL_AUDIO_5 0XE42C +#define PCI_DID_INTEL_PTL_AUDIO_6 0XE42D +#define PCI_DID_INTEL_PTL_AUDIO_7 0XE42E +#define PCI_DID_INTEL_PTL_AUDIO_8 0XE42F + /* Intel HECI/ME device Ids */ #define PCI_DID_INTEL_LPT_H_MEI 0x8c3a #define PCI_DID_INTEL_LPT_H_MEI_9 0x8cba @@ -4515,6 +4591,10 @@ #define PCI_DID_INTEL_RPP_S_CSE3 0x7a6d #define PCI_DID_INTEL_MTL_CSE0 0x7e70 #define PCI_DID_INTEL_LNL_CSE0 0xa870 +#define PCI_DID_INTEL_PTL_P_CSE0 0xE470 +#define PCI_DID_INTEL_PTL_P_CSE1 0xE471 +#define PCI_DID_INTEL_PTL_P_CSE2 0xE474 +#define PCI_DID_INTEL_PTL_P_CSE3 0xE475 /* Intel XDCI device Ids */ #define PCI_DID_INTEL_APL_XDCI 0x5aaa @@ -4538,6 +4618,7 @@ #define PCI_DID_INTEL_MTL_XDCI 0x7e7e #define PCI_DID_INTEL_MTL_M_TCSS_XDCI 0x7eb1 #define PCI_DID_INTEL_MTL_P_TCSS_XDCI 0x7ec1 +#define PCI_DID_INTEL_PTL_TCSS_XDCI 0xE432 /* Intel SD device Ids */ #define PCI_DID_INTEL_LPT_LP_SD 0x9c35 @@ -4559,6 +4640,7 @@ /* Intel UFS device Ids */ #define PCI_DID_INTEL_LNL_UFS 0xa847 +#define PCI_DID_INTEL_PTL_UFS 0xE447 /* Intel Thunderbolt device Ids */ #define PCI_DID_INTEL_TGL_TBT_RP0 0x9a23 @@ -4598,6 +4680,8 @@ #define PCI_DID_INTEL_LNL_TBT_RP2 0xa860 #define PCI_DID_INTEL_LNL_TBT_DMA0 0xa833 #define PCI_DID_INTEL_LNL_TBT_DMA1 0xa834 +#define PCI_DID_INTEL_PTL_TBT_DMA0 0xE433 +#define PCI_DID_INTEL_PTL_TBT_DMA1 0xE434 /* Intel WIFI Ids */ #define PCI_DID_1000_SERIES_WIFI 0x0084 @@ -4630,6 +4714,7 @@ #define PCI_DID_TP_6SERIES_WIFI 0x2725 #define PCI_DID_MP_7SERIES_WIFI 0x272b +/* Intel IPU device IDs */ #define PCI_DID_INTEL_TGL_IPU 0x9a19 #define PCI_DID_INTEL_TGL_H_IPU 0x9a39 #define PCI_DID_INTEL_JSL_IPU 0x4e19 @@ -4638,6 +4723,7 @@ #define PCI_DID_INTEL_MTL_IPU 0x7d19 #define PCI_DID_INTEL_RPL_IPU 0xa75d #define PCI_DID_INTEL_LNL_IPU 0x645d +#define PCI_DID_INTEL_PTL_IPU 0xB05D /* Intel Dynamic Tuning Technology Device */ #define PCI_DID_INTEL_CML_DTT 0x1903 @@ -4697,6 +4783,11 @@ #define PCI_DID_INTEL_LNL_CNVI_WIFI_2 0xa842 #define PCI_DID_INTEL_LNL_CNVI_WIFI_3 0xa843 #define PCI_DID_INTEL_LNL_CNVI_BT 0xa876 +#define PCI_DID_INTEL_PTL_CNVI_WIFI_0 0xE440 +#define PCI_DID_INTEL_PTL_CNVI_WIFI_1 0xE441 +#define PCI_DID_INTEL_PTL_CNVI_WIFI_2 0xE442 +#define PCI_DID_INTEL_PTL_CNVI_WIFI_3 0xE443 +#define PCI_DID_INTEL_PTL_CNVI_BT 0xE476 /* Platform Security Engine */ #define PCI_DID_INTEL_LNL_PSE0 0xa862 -- To view, visit https://review.coreboot.org/c/coreboot/+/81849?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I82f47b6077e28a01f34c59b7e7697323b3d5f990 Gerrit-Change-Number: 81849 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: soc/intel/common: Add pantherlake device IDs
by Saurabh Mishra (Code Review) 12 Apr '24

12 Apr '24

Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81848?usp=email ) Change subject: soc/intel/common: Add pantherlake device IDs ...................................................................... soc/intel/common: Add pantherlake device IDs Added Panther Lake device IDs the device specific functions Reference: Panther Lake External Design Specification Volume 1 Change-Id: I941d6e1c8a697234b8e64a2523e60587897d7f7a Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/drivers/intel/ish/ish.c M src/soc/intel/common/block/cnvi/cnvi.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/ipu/ipu.c M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/usb4/usb4.c M src/soc/intel/common/block/usb4/xhci.c M src/soc/intel/common/block/xhci/xhci.c 20 files changed, 90 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/81848/1 diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c index 0ad0bb8..7d332e1 100644 --- a/src/drivers/intel/ish/ish.c +++ b/src/drivers/intel/ish/ish.c @@ -79,6 +79,7 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_ISHB, PCI_DID_INTEL_LNL_ISHB, PCI_DID_INTEL_MTL_ISHB, PCI_DID_INTEL_CNL_ISHB, diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c index e0ea793..bf51e49 100644 --- a/src/soc/intel/common/block/cnvi/cnvi.c +++ b/src/soc/intel/common/block/cnvi/cnvi.c @@ -21,6 +21,10 @@ }; static const unsigned short wifi_pci_device_ids[] = { + PCI_DID_INTEL_PTL_CNVI_WIFI_0, + PCI_DID_INTEL_PTL_CNVI_WIFI_1, + PCI_DID_INTEL_PTL_CNVI_WIFI_2, + PCI_DID_INTEL_PTL_CNVI_WIFI_3, PCI_DID_INTEL_LNL_CNVI_WIFI_0, PCI_DID_INTEL_LNL_CNVI_WIFI_1, PCI_DID_INTEL_LNL_CNVI_WIFI_2, diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index a178405..cb80d1a 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -32,6 +32,7 @@ }; static const struct cpu_device_id cpu_table[] = { + { X86_VENDOR_INTEL, CPUID_PANTHERLAKE_P, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_1, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_2, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_1, CPUID_EXACT_MATCH_MASK }, diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index d0ca57b..26685e5 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1475,6 +1475,7 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_P_CSE0, PCI_DID_INTEL_LNL_CSE0, PCI_DID_INTEL_MTL_CSE0, PCI_DID_INTEL_APL_CSE0, diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 1f11df0..7e8322e 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -13,6 +13,14 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_AUDIO_1, + PCI_DID_INTEL_PTL_AUDIO_2, + PCI_DID_INTEL_PTL_AUDIO_3, + PCI_DID_INTEL_PTL_AUDIO_4, + PCI_DID_INTEL_PTL_AUDIO_5, + PCI_DID_INTEL_PTL_AUDIO_6, + PCI_DID_INTEL_PTL_AUDIO_7, + PCI_DID_INTEL_PTL_AUDIO_8, PCI_DID_INTEL_LNL_AUDIO_1, PCI_DID_INTEL_LNL_AUDIO_2, PCI_DID_INTEL_LNL_AUDIO_3, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index ef4b269..491212f 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -332,6 +332,8 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_P_GT3, + PCI_DID_INTEL_PTL_P_GT2, PCI_DID_INTEL_LNL_M_GT2, PCI_DID_INTEL_RPL_U_GT1, PCI_DID_INTEL_RPL_U_GT2, diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index 44c0341..ca50312 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -21,6 +21,14 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_AUDIO_1, + PCI_DID_INTEL_PTL_AUDIO_2, + PCI_DID_INTEL_PTL_AUDIO_3, + PCI_DID_INTEL_PTL_AUDIO_4, + PCI_DID_INTEL_PTL_AUDIO_5, + PCI_DID_INTEL_PTL_AUDIO_6, + PCI_DID_INTEL_PTL_AUDIO_7, + PCI_DID_INTEL_PTL_AUDIO_8, PCI_DID_INTEL_LNL_AUDIO_1, PCI_DID_INTEL_LNL_AUDIO_2, PCI_DID_INTEL_LNL_AUDIO_3, diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index c0f0b6e0..f84b2cd 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -174,6 +174,12 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_I2C0, + PCI_DID_INTEL_PTL_I2C1, + PCI_DID_INTEL_PTL_I2C2, + PCI_DID_INTEL_PTL_I2C3, + PCI_DID_INTEL_PTL_I2C4, + PCI_DID_INTEL_PTL_I2C5, PCI_DID_INTEL_LNL_I2C0, PCI_DID_INTEL_LNL_I2C1, PCI_DID_INTEL_LNL_I2C2, diff --git a/src/soc/intel/common/block/ipu/ipu.c b/src/soc/intel/common/block/ipu/ipu.c index b2d3904..989da2e 100644 --- a/src/soc/intel/common/block/ipu/ipu.c +++ b/src/soc/intel/common/block/ipu/ipu.c @@ -12,6 +12,7 @@ }; static const uint16_t pci_device_ids[] = { + PCI_DID_INTEL_PTL_IPU, PCI_DID_INTEL_LNL_IPU, PCI_DID_INTEL_RPL_IPU, PCI_DID_INTEL_MTL_IPU, diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index e805035..20b8bfb 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -141,6 +141,38 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_ESPI_0, + PCI_DID_INTEL_PTL_ESPI_1, + PCI_DID_INTEL_PTL_ESPI_2, + PCI_DID_INTEL_PTL_ESPI_3, + PCI_DID_INTEL_PTL_ESPI_4, + PCI_DID_INTEL_PTL_ESPI_5, + PCI_DID_INTEL_PTL_ESPI_6, + PCI_DID_INTEL_PTL_ESPI_7, + PCI_DID_INTEL_PTL_ESPI_8, + PCI_DID_INTEL_PTL_ESPI_9, + PCI_DID_INTEL_PTL_ESPI_10, + PCI_DID_INTEL_PTL_ESPI_11, + PCI_DID_INTEL_PTL_ESPI_12, + PCI_DID_INTEL_PTL_ESPI_13, + PCI_DID_INTEL_PTL_ESPI_14, + PCI_DID_INTEL_PTL_ESPI_15, + PCI_DID_INTEL_PTL_ESPI_16, + PCI_DID_INTEL_PTL_ESPI_17, + PCI_DID_INTEL_PTL_ESPI_18, + PCI_DID_INTEL_PTL_ESPI_19, + PCI_DID_INTEL_PTL_ESPI_20, + PCI_DID_INTEL_PTL_ESPI_21, + PCI_DID_INTEL_PTL_ESPI_22, + PCI_DID_INTEL_PTL_ESPI_23, + PCI_DID_INTEL_PTL_ESPI_24, + PCI_DID_INTEL_PTL_ESPI_25, + PCI_DID_INTEL_PTL_ESPI_26, + PCI_DID_INTEL_PTL_ESPI_27, + PCI_DID_INTEL_PTL_ESPI_28, + PCI_DID_INTEL_PTL_ESPI_29, + PCI_DID_INTEL_PTL_ESPI_30, + PCI_DID_INTEL_PTL_ESPI_31, PCI_DID_INTEL_LNL_ESPI_0, PCI_DID_INTEL_LNL_ESPI_1, PCI_DID_INTEL_LNL_ESPI_2, diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 5c6681d..3c5e26a 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -67,6 +67,14 @@ }; static const unsigned short pcie_device_ids[] = { + PCI_DID_INTEL_PTL_PCIE_RP1, + PCI_DID_INTEL_PTL_PCIE_RP2, + PCI_DID_INTEL_PTL_PCIE_RP3, + PCI_DID_INTEL_PTL_PCIE_RP4, + PCI_DID_INTEL_PTL_PCIE_RP5, + PCI_DID_INTEL_PTL_PCIE_RP6, + PCI_DID_INTEL_PTL_PCIE_RP7, + PCI_DID_INTEL_PTL_PCIE_RP8, PCI_DID_INTEL_LNL_PCIE_RP1, PCI_DID_INTEL_LNL_PCIE_RP2, PCI_DID_INTEL_LNL_PCIE_RP3, diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index ca575ff..bc70b1a 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -111,6 +111,7 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_PMC, PCI_DID_INTEL_LNL_PMC, PCI_DID_INTEL_MTL_SOC_PMC, PCI_DID_INTEL_MTL_IOE_M_PMC, diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index 97651c0..7f87a52 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -49,6 +49,7 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_SMBUS, PCI_DID_INTEL_LNL_SMBUS, PCI_DID_INTEL_MTL_SMBUS, PCI_DID_INTEL_RPP_P_SMBUS, diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index d1063f1..0e8aa26 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -123,6 +123,10 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_HWSEQ_SPI, + PCI_DID_INTEL_PTL_SPI0, + PCI_DID_INTEL_PTL_SPI1, + PCI_DID_INTEL_PTL_SPI2, PCI_DID_INTEL_LNL_GSPI0, PCI_DID_INTEL_LNL_GSPI1, PCI_DID_INTEL_LNL_GSPI2, diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index cd8c3fd..8d0387b 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -33,6 +33,7 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_SRAM, PCI_DID_INTEL_LNL_SRAM, PCI_DID_INTEL_MTL_SOC_SRAM, PCI_DID_INTEL_MTL_IOE_M_SRAM, diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 97044ec..d5fb83a 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -414,6 +414,7 @@ }; static const unsigned short systemagent_ids[] = { + PCI_DID_INTEL_PTL_P_ID, PCI_DID_INTEL_LNL_M_ID, PCI_DID_INTEL_LNL_M_ID_1, PCI_DID_INTEL_MTL_M_ID, diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index c03f5a9..e52bb0f 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -309,6 +309,7 @@ static const char *uart_acpi_name(const struct device *dev) { switch (dev->device) { + case PCI_DID_INTEL_PTL_UART0: case PCI_DID_INTEL_LNL_UART0: case PCI_DID_INTEL_ADP_P_UART0: case PCI_DID_INTEL_APL_UART0: @@ -317,6 +318,7 @@ case PCI_DID_INTEL_SPT_H_UART0: case PCI_DID_INTEL_CNP_H_UART0: return "UAR0"; + case PCI_DID_INTEL_PTL_UART1: case PCI_DID_INTEL_LNL_UART1: case PCI_DID_INTEL_ADP_P_UART1: case PCI_DID_INTEL_APL_UART1: @@ -325,6 +327,7 @@ case PCI_DID_INTEL_SPT_H_UART1: case PCI_DID_INTEL_CNP_H_UART1: return "UAR1"; + case PCI_DID_INTEL_PTL_UART2: case PCI_DID_INTEL_LNL_UART2: case PCI_DID_INTEL_ADP_P_UART2: case PCI_DID_INTEL_APL_UART2: @@ -352,6 +355,9 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_UART0, + PCI_DID_INTEL_PTL_UART1, + PCI_DID_INTEL_PTL_UART2, PCI_DID_INTEL_LNL_UART0, PCI_DID_INTEL_LNL_UART1, PCI_DID_INTEL_LNL_UART2, diff --git a/src/soc/intel/common/block/usb4/usb4.c b/src/soc/intel/common/block/usb4/usb4.c index a47bb9b..ff898ab 100644 --- a/src/soc/intel/common/block/usb4/usb4.c +++ b/src/soc/intel/common/block/usb4/usb4.c @@ -52,6 +52,8 @@ #endif static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_TBT_DMA0, + PCI_DID_INTEL_PTL_TBT_DMA1, PCI_DID_INTEL_LNL_TBT_DMA0, PCI_DID_INTEL_LNL_TBT_DMA1, PCI_DID_INTEL_RPL_TBT_DMA0, diff --git a/src/soc/intel/common/block/usb4/xhci.c b/src/soc/intel/common/block/usb4/xhci.c index 4912e1a..4e1a2a8 100644 --- a/src/soc/intel/common/block/usb4/xhci.c +++ b/src/soc/intel/common/block/usb4/xhci.c @@ -26,6 +26,7 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_TCSS_XHCI, PCI_DID_INTEL_LNL_TCSS_XHCI, PCI_DID_INTEL_RPP_P_TCSS_XHCI, PCI_DID_INTEL_MTL_M_TCSS_XHCI, diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 03ed578..dd4e5de 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -131,6 +131,7 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_XHCI, PCI_DID_INTEL_LNL_XHCI, PCI_DID_INTEL_MTL_XHCI, PCI_DID_INTEL_APL_XHCI, -- To view, visit https://review.coreboot.org/c/coreboot/+/81848?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I941d6e1c8a697234b8e64a2523e60587897d7f7a Gerrit-Change-Number: 81848 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/intel/{common, lunarlake}: Add support for new MCH
by Saurabh Mishra (Code Review) 12 Apr '24

12 Apr '24

Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81847?usp=email ) Change subject: soc/intel/{common, lunarlake}: Add support for new MCH ...................................................................... soc/intel/{common, lunarlake}: Add support for new MCH Details: - The patch adds support for new Lunar Lake MCH (ID:0x6410). - Add new CPU ID (ID:0xb06d1) Reference: Lunar Lake External Design Specification Volume 1 (734362) TEST=Build and boot the system having MCH ID:0x6410. Change-Id: I976d7f269485633d835d204afa224736d71baaa8 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/include/cpu/intel/cpu_ids.h M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/systemagent/systemagent.c 4 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/81847/1 diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index ddb4e54..e25e97f 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -81,5 +81,6 @@ #define CPUID_RAPTORLAKE_J0 0xb06a2 #define CPUID_RAPTORLAKE_Q0 0xb06a3 #define CPUID_LUNARLAKE_A0_1 0xb06d0 +#define CPUID_LUNARLAKE_A0_2 0xb06d1 #endif /* CPU_INTEL_CPU_IDS_H */ diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 7831d5b..4d106a7 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4289,6 +4289,7 @@ #define PCI_DID_INTEL_RPL_P_ID_7 0xa70a #define PCI_DID_INTEL_RPL_P_ID_8 0xa716 #define PCI_DID_INTEL_LNL_M_ID 0x6400 +#define PCI_DID_INTEL_LNL_M_ID_1 0x6410 /* Intel SMBUS device Ids */ #define PCI_DID_INTEL_LPT_H_SMBUS 0x8c22 diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 7abbb40..a178405 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -33,6 +33,7 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_1, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_2, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_1, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_2, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_METEORLAKE_B0, CPUID_EXACT_MATCH_MASK }, diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index b53814e3..97044ec 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -415,6 +415,7 @@ static const unsigned short systemagent_ids[] = { PCI_DID_INTEL_LNL_M_ID, + PCI_DID_INTEL_LNL_M_ID_1, PCI_DID_INTEL_MTL_M_ID, PCI_DID_INTEL_MTL_P_ID_1, PCI_DID_INTEL_MTL_P_ID_2, -- To view, visit https://review.coreboot.org/c/coreboot/+/81847?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I976d7f269485633d835d204afa224736d71baaa8 Gerrit-Change-Number: 81847 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/intel/common: Add Lunar Lake CNVI device IDs
by Saurabh Mishra (Code Review) 12 Apr '24

12 Apr '24

Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81846?usp=email ) Change subject: soc/intel/common: Add Lunar Lake CNVI device IDs ...................................................................... soc/intel/common: Add Lunar Lake CNVI device IDs Reference: Lunar Lake External Design Specification Volume 1 (734362) Change-Id: I5a0a3fbc9f43a6a573e33fcf3901055e10faaed1 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/soc/intel/common/block/cnvi/cnvi.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/81846/1 diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c index fed95492..e0ea793 100644 --- a/src/soc/intel/common/block/cnvi/cnvi.c +++ b/src/soc/intel/common/block/cnvi/cnvi.c @@ -21,6 +21,10 @@ }; static const unsigned short wifi_pci_device_ids[] = { + PCI_DID_INTEL_LNL_CNVI_WIFI_0, + PCI_DID_INTEL_LNL_CNVI_WIFI_1, + PCI_DID_INTEL_LNL_CNVI_WIFI_2, + PCI_DID_INTEL_LNL_CNVI_WIFI_3, PCI_DID_INTEL_MTL_CNVI_WIFI_0, PCI_DID_INTEL_MTL_CNVI_WIFI_1, PCI_DID_INTEL_MTL_CNVI_WIFI_2, -- To view, visit https://review.coreboot.org/c/coreboot/+/81846?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5a0a3fbc9f43a6a573e33fcf3901055e10faaed1 Gerrit-Change-Number: 81846 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: util/inteltool/inteltool.h: add Device IDs
by Filip Lewiński (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Pratikkumar V Prajapati. Filip Lewiński has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81845?usp=email ) Change subject: util/inteltool/inteltool.h: add Device IDs ...................................................................... util/inteltool/inteltool.h: add Device IDs Change-Id: I94949470c845e08d7f55e9d6b94c993cb24e73ea Signed-off-by: Filip Lewiński <filip.lewinski(a)3mdeb.com> --- M util/inteltool/inteltool.h 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/81845/1 diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 55f9985..2f727f3 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -239,6 +239,8 @@ #define PCI_DEVICE_ID_INTEL_Q670E 0x7a91 #define PCI_DEVICE_ID_INTEL_H610E 0x7a92 + + #define PCI_DEVICE_ID_INTEL_W790 0x7a8a #define PCI_DEVICE_ID_INTEL_Z790 0x7a04 #define PCI_DEVICE_ID_INTEL_H770 0x7a05 @@ -392,6 +394,14 @@ #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_8 0x4617 /* Alderlake N 0+8 */ #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4 0x461b /* Alderlake N 0+4 */ #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4_1 0x461c /* Alderlake N 0+4 */ +//--- +#define PCI_DEVICE_ID_INTEL_CORE_MTL_ID_M 0x7D00 +#define PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_1 0x7D01 +#define PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_2 0x7D02 +#define PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_3 0x7d14 +#define PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_4 0x7d15 +#define PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_5 0x7d16 +//--- #define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_8_6 0xa706 /* Raptorlake H 8+6 */ /* Intel GPUs */ @@ -476,6 +486,13 @@ #define PCI_DEVICE_ID_INTEL_ADL_N_UHD 0x46D0 #define PCI_DEVICE_ID_INTEL_ADL_N_UHD_2 0x46D1 #define PCI_DEVICE_ID_INTEL_ADL_N_UHD_3 0x46D2 +//---- +#define PCI_DEVICE_ID_INTEL_MTL_M_GT2 0x7d40 +#define PCI_DEVICE_ID_INTEL_MTL_P_GT2_1 0x7d45 +#define PCI_DEVICE_ID_INTEL_MTL_P_GT2_2 0x7d50 +#define PCI_DEVICE_ID_INTEL_MTL_P_GT2_3 0x7d55 +#define PCI_DEVICE_ID_INTEL_MTL_P_GT2_4 0x7d60 +//--- #define PCI_DEVICE_ID_INTEL_RPL_H_IRIS_XE 0xa7a0 #if !defined(__DARWIN__) && !defined(__FreeBSD__) -- To view, visit https://review.coreboot.org/c/coreboot/+/81845?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I94949470c845e08d7f55e9d6b94c993cb24e73ea Gerrit-Change-Number: 81845 Gerrit-PatchSet: 1 Gerrit-Owner: Filip Lewiński Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: util/inteltool/gpio_names/meteorlake.h: set .pcr_port_id
by Filip Lewiński (Code Review) 12 Apr '24

12 Apr '24

Filip Lewiński has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81844?usp=email ) Change subject: util/inteltool/gpio_names/meteorlake.h: set .pcr_port_id ...................................................................... util/inteltool/gpio_names/meteorlake.h: set .pcr_port_id Change-Id: I3f8ed04c6b85987a81d598b5400767a7bbc476c6 Signed-off-by: Filip Lewiński <filip.lewinski(a)3mdeb.com> --- M util/inteltool/gpio_names/meteorlake.h 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/81844/1 diff --git a/util/inteltool/gpio_names/meteorlake.h b/util/inteltool/gpio_names/meteorlake.h index c0b986d..9144c7e 100644 --- a/util/inteltool/gpio_names/meteorlake.h +++ b/util/inteltool/gpio_names/meteorlake.h @@ -357,7 +357,7 @@ const struct gpio_community meteorlake_pch_community_0 = { .name = "------- GPIO Community 0 -------", - .pcr_port_id = 0x6e, + .pcr_port_id = 0xd1, .group_count = ARRAY_SIZE(meteorlake_pch_community_0_groups), .groups = meteorlake_pch_community_0_groups, }; @@ -370,7 +370,7 @@ const struct gpio_community meteorlake_pch_community_1 = { .name = "------- GPIO Community 1 -------", - .pcr_port_id = 0x6e, + .pcr_port_id = 0xd2, .group_count = ARRAY_SIZE(meteorlake_pch_community_1_groups), .groups = meteorlake_pch_community_1_groups, }; @@ -384,7 +384,7 @@ const struct gpio_community meteorlake_pch_community_3 = { .name = "------- GPIO Community 3 -------", - .pcr_port_id = 0x6e, + .pcr_port_id = 0xd3, .group_count = ARRAY_SIZE(meteorlake_pch_community_3_groups), .groups = meteorlake_pch_community_3_groups, }; @@ -396,7 +396,7 @@ const struct gpio_community meteorlake_pch_community_4 = { .name = "------- GPIO Community 4 -------", - .pcr_port_id = 0x6e, + .pcr_port_id = 0xd4, .group_count = ARRAY_SIZE(meteorlake_pch_community_4_groups), .groups = meteorlake_pch_community_4_groups, }; @@ -410,7 +410,7 @@ const struct gpio_community meteorlake_pch_community_5 = { .name = "------- GPIO Community 5 -------", - .pcr_port_id = 0x6e, + .pcr_port_id = 0xd5, .group_count = ARRAY_SIZE(meteorlake_pch_community_5_groups), .groups = meteorlake_pch_community_5_groups, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/81844?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f8ed04c6b85987a81d598b5400767a7bbc476c6 Gerrit-Change-Number: 81844 Gerrit-PatchSet: 1 Gerrit-Owner: Filip Lewiński Gerrit-MessageType: newchange

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