coreboot-gerrit April 2024

coreboot-gerrit@coreboot.org

1 participants
3292 discussions

[XS] Change in coreboot[main]: mb/dell/optiplex_9020: Fix SATA port maps
by Felix Held (Code Review) 12 Apr '24

12 Apr '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81550?usp=email ) Change subject: mb/dell/optiplex_9020: Fix SATA port maps ...................................................................... mb/dell/optiplex_9020: Fix SATA port maps Previously incorrect sets of SATA ports were enabled. There are no publically available schematics, but I am almost certain the new values are correct. The original 0x33 value was carlessly copy pasted, and only enables ports 0, 1, 4, 5, leaving 2, 3 disabled. On the SFF, with 0x33 only the first 2 ports worked. I have verified by plugging in devices under the stock firmware that 0, 1, 2 are the ones that should be enabled, so setting the value to 0x7 per datasheet. This was also tested in practice to work. I don't have an MT, but I was told the two white ports didn't work with 0x33, so those are most certainly ports 3, 4, hence me setting the value to 0xf. If the MT's working ports are port 0, 1 on the PCH this is correct. Signed-off-by: Mate Kukri <kukri.mate(a)gmail.com> Change-Id: I32cb236b8f8140fba4a04c23161363d21741dcbc Reviewed-on: https://review.coreboot.org/c/coreboot/+/81550 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/dell/optiplex_9020/devicetree.cb M src/mainboard/dell/optiplex_9020/overridetree_mt.cb 2 files changed, 3 insertions(+), 1 deletion(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb index c0b17a1..dce5869 100644 --- a/src/mainboard/dell/optiplex_9020/devicetree.cb +++ b/src/mainboard/dell/optiplex_9020/devicetree.cb @@ -23,7 +23,7 @@ register "gen2_dec" = "0x007c0901" register "gen3_dec" = "0x003c07e1" register "gen4_dec" = "0x001c0901" - register "sata_port_map" = "0x33" + register "sata_port_map" = "0x7" device pci 14.0 on end # xHCI controller device pci 16.0 on end # Management Engine interface 1 diff --git a/src/mainboard/dell/optiplex_9020/overridetree_mt.cb b/src/mainboard/dell/optiplex_9020/overridetree_mt.cb index 90205c2..a781960 100644 --- a/src/mainboard/dell/optiplex_9020/overridetree_mt.cb +++ b/src/mainboard/dell/optiplex_9020/overridetree_mt.cb @@ -3,6 +3,8 @@ chip northbridge/intel/haswell device domain 0 on chip southbridge/intel/lynxpoint + register "sata_port_map" = "0xf" + device pci 1c.1 on end # PCI (via XIO2001 bridge) device pci 1c.2 on end # PCIe 1x slot end -- To view, visit https://review.coreboot.org/c/coreboot/+/81550?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32cb236b8f8140fba4a04c23161363d21741dcbc Gerrit-Change-Number: 81550 Gerrit-PatchSet: 4 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XL] Change in coreboot[main]: lib/device_tree: Add some FDT helper functions
by Maximilian Brune (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Jakub Czapiga, Julius Werner, Martin L Roth. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81081?usp=email ) Change subject: lib/device_tree: Add some FDT helper functions ...................................................................... Patch Set 18: (1 comment) File src/lib/device_tree.c: https://review.coreboot.org/c/coreboot/+/81081/comment/8d97837b_0f4d6661 : PS18, Line 175: "" > Okay, sorry, I see your point now. […] ``` In that case, how about just making the function take both offsets (parent_node_offset and child_array_offset) as parameters instead? ``` I have to return the addr-cells and size-cells, but changing the order of the `*path == NULL` check makes it tricky, because instead of getting the addr-cells/size-cells of the parent I will get it from the current node. Any suggestions? -- To view, visit https://review.coreboot.org/c/coreboot/+/81081?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2fb1d93c5b3e1cb2f7d9584db52bbce3767b63d8 Gerrit-Change-Number: 81081 Gerrit-PatchSet: 18 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 12 Apr 2024 16:10:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: include: Add 'IWYU pragma: export' comment
by Elyes Haouas (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Eric Lai. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81824?usp=email ) Change subject: include: Add 'IWYU pragma: export' comment ...................................................................... Patch Set 3: (1 comment) File src/include/device/device.h: https://review.coreboot.org/c/coreboot/+/81824/comment/4ed92080_b1f04885 : PS2, Line 12: #include <device/pci_type.h> > to move <device/pci_type. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81824?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3acb5e6b18443e454d8174b0b1f9d207c0fb78b5 Gerrit-Change-Number: 81824 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Comment-Date: Fri, 12 Apr 2024 15:53:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: nb/intel/haswell: Fix building BDW MRC.bin path with clang
by Angel Pons (Code Review) 12 Apr '24

12 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81862?usp=email ) Change subject: nb/intel/haswell: Fix building BDW MRC.bin path with clang ...................................................................... nb/intel/haswell: Fix building BDW MRC.bin path with clang Clang complains that the two enumerations are incompatible. However, the values themselves are the same (0: mobile, 1: desktop, 5: ULT). So, cast the function's return value to silence the warning. Change-Id: If7b5e22e893e9f3f17a15197c65448fb782590f6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/broadwell_mrc/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/81862/1 diff --git a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c index b8a9416..e7e9b63 100644 --- a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c @@ -331,7 +331,7 @@ struct pei_data pei_data = { .pei_version = PEI_VERSION, - .board_type = get_pch_platform_type(), + .board_type = (enum board_type)get_pch_platform_type(), .usbdebug = CONFIG(USBDEBUG), .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, -- To view, visit https://review.coreboot.org/c/coreboot/+/81862?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7b5e22e893e9f3f17a15197c65448fb782590f6 Gerrit-Change-Number: 81862 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: mb/google/brox: Create greenbayupoc variant
by Karthik Ramasubramanian (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Eren Peng, Ivan Chen, Shelley Chen, Sumeet R Pawnikar. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81565?usp=email ) Change subject: mb/google/brox: Create greenbayupoc variant ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81565?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I90936d97b41e59c49dd92997146caf580bce1f4f Gerrit-Change-Number: 81565 Gerrit-PatchSet: 5 Gerrit-Owner: Eren Peng <peng.eren(a)inventec.corp-partner.google.com> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Garen Wu <wu.garen(a)inventec.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <hsueh.rasheed(a)inventec.corp-partner.google.com> Gerrit-CC: Steven Yeh <yeh.stevenct(a)inventec.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Eren Peng <peng.eren(a)inventec.corp-partner.google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Ivan Chen <yulunchen(a)google.com> Gerrit-Comment-Date: Fri, 12 Apr 2024 15:12:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: nb/intel/gm45: Fill in memory info
by Angel Pons (Code Review) 12 Apr '24

12 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81861?usp=email ) Change subject: nb/intel/gm45: Fill in memory info ...................................................................... nb/intel/gm45: Fill in memory info Fill in memory info so that coreboot can generate SMBIOS Type 17 tables. The S/N, P/N and module ID fields are only populated for DDR3. Change-Id: I92060ce05bdf0ca617a3383a2db1fdbd43df6fe4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/gm45/Makefile.mk M src/northbridge/intel/gm45/gm45.h A src/northbridge/intel/gm45/raminit_meminfo.c M src/northbridge/intel/gm45/romstage.c 4 files changed, 88 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/81861/1 diff --git a/src/northbridge/intel/gm45/Makefile.mk b/src/northbridge/intel/gm45/Makefile.mk index db9dc3f..a26565ff 100644 --- a/src/northbridge/intel/gm45/Makefile.mk +++ b/src/northbridge/intel/gm45/Makefile.mk @@ -10,6 +10,7 @@ romstage-y += raminit_rcomp_calibration.c romstage-y += raminit_receive_enable_calibration.c romstage-y += raminit_read_write_training.c +romstage-y += raminit_meminfo.c romstage-y += pcie.c romstage-y += thermal.c romstage-y += igd.c diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index d929533..5d9ac56 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -412,6 +412,7 @@ void get_gmch_info(sysinfo_t *); void raminit(sysinfo_t *, int s3resume); void raminit_thermal(const sysinfo_t *); +void setup_sdram_meminfo(const sysinfo_t *); void init_igd(const sysinfo_t *const); void init_pm(const sysinfo_t *, int do_freq_scaling_cfg); void igd_compute_ggc(sysinfo_t *const sysinfo); diff --git a/src/northbridge/intel/gm45/raminit_meminfo.c b/src/northbridge/intel/gm45/raminit_meminfo.c new file mode 100644 index 0000000..6e179ad --- /dev/null +++ b/src/northbridge/intel/gm45/raminit_meminfo.c @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbmem.h> +#include <console/console.h> +#include <device/dram/ddr2.h> +#include <device/dram/ddr3.h> +#include <device/smbus_host.h> +#include <lib.h> +#include <memory_info.h> +#include <spd.h> + +#include "gm45.h" +#include "chip.h" + +static u8 get_dimm_mod_type(const sysinfo_t *sysinfo, const int idx) +{ + if (sysinfo->spd_type == DDR2) { + return smbus_read_byte(sysinfo->spd_map[idx], 20) & SPD_DDR2_DIMM_TYPE_MASK; + } else { + return smbus_read_byte(sysinfo->spd_map[idx], 3) & 0xf; + } +} + +static void ddr3_read_ids(const sysinfo_t *sysinfo, struct dimm_info *dimm, const int idx) +{ + const u8 addr = sysinfo->spd_map[idx]; + for (int k = 0; k < SPD_DIMM_SERIAL_LEN; k++) { + dimm->serial[k] = smbus_read_byte(addr, SPD_DIMM_SERIAL_NUM + k); + } + for (int k = 0; k < SPD_DIMM_PART_LEN; k++) { + dimm->module_part_number[k] = smbus_read_byte(addr, SPD_DIMM_PART_NUM + k); + } + dimm->mod_id = (smbus_read_byte(addr, SPD_DIMM_MOD_ID2) << 8) | + (smbus_read_byte(addr, SPD_DIMM_MOD_ID1) << 0); +} + +static u32 get_mem_clock_mt(const int clock_index) +{ + switch (clock_index) { + case MEM_CLOCK_1067MT: return 1067; + case MEM_CLOCK_800MT: return 800; + case MEM_CLOCK_667MT: return 667; + default: return 0; + } +} + +void setup_sdram_meminfo(const sysinfo_t *sysinfo) +{ + struct memory_info *mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); + if (!mem_info) + die("Failed to add memory info to CBMEM.\n"); + + memset(mem_info, 0, sizeof(struct memory_info)); + + const u16 ddr_type = (sysinfo->spd_type == DDR2) ? MEMORY_TYPE_DDR2 : MEMORY_TYPE_DDR3; + const u32 ddr_freq_mt = get_mem_clock_mt(sysinfo->selected_timings.mem_clock); + + int dimm_cnt = 0; + + int ch, r; + FOR_EACH_POPULATED_RANK(sysinfo->dimms, ch, r) { + struct dimm_info *dimm = &mem_info->dimm[dimm_cnt]; + const int idx = ch * 2 + r; + dimm->dimm_size = 256 << sysinfo->dimms[ch].chip_capacity; + dimm->ddr_type = ddr_type; + dimm->ddr_frequency = ddr_freq_mt; + dimm->rank_per_dimm = sysinfo->dimms[ch].ranks; + dimm->channel_num = ch; + dimm->dimm_num = 0; + dimm->bank_locator = ch; + /* TODO: Handle DDR2 SPDs */ + if (sysinfo->spd_type == DDR3) { + ddr3_read_ids(sysinfo, dimm, idx); + } + dimm->mod_type = get_dimm_mod_type(sysinfo, idx); + dimm->bus_width = MEMORY_BUS_WIDTH_64; + dimm_cnt++; + } + mem_info->dimm_cnt = dimm_cnt; + + mem_info->ecc_type = MEMORY_ARRAY_ECC_NONE; + mem_info->max_capacity_mib = 8192; + mem_info->number_of_devices = 2; +} diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index 01df965..9ed3c00 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -91,6 +91,8 @@ cbmem_initted = !cbmem_recovery(s3resume); + setup_sdram_meminfo(&sysinfo); + romstage_handoff_init(cbmem_initted && s3resume); printk(BIOS_SPEW, "exit main()\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/81861?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92060ce05bdf0ca617a3383a2db1fdbd43df6fe4 Gerrit-Change-Number: 81861 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[main]: mb/asrock/z97_extreme6: Add new mainboard
by Paul Menzel (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Angel Pons, Felix Singer, Martin L Roth. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68188?usp=email ) Change subject: mb/asrock/z97_extreme6: Add new mainboard ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68188?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If1d22547725e59f435de36b973e1bf4f334269a9 Gerrit-Change-Number: 68188 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 12 Apr 2024 15:05:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[L] Change in coreboot[main]: util/inteltool/gpio_names/meteorlake.h: init add
by Filip Lewiński (Code Review) 12 Apr '24

12 Apr '24

Filip Lewiński has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81843?usp=email ) Change subject: util/inteltool/gpio_names/meteorlake.h: init add ...................................................................... util/inteltool/gpio_names/meteorlake.h: init add Change-Id: I7473119fa97c57cd2a1303f08f964abd0ca96270 Signed-off-by: Filip Lewiński <filip.lewinski(a)3mdeb.com> --- A util/inteltool/gpio_names/meteorlake.h 1 file changed, 433 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/81843/1 diff --git a/util/inteltool/gpio_names/meteorlake.h b/util/inteltool/gpio_names/meteorlake.h new file mode 100644 index 0000000..c0b986d --- /dev/null +++ b/util/inteltool/gpio_names/meteorlake.h @@ -0,0 +1,433 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef GPIO_NAMES_METEORLAKE +#define GPIO_NAMES_METEORLAKE + +#include "gpio_groups.h" + +/* ----------------------------- Meteor Lake ----------------------------- */ + +const char *const meteorlake_pch_group_a_names[] = { + "GPP_A0", "ESPI_IO0", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_A1", "ESPI_IO1", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_A2", "ESPI_IO2", "SUSWARN# / SUSPWRDNACK", "n/a", "n/a", "n/a", "n/a", + "GPP_A3", "ESPI_IO3", "SUSACK#", "n/a", "n/a", "n/a", "n/a", + "GPP_A4", "ESPI_CS0#", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_A5", "ESPI_ALERT0#", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_A6", "ESPI_ALERT1#", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_A7", "SRCCLK_OE7#", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_A8", "SRCCLKREQ7#", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_A9", "ESPI_CLK", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_A10", "ESPI_RESET#", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_A11", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_A12", "SATAXPCIE1", "SATAGP1", "n/a", "SRCCLKREQ9B#", "n/a", "n/a", + "GPP_A13", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_A14", "USB_OC1#", "DDSP_HPD3", "n/a", "DISP_MISC3", "n/a", "n/a", + "GPP_A15", "USB_OC2#", "DDSP_HPD4", "n/a", "DISP_MISC4", "n/a", "n/a", + "GPP_A16", "USB_OC3#", "n/a", "n/a", "ISH_GP5", "n/a", "n/a", + "GPP_A17", "n/a", "n/a", "n/a", "DISP_MISCC", "n/a", "n/a", + "GPP_A18", "DDSP_HPDB", "n/a", "n/a", "DISP_MISCB", "n/a", "n/a", + "GPP_A19", "DDSP_HPD1", "n/a", "n/a", "DISP_MISC1", "n/a", "n/a", + "GPP_A20", "DDSP_HPD2", "n/a", "n/a", "DISP_MISC2", "n/a", "n/a", + "GPP_A21", "DDPC_CTRLCLK", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_A22", "DDPC_CTRLDATA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_A23", "ESPI_CS1#", "n/a", "n/a", "n/a", "n/a", "n/a", +}; + +const struct gpio_group meteorlake_pch_group_a = { + .display = "------- GPIO Group GPP_A -------", + .pad_count = ARRAY_SIZE(meteorlake_pch_group_a_names) / 7, + .func_count = 7, + .pad_names = meteorlake_pch_group_a_names, +}; + +/* +"n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", +"n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", +*/ + +const char *const meteorlake_pch_group_b_names[] = { + "GPP_B0", "CORE_VID0", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_B1", "CORE_VID1", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_B2", "VRALERT#", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_B3", "PROC_GP2", "n/a", "n/a", "ISH_GP4B", "n/a", "n/a", + "GPP_B4", "PROC_GP3", "n/a", "n/a", "ISH_GP5B", "n/a", "n/a", + "GPP_B5", "ISH_I2C0_SDA", "I2C2_SDA", "n/a", "n/a", "n/a", "n/a", + "GPP_B6", "ISH_I2C0_SCL", "I2C2_SCL", "n/a", "n/a", "n/a", "n/a", + "GPP_B7", "ISH_I2C1_SDA", "I2C3_SDA", "n/a", "n/a", "n/a", "n/a", + "GPP_B8", "ISH_I2C1_SCL", "I2C3_SCL", "n/a", "n/a", "n/a", "n/a", + + "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + + "GPP_B11", "PMCALERT#", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_B12", "SLP_S0#", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_B13", "PLTRST#", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_B14", "SPKR", "TIME_SYNC1", "n/a", "SATA_LED#", "n/a", "ISH_GP6", + "GPP_B15", "n/a", "TIME_SYNC0", "n/a", "n/a", "n/a", "ISH_GP7", + "GPP_B16", "n/a", "I2C5_SDA", "n/a", "ISH_I2C2_SDA", "n/a", "n/a", + "GPP_B17", "n/a", "I2C5_SCL", "n/a", "ISH_I2C2_SCL", "n/a", "n/a", + "GPP_B18", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + + "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + + "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a", "n/a", "n/a", "n/a", + +}; + +const struct gpio_group meteorlake_pch_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(meteorlake_pch_group_b_names) / 7, + .func_count = 7, + .pad_names = meteorlake_pch_group_b_names, +}; + + +const char *const meteorlake_pch_group_c_names[] = { + "GPP_C0", "SMBCLK", + "GPP_C1", "SMBDATA", + "GPP_C2", "SMBALERT#", + "GPP_C3", "SML0CLK", + "GPP_C4", "SML0DATA", + "GPP_C5", "SML0ALERT#", + "GPP_C6", "SML1CLK", + "GPP_C7", "SML1DATA", +}; + +const struct gpio_group meteorlake_pch_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(meteorlake_pch_group_c_names) / 2, + .func_count = 2, + .pad_names = meteorlake_pch_group_c_names, +}; + + +const char *const meteorlake_pch_group_d_names[] = { + "GPP_D0", "ISH_GP0", "BK0", "n/a", "n/a", "n/a", "SBK0", + "GPP_D1", "ISH_GP1", "BK1", "n/a", "n/a", "n/a", "SBK1", + "GPP_D2", "ISH_GP2", "BK2", "n/a", "n/a", "n/a", "SBK2", + "GPP_D3", "ISH_GP3", "BK3", "n/a", "n/a", "n/a", "SBK3", + "GPP_D4", "IMGCLKOUT0", "BK4", "n/a", "n/a", "n/a", "SBK4", + "GPP_D5", "SRCCLKREQ0#", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D6", "SRCCLKREQ1#", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D7", "SRCCLKREQ2#", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D8", "SRCCLKREQ3#", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D9", "ISH_SPI_CS#", "DDP3_CTRLCLK", "n/a", "TBT_LSX2_TXD", "n/a", "BSSB_LS2_RX", + "GPP_D10", "ISH_SPI_CLK", "DDP3_CTRLDATA", "n/a", "TBT_LSX2_RXD", "n/a", "BSSB_LS2_TX", + "GPP_D11", "ISH_SPI_MISO", "DDP4_CTRLCLK", "n/a", "TBT_LSX3_TXD", "n/a", "BSSB_LS3_RX", + "GPP_D12", "ISH_SPI_MOSI", "DDP4_CTRLDATA", "n/a", "TBT_LSX3_RXD", "n/a", "BSSB_LS3_TX", + "GPP_D13", "ISH_UART0_RXD", "n/a", "I2C6_SDA", "n/a", "n/a", "n/a", + "GPP_D14", "ISH_UART0_TXD", "n/a", "I2C6_SCL", "n/a", "n/a", "n/a", + "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a", "I2C7B_SDA", "n/a", "n/a", + "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", "I2C7B_SCL", "n/a", "n/a", + "GPP_D17", "UART1_RXD", "ISH_UART1_RXD", "n/a", "n/a", "n/a", "n/a", + "GPP_D18", "UART1_TXD", "ISH_UART1_TXD", "n/a", "n/a", "n/a", "n/a", + "GPP_D19", "I2S_MCLK1_OUT", "n/a", "n/a", "n/a", "n/a", "n/a", +}; + +const struct gpio_group meteorlake_pch_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(meteorlake_pch_group_d_names) / 7, + .func_count = 7, + .pad_names = meteorlake_pch_group_d_names, +}; + + +const char *const meteorlake_pch_group_e_names[] = { + "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", "n/a", "n/a", "n/a", + + "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + + "GPP_E1", "n/a", "THC0_SPI1_IO2", "n/a", "n/a", "n/a", "n/a", + "GPP_E2", "n/a", "THC0_SPI1_IO3", "n/a", "n/a", "n/a", "n/a", + "GPP_E3", "PROC_GP0", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_E4", "DEVSLP0", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_E5", "DEVSLP1", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_E6", "n/a", "THC0_SPI1_RST#", "n/a", "n/a", "n/a", "n/a", + "GPP_E7", "PROC_GP1", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_E8", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_E9", "USB_OC0#", "ISH_GP4", "n/a", "n/a", "n/a", "n/a", + "GPP_E10", "n/a", "THC0_SPI1_CS#", "n/a", "n/a", "n/a", "n/a", + "GPP_E11", "n/a", "THC0_SPI1_CLK", "n/a", "n/a", "n/a", "n/a", + "GPP_E12", "n/a", "THC0_SPI1_IO1", "n/a", "n/a", "n/a", "I2C0A_SDA", + "GPP_E13", "n/a", "THC0_SPI1_IO0", "n/a", "n/a", "n/a", "I2C0A_SCL", + "GPP_E14", "DDSP_HPDA", "DISP_MISC_A", "n/a", "n/a", "n/a", "n/a", + "GPP_E15", "n/a", "Reserved", "n/a", "n/a", "n/a", "n/a", + "GPP_E16", "n/a", "Reserved", "n/a", "n/a", "n/a", "n/a", + "GPP_E17", "n/a", "THC0_SPI1_INT#", "n/a", "n/a", "n/a", "n/a", + "GPP_E18", "DDP1_CTRLCLK", "n/a", "n/a", "TBT_LSX0_TXD", "n/a", "BSSB_LS0_RX", + "GPP_E19", "DDP1_CTRLDATA", "n/a", "n/a", "TBT_LSX0_RXD", "n/a", "BSSB_LS0_TX", + "GPP_E20", "DDP2_CTRLCLK", "n/a", "n/a", "TBT_LSX1_TXD", "n/a", "BSSB_LS1_RX", + "GPP_E21", "DDP2_CTRLDATA", "n/a", "n/a", "TBT_LSX1_RXD", "n/a", "BSSB_LS1_TX", + "GPP_E22", "DDPA_CTRLCLK", "DNX_FORCE_RELOAD", "n/a", "n/a", "n/a", "n/a", + "GPP_E23", "DDPA_CTRLDATA", "n/a", "n/a", "n/a", "n/a", "n/a", +}; + +const struct gpio_group meteorlake_pch_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(meteorlake_pch_group_e_names) / 7, + .func_count = 7, + .pad_names = meteorlake_pch_group_e_names, +}; + + +const char *const meteorlake_pch_group_f_names[] = { + "GPP_F0", "CNV_BRI_DT", "UART2_RTS#", "n/a", "n/a", "n/a", "n/a", + "GPP_F1", "CNV_BRI_RSP", "UART2_RXD", "n/a", "n/a", "n/a", "n/a", + "GPP_F2", "CNV_RGI_DT", "UART2_TXD", "n/a", "n/a", "n/a", "n/a", + "GPP_F3", "CNV_RGI_RSP", "UART2_CTS#", "n/a", "n/a", "n/a", "n/a", + "GPP_F4", "CNV_RF_RESET#", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_F5", "n/a", "MODEM_CLKREQ", "CRF_XTAL_CLKREQ", "n/a", "n/a", "n/a", + "GPP_F6", "CNV_PA_BLANKING", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_F7", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_F9", "BOOTMPC", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_F10", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_F11", "n/a", "n/a", "THC1_SPI2_CLK", "GSPI1_CLK", "n/a", "n/a", + "GPP_F12", "GSXDOUT", "n/a", "THC1_SPI2_IO0", "GSPI1_MOSI", "n/a", "I2C1A_SCL", + "GPP_F13", "GSXSLOAD", "n/a", "THC1_SPI2_IO1", "GSPI1_MISO", "n/a", "I2C1A_SDA", + "GPP_F14", "GSXDIN", "n/a", "THC1_SPI2_IO2", "n/a", "n/a", "n/a", + "GPP_F15", "GSXSRESET#", "n/a", "THC1_SPI2_IO3", "n/a", "n/a", "n/a", + "GPP_F16", "GSXCLK", "n/a", "THC1_SPI2_CS#", "GSPI_CS0#", "n/a", "n/a", + "GPP_F17", "n/a", "n/a", "THC1_SPI2_RST#", "n/a", "n/a", "n/a", + "GPP_F18", "n/a", "n/a", "THC1_SPI2_INT#", "n/a", "n/a", "n/a", + "GPP_F19", "SRCCLKREQ6#", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_F20", "Reserved", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_F21", "Reserved", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_F22", "VNN_CTRL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_F23", "V1P05_CTRL", "n/a", "n/a", "n/a", "n/a", "n/a" +}; + +const struct gpio_group meteorlake_pch_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(meteorlake_pch_group_f_names) / 7, + .func_count = 7, + .pad_names = meteorlake_pch_group_f_names, +}; + + +const char *const meteorlake_pch_group_h_names[] = { + "GPP_H0", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_H1", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_H2", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_H3", "SX_EXIT_HOLDOFF#", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_H4", "I2C0_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_H5", "I2C0_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_H6", "I2C1_SDA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_H7", "I2C1_SCL", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_H8", "I2C4_SDA", "CNV_MFUART2_RXD", "n/a", "n/a", "n/a", "n/a", + "GPP_H9", "I2C4_SCL", "CNV_MFUART2_TXD", "n/a", "n/a", "n/a", "n/a", + "GPP_H10", "n/a", "UART0_RXD", "M2_SKT2_CFG0", "n/a", "n/a", "n/a", + "GPP_H11", "n/a", "UART0_TXD", "M2_SKT2_CFG1", "n/a", "n/a", "n/a", + "GPP_H12", "I2C7_SDA", "UART0_RTS#", "M2_SKT2_CFG2", "ISH_GP6B", "n/a", "DEVSLP0B", + "GPP_H13", "I2C7_SCL", "UART0_CTS#", "M2_SKT2_CFG3", "ISH_GP7B", "n/a", "DEVSLP1B", + + "n/a","n/a","n/a","n/a","n/a","n/a","n/a", + + "GPP_H15", "DDPB_CTRLCLK", "n/a", "PCIE_LINK_DOWN", "n/a", "n/a", "n/a", + + "n/a","n/a","n/a","n/a","n/a","n/a","n/a", + + "GPP_H17", "DDPB_CTRLDATA", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_H18", "PROC_C10_GATE#", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_H19", "SRCCLKREQ4#", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_H20", "IMGCLKOUT1", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_H21", "IMGCLKOUT2", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_H22", "IMGCLKOUT3", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_H23", "n/a", "SRCCLKREQ5#", "n/a", "n/a", "n/a", "n/a", +}; + +const struct gpio_group meteorlake_pch_group_h = { + .display = "------- GPIO Group GPP_H -------", + .pad_count = ARRAY_SIZE(meteorlake_pch_group_h_names) / 7, + .func_count = 7, + .pad_names = meteorlake_pch_group_h_names, +}; + + +const char *const meteorlake_pch_group_r_names[] = { + "GPP_R0", "HDA_BCLK", "I2S0_SCLK", "DMIC_CLK_B0", "HDAPROC_BCLK", + "GPP_R1", "HDA_SYNC", "I2S0_SFRM", "DMIC_CLK_B1", "n/a", + "GPP_R2", "HDA_SDO", "I2S0_TXD", "n/a", "HDAPROC_SDO", + "GPP_R3", "HDA_SDI0", "I2S0_RXD", "n/a", "HDAPROC_SDI", + "GPP_R4", "HDA_RST#", "I2S2_SCLK", "DMIC_CLK_A0", "n/a", + "GPP_R5", "HDA_SDI1", "I2S2_SFRM", "DMIC_DATA0", "n/a", + "GPP_R6", "n/a", "I2S2_TXD", "DMIC_CLK_A1", "n/a", + "GPP_R7", "n/a", "I2S2_RXD", "DMIC_DATA1", "n/a", +}; + +const struct gpio_group meteorlake_pch_group_r = { + .display = "------- GPIO Group GPP_R -------", + .pad_count = ARRAY_SIZE(meteorlake_pch_group_r_names) / 5, + .func_count = 5, + .pad_names = meteorlake_pch_group_r_names, +}; + + +const char *const meteorlake_pch_group_s_names[] = { + "GPP_S0", "SNDW0_CLK", "n/a", "n/a", "I2S1_SCLK", + "GPP_S1", "SNDW0_DATA", "n/a", "n/a", "I2S1_SFRM", + "GPP_S2", "SNDW1_CLK", "DMIC_CKL_A0", "n/a", "I2S1_TXD", + "GPP_S3", "SNDW1_DATA", "DMIC_DATA0", "n/a", "I2S1_RXD", + "GPP_S4", "SNDW2_CLK", "DMIC_CLK_B0", "n/a", "n/a", + "GPP_S5", "SNDW2_DATA", "DMIC_CLK_B1", "n/a", "n/a", + "GPP_S6", "SNDW3_CLK", "DMIC_CLK_A1", "n/a", "n/a", + "GPP_S7", "SNDW3_DATA", "DMIC_DATA1", "n/a", "n/a", +} + +const struct gpio_group meteorlake_pch_group_s = { + .display = "------- GPIO Group GPP_S -------", + .pad_count = ARRAY_SIZE(meteorlake_pch_group_s_names) / 5, + .func_count = 5, + .pad_names = meteorlake_pch_group_s_names, +}; + + +const char *const meteorlake_pch_group_t_names[] = { + "GPP_T2", "n/a", "Reserved", + "GPP_T3", "n/a", "Reserved", +}; + +const struct gpio_group meteorlake_pch_group_t = { + .display = "------- GPIO Group GPP_T -------", + .pad_count = ARRAY_SIZE(meteorlake_pch_group_t_names) / 3, + .func_count = 3, + .pad_names = meteorlake_pch_group_t_names, +}; + + +const char *const meteorlake_pch_group_gpd_names[] = { + "GPD0", "BATLOW#", + "GPD1", "ACPRESENT", + "GPD2", "LAN_WAKE#", + "GPD3", "PWRBTN#", + "GPD4", "SLP_S3#", + "GPD5", "SLP_S4#", + "GPD6", "SLP_A#", + "GPD7", "n/a", + "GPD8", "SUSCLK", + "GPD9", "SLP_WLAN#", + "GPD10", "SLP_S5#", + "GPD11", "LANPHYPC", +} + +const struct gpio_group meteorlake_pch_group_gpd = { + .display = "------- GPIO Group GPP_GPD -------", + .pad_count = ARRAY_SIZE(meteorlake_pch_group_gpd_names) / 2, + .func_count = 2, + .pad_names = meteorlake_pch_group_gpd_names, +}; + + +/* + COMMUNITIES + + community 0: 8h - 944h + GPP_V + GPP_C + + community 1: 8h - 8f4h + GPP_A + GPP_E + + community 2: ???? + + community 3: 8h - 914h + GPP_H + GPP_F + + gpio expander capability + + community 4: 8h - 674h + GPP_S + + community 5: 8h - 904h + GPP_B + GPP_D + + blink, serial blink, and PWM control +*/ + +const struct gpio_group *const meteorlake_pch_community_0_groups[] = { + &meteorlake_pch_group_v, + &meteorlake_pch_group_c, +}; + +const struct gpio_community meteorlake_pch_community_0 = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0x6e, + .group_count = ARRAY_SIZE(meteorlake_pch_community_0_groups), + .groups = meteorlake_pch_community_0_groups, +}; + + +const struct gpio_group *const meteorlake_pch_community_1_groups[] = { + &meteorlake_pch_group_a, + &meteorlake_pch_group_e, +}; + +const struct gpio_community meteorlake_pch_community_1 = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0x6e, + .group_count = ARRAY_SIZE(meteorlake_pch_community_1_groups), + .groups = meteorlake_pch_community_1_groups, +}; + + +const struct gpio_group *const meteorlake_pch_community_3_groups[] = { + &meteorlake_pch_group_h, + &meteorlake_pch_group_f, + // and gpio expander? +}; + +const struct gpio_community meteorlake_pch_community_3 = { + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0x6e, + .group_count = ARRAY_SIZE(meteorlake_pch_community_3_groups), + .groups = meteorlake_pch_community_3_groups, +}; + + +const struct gpio_group *const meteorlake_pch_community_4_groups[] = { + &meteorlake_pch_group_s, +}; + +const struct gpio_community meteorlake_pch_community_4 = { + .name = "------- GPIO Community 4 -------", + .pcr_port_id = 0x6e, + .group_count = ARRAY_SIZE(meteorlake_pch_community_4_groups), + .groups = meteorlake_pch_community_4_groups, +}; + + +const struct gpio_group *const meteorlake_pch_community_5_groups[] = { + &meteorlake_pch_group_b, + &meteorlake_pch_group_d, + // and blink, serial blink and pwm? +}; + +const struct gpio_community meteorlake_pch_community_5 = { + .name = "------- GPIO Community 5 -------", + .pcr_port_id = 0x6e, + .group_count = ARRAY_SIZE(meteorlake_pch_community_5_groups), + .groups = meteorlake_pch_community_5_groups, +}; + +const struct gpio_community *const meteorlake_pch_communities[] = { + &meteorlake_pch_community_0, + &meteorlake_pch_community_1, + &meteorlake_pch_community_3, + &meteorlake_pch_community_4, + &meteorlake_pch_community_5, +}; + + +/* +"n/a", "Deglitch Legend", "n/a", "n/a", "n/a", "n/a", "n/a", +"n/a", "n/a"yes(1) - o/p Hi-Z", "n/a", "n/a", "n/a", "n/a", "n/a", +"n/a", "n/a"yes(2) - o/p Hi-Z", "n/a", "n/a", "n/a", "n/a", "n/a", +"n/a", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", +" UART", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", +*/ -- To view, visit https://review.coreboot.org/c/coreboot/+/81843?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7473119fa97c57cd2a1303f08f964abd0ca96270 Gerrit-Change-Number: 81843 Gerrit-PatchSet: 1 Gerrit-Owner: Filip Lewiński Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: soc/amd/picasso: Mark eMMC as non-removable for Windows 10/11 install
by Matt DeVillier (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: CoolStar, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81858?usp=email ) Change subject: soc/amd/picasso: Mark eMMC as non-removable for Windows 10/11 install ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81858?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If0e14106521f99cb97d1bf421f4d82d1234c2f15 Gerrit-Change-Number: 81858 Gerrit-PatchSet: 2 Gerrit-Owner: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 12 Apr 2024 14:07:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: configs: Add Hifive Unleashed config with OpenSBI
by Maximilian Brune (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Martin L Roth. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81859?usp=email ) Change subject: configs: Add Hifive Unleashed config with OpenSBI ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: I noticed that jenkins did not use the config that I added. Is that normal or am I missing something? -- To view, visit https://review.coreboot.org/c/coreboot/+/81859?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2101b194bf0d74f4f444fba507e0294bddc746d3 Gerrit-Change-Number: 81859 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Fri, 12 Apr 2024 14:06:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2024