coreboot-gerrit April 2024

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[XS] Change in coreboot[main]: configs: Add Hifive Unleashed config with OpenSBI
by Maximilian Brune (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Martin L Roth. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81859?usp=email ) Change subject: configs: Add Hifive Unleashed config with OpenSBI ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: I noticed that jenkins did not use the config that I added. Is that normal or am I missing something? -- To view, visit https://review.coreboot.org/c/coreboot/+/81859?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2101b194bf0d74f4f444fba507e0294bddc746d3 Gerrit-Change-Number: 81859 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Fri, 12 Apr 2024 14:06:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in em100[main]: em100: add missing long options for --upload and --voltage
by Maximilian Brune (Code Review) 12 Apr '24

12 Apr '24

Maximilian Brune has submitted this change. ( https://review.coreboot.org/c/em100/+/81078?usp=email ) Change subject: em100: add missing long options for --upload and --voltage ...................................................................... em100: add missing long options for --upload and --voltage Our usage says that those long options exists. Unfortunately, we do not parse them which may lead to confused user. Change-Id: I4a4e8d5ffa38e8ffef47f9966262eca874520f2c Signed-off-by: Corvin Köhne <c.koehne(a)beckhoff.com> Reviewed-on: https://review.coreboot.org/c/em100/+/81078 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M em100.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: Martin L Roth: Looks good to me, approved build bot (Jenkins): Verified diff --git a/em100.c b/em100.c index 68407c3..fe02d8d 100644 --- a/em100.c +++ b/em100.c @@ -785,6 +785,7 @@ {"download", 1, 0, 'd'}, {"start-address", 1, 0, 'a'}, {"address-mode", 1, 0, 'm'}, + {"upload", 1, 0, 'u'}, {"start", 0, 0, 'r'}, {"stop", 0, 0, 's'}, {"verify", 0, 0, 'v'}, @@ -794,6 +795,7 @@ {"trace", 0, 0, 't'}, {"offset", 1, 0, 'O'}, {"set-serialno", 1, 0, 'S'}, + {"set-voltage", 1, 0, 'V'}, {"firmware-update", 1, 0, 'F'}, {"firmware-dump", 1, 0, 'f'}, {"firmware-write", 1, 0, 'g'}, -- To view, visit https://review.coreboot.org/c/em100/+/81078?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: main Gerrit-Change-Id: I4a4e8d5ffa38e8ffef47f9966262eca874520f2c Gerrit-Change-Number: 81078 Gerrit-PatchSet: 2 Gerrit-Owner: c.koehne(a)beckhoff.com Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: lynxpoint/broadwell: Correct PCH-LP PCIe ASPM check
by Lean Sheng Tan (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Angel Pons, Patrick Rudolph. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57500?usp=email ) Change subject: lynxpoint/broadwell: Correct PCH-LP PCIe ASPM check ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57500?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie4bd7cbbfc151762f29eab1326567f987b25ab19 Gerrit-Change-Number: 57500 Gerrit-PatchSet: 7 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <rudolphpatrick05(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <rudolphpatrick05(a)gmail.com> Gerrit-Comment-Date: Fri, 12 Apr 2024 13:42:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/asrock/z97_extreme6: Add new mainboard
by Angel Pons (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Martin L Roth. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68188?usp=email ) Change subject: mb/asrock/z97_extreme6: Add new mainboard ...................................................................... Patch Set 6: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68188/comment/55624242_35d6a898 : PS4, Line 38: - Intel GbE (I218-V PHY and PCH MAC) > Test the Realtek GbE too, make sure the MAC address is correct. Done https://review.coreboot.org/c/coreboot/+/68188/comment/6d488ed3_f583dec9 : PS4, Line 43: - Broadwell CPUs (most likely need more magic to work) > They do not work with Broadwell MRC. […] Done https://review.coreboot.org/c/coreboot/+/68188/comment/6ca81c8d_ebde22c6 : PS4, Line 44: - DVI-I, DisplayPort > DVI-I might need a bit of Kconfig magic so that libgfxinit knows where to get the EDID for the analo […] Ack https://review.coreboot.org/c/coreboot/+/68188/comment/c9c93b56_8bbf7615 : PS4, Line 57: - ME: unless disabled, the system powers off after a minute or so > Need to re-test, it's likely that we were using a bad ME firmware with the EM100Pro. Done Commit Message: https://review.coreboot.org/c/coreboot/+/68188/comment/7e3b6b91_2486c6b3 : PS5, Line 7: [WIP] > Need to do some more testing first, especially regarding the ME issue. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68188?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If1d22547725e59f435de36b973e1bf4f334269a9 Gerrit-Change-Number: 68188 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Fri, 12 Apr 2024 13:28:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/asrock/z97_extreme6: Add new mainboard
by Angel Pons (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Martin L Roth. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68188?usp=email to look at the new patch set (#6). Change subject: mb/asrock/z97_extreme6: Add new mainboard ...................................................................... mb/asrock/z97_extreme6: Add new mainboard This is an ATX mainboard with a LGA1150 socket and four DDR3 DIMM slots. Porting was done using autoport and then doing a bunch of manual edits. This board has two socketed DIP-8 SPI flash chips and a physical switch to choose which one should the system boot from. As long as one of them contains a bootable firmware image, it is possible to reflash the other chip using the internal programmer by flipping the switch after booting to OS. Even if one somehow manages to flash unbootable firmware to both chips, they are socketed: one can carefully remove them from the socket and reflash them externally, which is a relatively safe procedure (when compared to in-circuit flashing, especially if the board isn't designed to safely be flashed in-circuit). In short, the board is hard to brick. Haswell MRC.bin cannot be used because it lacks support for the Z97 PCH found on this mainboard. Broadwell MRC.bin only works with Haswell CPUs so far, as raminit fails on Broadwell CPUs for an unknown reason. Maybe it's something about RcvEn, but it's unlikely it can easily be fixed. Working: - All four DIMM slots - Broadwell MRC.bin for raminit purposes - Serial port to emit spam - POST code display - S3 suspend/resume - At least one rear USB port - Integrated graphics (libgfxinit) - HDMI - VBT - Intel GbE (I218-V PHY and PCH MAC) - Realtek RTL8111E GbE - At least one SATA port - SeaBIOS (current version) to boot Arch Linux - NCT6791D Super I/O software-based fan control tested using `sensors` and `pwmconfig`, all 6 fan tachometers and 5 PWM outputs work fine. Untested for now (i.e. will eventually test): - DVI-I, DisplayPort - EHCI debug - The other USB ports (rear, on-board, front) - The other audio jacks (all of them) - PCIe and M.2 ports (PEG mux spam likely needs more magic) - Flashing with flashrom - Non-Linux OSes - PS/2 combo port (can only test with a keyboard) Untestable (i.e. cannot test due to unavailable hardware): - Thunderbolt AIC (Add-In Card) support Not working: - Broadwell CPUs, they require more magic to work. - Super I/O automatic fan control: not yet implemented in coreboot. To control fans, use software fan control methods in the meantime. - Acer B247Y board driving a FHD panel of a Samsung S24E650 monitor, connected to the board's HDMI output says "Unsupported resolution" after libgfxinit configured the iGPU outputs in linear framebuffer mode. HDMI output works fine after Linux's i915 driver takes over. Not sure if it's specific to the monitor: the HDMI cable is beaten up, and it is hard to replace (need to relocate the logic board so that the ports are accessible). Change-Id: If1d22547725e59f435de36b973e1bf4f334269a9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/asrock/z97_extreme6/Kconfig A src/mainboard/asrock/z97_extreme6/Kconfig.name A src/mainboard/asrock/z97_extreme6/Makefile.mk A src/mainboard/asrock/z97_extreme6/acpi/ec.asl A src/mainboard/asrock/z97_extreme6/acpi/platform.asl A src/mainboard/asrock/z97_extreme6/acpi/superio.asl A src/mainboard/asrock/z97_extreme6/board_info.txt A src/mainboard/asrock/z97_extreme6/bootblock.c A src/mainboard/asrock/z97_extreme6/data.vbt A src/mainboard/asrock/z97_extreme6/devicetree.cb A src/mainboard/asrock/z97_extreme6/dsdt.asl A src/mainboard/asrock/z97_extreme6/gma-mainboard.ads A src/mainboard/asrock/z97_extreme6/gpio.c A src/mainboard/asrock/z97_extreme6/hda_verb.c A src/mainboard/asrock/z97_extreme6/romstage.c 15 files changed, 537 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/68188/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/68188?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If1d22547725e59f435de36b973e1bf4f334269a9 Gerrit-Change-Number: 68188 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Compress FSP-S
by Lean Sheng Tan (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Paul Menzel, Ray Ni, Shuo Liu, Sumeet R Pawnikar, Tim Chu. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81634?usp=email ) Change subject: soc/intel/xeon_sp: Compress FSP-S ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81634/comment/91d39720_f78c6c97 : PS1, Line 12: Test: Still boots on ibm/sbp1. > Boot time differences when using a debug FSP-S would be rather meaningless (most of the time would b […] any further concern? if no i will mark as close and get it merged. -- To view, visit https://review.coreboot.org/c/coreboot/+/81634?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6248e7cabbce45f6c2fedfab34f328309f87e868 Gerrit-Change-Number: 81634 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Ray Ni <ray.ni(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ray Ni <ray.ni(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 12 Apr 2024 13:12:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: configs: Add Hifive Unleashed config with OpenSBI
by Maximilian Brune (Code Review) 12 Apr '24

12 Apr '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81859?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: configs: Add Hifive Unleashed config with OpenSBI ...................................................................... configs: Add Hifive Unleashed config with OpenSBI OpenSBI often breaks if you update it. This should ensure that jenkins keeps an eye on it. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I2101b194bf0d74f4f444fba507e0294bddc746d3 --- A configs/config.sifive_hifive-unleashed.opensbi 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/81859/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81859?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2101b194bf0d74f4f444fba507e0294bddc746d3 Gerrit-Change-Number: 81859 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: security/tpm: support compiling in multiple TPM drivers
by Sergii Dmytruk (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Julius Werner, Jérémy Compostella, Krystian Hebel, Matt DeVillier, Michał Żygowski, Raul Rangel. Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69162?usp=email ) Change subject: security/tpm: support compiling in multiple TPM drivers ...................................................................... Patch Set 40: (1 comment) File src/drivers/crb/tis.h: PS38: > Well, in that case you need to fix that anyway. […] Sure, you're right, renamed symbols of CRB driver in CB:81860 and dropped `tis.h` here. -- To view, visit https://review.coreboot.org/c/coreboot/+/69162?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44c5a1d825afe414c2f5c2c90f4cfe41ba9bef5f Gerrit-Change-Number: 69162 Gerrit-PatchSet: 40 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 12 Apr 2024 12:54:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: drivers/crb: use crb_tpm_ prefix instead of tpm2_
by Sergii Dmytruk (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Cliff Huang, Lance Zhao, Tim Wawrzynczak. Sergii Dmytruk has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81860?usp=email ) Change subject: drivers/crb: use crb_tpm_ prefix instead of tpm2_ ...................................................................... drivers/crb: use crb_tpm_ prefix instead of tpm2_ This prevents name clashes with drivers/spi/tpm and allows both to be potentially compiled in at the same time. Change-Id: I0aa2686103546e0696ab8dcf77e2b99bf9734915 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/acpi/acpi.c M src/drivers/crb/tis.c M src/drivers/crb/tpm.c M src/drivers/crb/tpm.h 4 files changed, 27 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/81860/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index c33d195..39eadc3 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -273,7 +273,7 @@ /* Hard to detect for coreboot. Just set it to 0 */ tpm2->platform_class = 0; - if (CONFIG(CRB_TPM) && tpm2_has_crb_active()) { + if (CONFIG(CRB_TPM) && crb_tpm_is_active()) { /* Must be set to 7 for CRB Support */ tpm2->control_area = CONFIG_CRB_TPM_BASE_ADDRESS + 0x40; tpm2->start_method = 7; diff --git a/src/drivers/crb/tis.c b/src/drivers/crb/tis.c index 04e255a..1b398f7 100644 --- a/src/drivers/crb/tis.c +++ b/src/drivers/crb/tis.c @@ -23,7 +23,7 @@ {0xa13a, 0x8086, "Intel iTPM"} }; -static const char *tis_get_dev_name(struct tpm2_info *info) +static const char *tis_get_dev_name(struct crb_tpm_info *info) { int i; @@ -36,7 +36,7 @@ static tpm_result_t crb_tpm_sendrecv(const uint8_t *sendbuf, size_t sbuf_size, uint8_t *recvbuf, size_t *rbuf_len) { - int len = tpm2_process_command(sendbuf, sbuf_size, recvbuf, *rbuf_len); + int len = crb_tpm_process_command(sendbuf, sbuf_size, recvbuf, *rbuf_len); if (len == 0) return TPM_CB_FAIL; @@ -48,17 +48,17 @@ tis_sendrecv_fn tis_probe(enum tpm_family *family) { - struct tpm2_info info; + struct crb_tpm_info info; /* Wake TPM up (if necessary) */ - if (tpm2_init()) + if (crb_tpm_init()) return NULL; /* CRB interface exists only in TPM2 */ if (family != NULL) *family = TPM_2; - tpm2_get_info(&info); + crb_tpm_get_info(&info); printk(BIOS_INFO, "Initialized TPM device %s revision %d\n", tis_get_dev_name(&info), info.revision); @@ -137,7 +137,7 @@ static int smbios_write_type43_tpm(struct device *dev, int *handle, unsigned long *current) { - struct tpm2_info info; + struct crb_tpm_info info; uint32_t tpm_manuf, tpm_family; uint32_t fw_ver1, fw_ver2; uint8_t major_spec_ver, minor_spec_ver; @@ -145,7 +145,7 @@ if (tlcl_get_family() == TPM_1) return 0; - tpm2_get_info(&info); + crb_tpm_get_info(&info); /* If any of these have invalid values, assume TPM not present or disabled */ if (info.vendor_id == 0 || info.vendor_id == 0xFFFF || diff --git a/src/drivers/crb/tpm.c b/src/drivers/crb/tpm.c index b568dcc..ea5e701 100644 --- a/src/drivers/crb/tpm.c +++ b/src/drivers/crb/tpm.c @@ -54,7 +54,7 @@ * register before each command submission otherwise the control area * is all zeroed. This has been observed on Alder Lake S CPU and may be * applicable to other new microarchitectures. Update the local control - * area data to make tpm2_process_command not fail on buffer checks. + * area data to make crb_tpm_process_command() not fail on buffer checks. * PTT command/response buffer is fixed to be at offset 0x80 and spans * up to the end of 4KB region for the current locality. */ @@ -181,14 +181,14 @@ } /* - * tpm2_init + * crb_tpm_init * * Even though the TPM does not need an initialization we check * if the TPM responds and is in IDLE mode, which should be the * normal bring up mode. * */ -tpm_result_t tpm2_init(void) +tpm_result_t crb_tpm_init(void) { tpm_result_t rc = crb_probe(); if (rc) { @@ -227,10 +227,10 @@ } /* - * tpm2_process_command + * crb_tpm_process_command */ -size_t tpm2_process_command(const void *tpm2_command, size_t command_size, void *tpm2_response, - size_t max_response) +size_t crb_tpm_process_command(const void *tpm2_command, size_t command_size, + void *tpm2_response, size_t max_response) { tpm_result_t rc; @@ -312,24 +312,24 @@ * Returns information about the TPM * */ -void tpm2_get_info(struct tpm2_info *tpm2_info) +void crb_tpm_get_info(struct crb_tpm_info *crb_tpm_info) { uint64_t interfaceReg = read64(CRB_REG(cur_loc, CRB_REG_INTF_ID)); - tpm2_info->vendor_id = (interfaceReg >> 48) & 0xFFFF; - tpm2_info->device_id = (interfaceReg >> 32) & 0xFFFF; - tpm2_info->revision = (interfaceReg >> 24) & 0xFF; + crb_tpm_info->vendor_id = (interfaceReg >> 48) & 0xFFFF; + crb_tpm_info->device_id = (interfaceReg >> 32) & 0xFFFF; + crb_tpm_info->revision = (interfaceReg >> 24) & 0xFF; } /* - * tpm2_has_crb_active + * crb_tpm_is_active * * Checks that CRB interface is available and active. * * The body was derived from crb_probe() which unlike this function can also * write to registers. */ -bool tpm2_has_crb_active(void) +bool crb_tpm_is_active(void) { uint64_t tpmStatus = read64(CRB_REG(0, CRB_REG_INTF_ID)); printk(BIOS_SPEW, "Interface ID Reg. %llx\n", tpmStatus); diff --git a/src/drivers/crb/tpm.h b/src/drivers/crb/tpm.h index 60020c3..fbe3901 100644 --- a/src/drivers/crb/tpm.h +++ b/src/drivers/crb/tpm.h @@ -53,15 +53,15 @@ /* START Register related */ #define CRB_REG_START_START 0x01 -/* TPM Info Struct */ -struct tpm2_info { +/* CRB TPM Info Struct */ +struct crb_tpm_info { uint16_t vendor_id; uint16_t device_id; uint16_t revision; }; -tpm_result_t tpm2_init(void); -void tpm2_get_info(struct tpm2_info *tpm2_info); -size_t tpm2_process_command(const void *tpm2_command, size_t command_size, - void *tpm2_response, size_t max_response); -bool tpm2_has_crb_active(void); +tpm_result_t crb_tpm_init(void); +void crb_tpm_get_info(struct crb_tpm_info *crb_tpm_info); +size_t crb_tpm_process_command(const void *tpm2_command, size_t command_size, + void *tpm2_response, size_t max_response); +bool crb_tpm_is_active(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/81860?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0aa2686103546e0696ab8dcf77e2b99bf9734915 Gerrit-Change-Number: 81860 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: security/tpm: support compiling in multiple TPM drivers
by Sergii Dmytruk (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Krystian Hebel, Matt DeVillier, Michał Żygowski, Raul Rangel, Sergii Dmytruk. Hello Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Julius Werner, Jérémy Compostella, Krystian Hebel, Matt DeVillier, Michał Żygowski, Raul Rangel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69162?usp=email to look at the new patch set (#40). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: security/tpm: support compiling in multiple TPM drivers ...................................................................... security/tpm: support compiling in multiple TPM drivers Starting from here CONFIG_TPM1 and CONFIG_TPM2 are no longer mutually exclusive. Change-Id: I44c5a1d825afe414c2f5c2c90f4cfe41ba9bef5f Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/drivers/crb/tis.c M src/drivers/crb/tpm.h M src/drivers/i2c/tpm/tis.c M src/drivers/i2c/tpm/tis_atmel.c M src/drivers/i2c/tpm/tpm.h M src/drivers/pc80/tpm/tis.c A src/drivers/pc80/tpm/tpm.h M src/drivers/spi/tpm/tis.c M src/drivers/spi/tpm/tpm.h M src/security/tpm/Kconfig M src/security/tpm/tis.h M src/security/tpm/tss/tss.c 12 files changed, 53 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/69162/40 -- To view, visit https://review.coreboot.org/c/coreboot/+/69162?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44c5a1d825afe414c2f5c2c90f4cfe41ba9bef5f Gerrit-Change-Number: 69162 Gerrit-PatchSet: 40 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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