coreboot-gerrit April 2024

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[XS] Change in coreboot[main]: payloads/edk2/Makefile: Drop duplicated build string option
by Matt DeVillier (Code Review) 12 Apr '24

12 Apr '24

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81894?usp=email ) Change subject: payloads/edk2/Makefile: Drop duplicated build string option ...................................................................... payloads/edk2/Makefile: Drop duplicated build string option The `PRIORITIZE_INTERNAL` option has been upstreamed, so remove the copy under the MrChromebox repo specific settings. TEST=build qemu w/edk2 payload, check build log that the 'PRIORITIZE_INTERNAL' option is only added once to the build string. Change-Id: I4c4c433184d93337c926e256e77054afc00a2566 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M payloads/external/edk2/Makefile 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/81894/1 diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile index 90d77e4..c4d56c8 100644 --- a/payloads/external/edk2/Makefile +++ b/payloads/external/edk2/Makefile @@ -79,10 +79,6 @@ ifneq ($(CONFIG_ECAM_MMCONF_LENGTH),) BUILD_STR += --pcd gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize=$(CONFIG_ECAM_MMCONF_LENGTH) endif -# PRIORITIZE_INTERNAL = FALSE -ifeq ($(CONFIG_EDK2_PRIORITIZE_INTERNAL),y) -BUILD_STR += -D PRIORITIZE_INTERNAL=TRUE -endif # PS2_KEYBOARD_ENABLE = FALSE ifeq ($(CONFIG_EDK2_PS2_SUPPORT),y) BUILD_STR += -D PS2_KEYBOARD_ENABLE=TRUE @@ -129,10 +125,6 @@ ifeq ($(CONFIG_EDK2_GOP_DRIVER), y) BUILD_STR += -D USE_PLATFORM_GOP=TRUE endif -# PRIORITIZE_INTERNAL = FALSE -ifeq ($(CONFIG_EDK2_PRIORITIZE_INTERNAL),y) -BUILD_STR += -D PRIORITIZE_INTERNAL=TRUE -endif # TPM_ENABLE = TRUE ifeq ($(CONFIG_EDK2_DISABLE_TPM),y) BUILD_STR += -D TPM_ENABLE=FALSE -- To view, visit https://review.coreboot.org/c/coreboot/+/81894?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4c4c433184d93337c926e256e77054afc00a2566 Gerrit-Change-Number: 81894 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: Wifi: Support 320Mhz Bandwidth Enablement per MCC
by Cliff Huang (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Poornima Tom. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81790?usp=email ) Change subject: Wifi: Support 320Mhz Bandwidth Enablement per MCC ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Can we add a enabling flag in chip.h so that we can enable it for discrete and disable for CNVi? -- To view, visit https://review.coreboot.org/c/coreboot/+/81790?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie76794825f1a0104d199c078aa4ffc714aa95b17 Gerrit-Change-Number: 81790 Gerrit-PatchSet: 2 Gerrit-Owner: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dinesh Sharma <dinesh.sharma(a)intel.corp-partner.google.com> Gerrit-Attention: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Comment-Date: Fri, 12 Apr 2024 21:07:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/zork: Enable eMMC driver for edk2 payload
by Matt DeVillier (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Jason Nien, Martin Roth. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81893?usp=email ) Change subject: mb/google/zork: Enable eMMC driver for edk2 payload ...................................................................... mb/google/zork: Enable eMMC driver for edk2 payload Several zork-based boards use eMMC for storage, so enable the edk2 eMMC driver when using the edk2 payload. TEST=build/boot google/zork (morphius, vilboz), verify internal boot media (both eMMC and NVMe) functional with edk2 payload. Change-Id: Ib7e98f309594554dbcf1ddd875d47c89bd9e0e44 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/zork/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/81893/1 diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index 21deea7..a6f5a3b 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -62,6 +62,7 @@ select EC_GOOGLE_CHROMEEC_I2C_TUNNEL select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG select EC_GOOGLE_CHROMEEC_SKUID + select EDK2_PCO_MMIO_EMMC if PAYLOAD_EDK2 select ELOG select ELOG_BOOT_COUNT select ELOG_GSMI -- To view, visit https://review.coreboot.org/c/coreboot/+/81893?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib7e98f309594554dbcf1ddd875d47c89bd9e0e44 Gerrit-Change-Number: 81893 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: payloads/edk2: Add Kconfig to enable AMD Picasso eMMC driver
by Matt DeVillier (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Benjamin Doron, Lean Sheng Tan, Martin L Roth, Sean Rhodes. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81892?usp=email ) Change subject: payloads/edk2: Add Kconfig to enable AMD Picasso eMMC driver ...................................................................... payloads/edk2: Add Kconfig to enable AMD Picasso eMMC driver Add a Kconfig to selectively enable the AMD Picasso eMMC driver recently added to MrChromebox's edk2 fork. When selected, will enable booting from AMD Picasso devices with eMMC storage. TEST=tested with rest of patch train Change-Id: I6536a6f243f6766b913e295afebcf5b965e4e969 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M payloads/external/Makefile.mk M payloads/external/edk2/Kconfig M payloads/external/edk2/Makefile 3 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/81892/1 diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk index 9b79f1a..7c92bcb 100644 --- a/payloads/external/Makefile.mk +++ b/payloads/external/Makefile.mk @@ -196,6 +196,7 @@ CONFIG_INTEL_GMA_VBT_FILE=$(CONFIG_INTEL_GMA_VBT_FILE) \ CONFIG_EDK2_DISABLE_TPM=$(CONFIG_EDK2_DISABLE_TPM) \ CONFIG_EDK2_UFS_ENABLE=$(CONFIG_EDK2_UFS_ENABLE) \ + CONFIG_EDK2_PCO_MMIO_EMMC=$(CONFIG_EDK2_PCO_MMIO_EMMC) \ GCC_CC_x86_32=$(GCC_CC_x86_32) \ GCC_CC_x86_64=$(GCC_CC_x86_64) \ GCC_CC_arm=$(GCC_CC_arm) \ diff --git a/payloads/external/edk2/Kconfig b/payloads/external/edk2/Kconfig index 9dd0c78..9d7e069 100644 --- a/payloads/external/edk2/Kconfig +++ b/payloads/external/edk2/Kconfig @@ -298,6 +298,14 @@ It is needed for boards with UFS storage, but can cause issues with other boards, so should only be enabled when needed. +config EDK2_PCO_MMIO_EMMC + bool "Enable MMIO eMMC driver for AMD Picasso boards in edk2" + default n + help + Select this option to enable the MMIO eMMC DXE driver in MrChromebox's fork of edk2. + It is needed for AMD Picasso boards with eMMC storage, but will conflict with the + PCI-based eMMC driver, so should only be enabled for AMD Picasso boards. + config EDK2_CUSTOM_BUILD_PARAMS string "edk2 additional custom build parameters" default "-D VARIABLE_SUPPORT=SMMSTORE" if EDK2_REPO_MRCHROMEBOX && SMMSTORE_V2 diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile index dd95942..90d77e4 100644 --- a/payloads/external/edk2/Makefile +++ b/payloads/external/edk2/Makefile @@ -141,6 +141,10 @@ ifeq ($(CONFIG_EDK2_UFS_ENABLE),y) BUILD_STR += -D UFS_ENABLE=TRUE endif +# USE_PCO_MMIO_EMMC = FALSE +ifeq ($(CONFIG_EDK2_PCO_MMIO_EMMC),y) +BUILD_STR += -D USE_PCO_MMIO_EMMC=TRUE +endif endif -- To view, visit https://review.coreboot.org/c/coreboot/+/81892?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6536a6f243f6766b913e295afebcf5b965e4e969 Gerrit-Change-Number: 81892 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/brya: Enable UFS driver for edk2 payload
by Matt DeVillier (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81871?usp=email ) Change subject: mb/google/brya: Enable UFS driver for edk2 payload ...................................................................... mb/google/brya: Enable UFS driver for edk2 payload Several brya-based boards use UFS for storage, so enable the edk2 UFS driver when using the edk2 payload. TEST=build/boot google/brya (banshee, craaskov), verify internal boot media functional with edk2 payload. Change-Id: I3dc018582e974bf73c7668f78da9b81eeb038c01 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/81871/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 7f6f7c7..c9bd832 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -22,6 +22,7 @@ select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_SKUID + select EDK2_UFS_ENABLE if PAYLOAD_EDK2 select ENABLE_TCSS_USB_DETECTION if !CHROMEOS select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI -- To view, visit https://review.coreboot.org/c/coreboot/+/81871?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dc018582e974bf73c7668f78da9b81eeb038c01 Gerrit-Change-Number: 81871 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: payloads/edk2: Add Kconfig to enable UFS support
by Matt DeVillier (Code Review) 12 Apr '24

12 Apr '24

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81870?usp=email ) Change subject: payloads/edk2: Add Kconfig to enable UFS support ...................................................................... payloads/edk2: Add Kconfig to enable UFS support Add a Kconfig to selectively enable the UFS DXE driver recently added to MrChromebox's edk2 fork. When selected, will enable booting from devices with UFS storage. TEST=tested with rest of patch train Change-Id: I0b54d21dc87abf6938c03948830f92ce5097ef7d Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M payloads/external/Makefile.mk M payloads/external/edk2/Kconfig M payloads/external/edk2/Makefile 3 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/81870/1 diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk index f1dc5cc..9b79f1a 100644 --- a/payloads/external/Makefile.mk +++ b/payloads/external/Makefile.mk @@ -195,6 +195,7 @@ CONFIG_EDK2_GOP_FILE=$(CONFIG_EDK2_GOP_FILE) \ CONFIG_INTEL_GMA_VBT_FILE=$(CONFIG_INTEL_GMA_VBT_FILE) \ CONFIG_EDK2_DISABLE_TPM=$(CONFIG_EDK2_DISABLE_TPM) \ + CONFIG_EDK2_UFS_ENABLE=$(CONFIG_EDK2_UFS_ENABLE) \ GCC_CC_x86_32=$(GCC_CC_x86_32) \ GCC_CC_x86_64=$(GCC_CC_x86_64) \ GCC_CC_arm=$(GCC_CC_arm) \ diff --git a/payloads/external/edk2/Kconfig b/payloads/external/edk2/Kconfig index 865ae67..9dd0c78 100644 --- a/payloads/external/edk2/Kconfig +++ b/payloads/external/edk2/Kconfig @@ -290,6 +290,14 @@ Select this option to disable TPM support in edk2. This is necessary to avoid boot hangs on some boards with a CR50 TPM, particularly those with an AMD Zen SoC. +config EDK2_UFS_ENABLE + bool "Enable UFS DXE driver in edk2" + default n + help + Select this option to enable the UFS DXE driver in MrChromebox's fork of edk2. + It is needed for boards with UFS storage, but can cause issues with other boards, + so should only be enabled when needed. + config EDK2_CUSTOM_BUILD_PARAMS string "edk2 additional custom build parameters" default "-D VARIABLE_SUPPORT=SMMSTORE" if EDK2_REPO_MRCHROMEBOX && SMMSTORE_V2 diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile index b03f1d5..dd95942 100644 --- a/payloads/external/edk2/Makefile +++ b/payloads/external/edk2/Makefile @@ -137,6 +137,10 @@ ifeq ($(CONFIG_EDK2_DISABLE_TPM),y) BUILD_STR += -D TPM_ENABLE=FALSE endif +# UFS_ENABLE = FALSE +ifeq ($(CONFIG_EDK2_UFS_ENABLE),y) +BUILD_STR += -D UFS_ENABLE=TRUE +endif endif -- To view, visit https://review.coreboot.org/c/coreboot/+/81870?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0b54d21dc87abf6938c03948830f92ce5097ef7d Gerrit-Change-Number: 81870 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: haswell NRI: Add write leveling
by Angel Pons (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Arthur Heymans, Nico Huber. Hello Arthur Heymans, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64197?usp=email to look at the new patch set (#8). Change subject: haswell NRI: Add write leveling ...................................................................... haswell NRI: Add write leveling Implement JEDEC write leveling, which is done in two steps. The first step uses the JEDEC procedure to do "fine" write leveling, i.e. align the DQS phase to the clock signal. The second step performs a regular read-write test to correct "coarse" cycle errors. Change-Id: I27678523fe22c38173a688e2a4751c259a20f009 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/native_raminit/Makefile.mk M src/northbridge/intel/haswell/native_raminit/raminit_main.c M src/northbridge/intel/haswell/native_raminit/raminit_native.h A src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c M src/northbridge/intel/haswell/registers/mchbar.h 5 files changed, 595 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/64197/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/64197?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I27678523fe22c38173a688e2a4751c259a20f009 Gerrit-Change-Number: 64197 Gerrit-PatchSet: 8 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: haswell NRI: Add read MPR training
by Angel Pons (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Arthur Heymans, Nico Huber. Hello Arthur Heymans, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64196?usp=email to look at the new patch set (#8). Change subject: haswell NRI: Add read MPR training ...................................................................... haswell NRI: Add read MPR training Implement read training using DDR3 MPR (Multi-Purpose Register). Change-Id: Id17cb2c4c399ac9bcc937b595b58f863c152461b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/native_raminit/Makefile.mk M src/northbridge/intel/haswell/native_raminit/raminit_main.c M src/northbridge/intel/haswell/native_raminit/raminit_native.h A src/northbridge/intel/haswell/native_raminit/train_read_mpr.c M src/northbridge/intel/haswell/registers/mchbar.h 5 files changed, 248 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/64196/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/64196?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id17cb2c4c399ac9bcc937b595b58f863c152461b Gerrit-Change-Number: 64196 Gerrit-PatchSet: 8 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[main]: haswell NRI: Add REUT I/O test library
by Angel Pons (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Arthur Heymans, Nico Huber. Hello Arthur Heymans, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64191?usp=email to look at the new patch set (#7). Change subject: haswell NRI: Add REUT I/O test library ...................................................................... haswell NRI: Add REUT I/O test library Implement a library to run I/O tests using the REUT hardware. Change-Id: Id7b207cd0a3989ddd23c88c6b1f0cfa79d2c861f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/native_raminit/Makefile.mk M src/northbridge/intel/haswell/native_raminit/raminit_native.h M src/northbridge/intel/haswell/native_raminit/reg_structs.h A src/northbridge/intel/haswell/native_raminit/testing_io.c M src/northbridge/intel/haswell/registers/mchbar.h 5 files changed, 1,006 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/64191/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/64191?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id7b207cd0a3989ddd23c88c6b1f0cfa79d2c861f Gerrit-Change-Number: 64191 Gerrit-PatchSet: 7 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: haswell NRI: Add DDR3 JEDEC reset and init
by Angel Pons (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Arthur Heymans, Nico Huber. Hello Arthur Heymans, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64189?usp=email to look at the new patch set (#7). Change subject: haswell NRI: Add DDR3 JEDEC reset and init ...................................................................... haswell NRI: Add DDR3 JEDEC reset and init Implement JEDEC reset and init sequence for DDR3. The MRS commands are issued through the REUT (Robust Electrical Unified Testing) hardware. Change-Id: I2a0c066537021b587599228086727cb1e041bff5 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/native_raminit/Makefile.mk A src/northbridge/intel/haswell/native_raminit/ddr3.c M src/northbridge/intel/haswell/native_raminit/io_comp_control.c A src/northbridge/intel/haswell/native_raminit/jedec_reset.c M src/northbridge/intel/haswell/native_raminit/raminit_main.c M src/northbridge/intel/haswell/native_raminit/raminit_native.h M src/northbridge/intel/haswell/native_raminit/reg_structs.h A src/northbridge/intel/haswell/native_raminit/reut.c M src/northbridge/intel/haswell/registers/mchbar.h M src/southbridge/intel/lynxpoint/pch.h 10 files changed, 833 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/64189/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/64189?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2a0c066537021b587599228086727cb1e041bff5 Gerrit-Change-Number: 64189 Gerrit-PatchSet: 7 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2024