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Change subject: arch/x86: Prevent .text/.init overlap with older linkers
......................................................................
arch/x86: Prevent .text/.init overlap with older linkers
Add Kconfig option `PROGRAM_SZ_EXTRA_SPACE` to reserve extra space,
avoiding overlap between .text and .init sections when using older
linkers (binutils 2.3x). Default is 1024 bytes (1 KiB) for ChromeOS,
0 otherwise.
BUG=b:332445618
TEST=Built and booted google/rex (32-bit/64-bit).
Change-Id: I019bf6896d84b2a84dff6f22323f0f446c0740b5
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/arch/x86/Kconfig
M src/arch/x86/bootblock.ld
2 files changed, 12 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/81886/2
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Gerrit-Change-Id: I019bf6896d84b2a84dff6f22323f0f446c0740b5
Gerrit-Change-Number: 81886
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81886?usp=email )
Change subject: arch/x86: Prevent .text/.init overlap with older linkers
......................................................................
arch/x86: Prevent .text/.init overlap with older linkers
Add Kconfig option `PROGRAM_SZ_EXTRA_SPACE` to reserve extra space,
avoiding overlap between .text and .init sections when using older
linkers (binutils 2.3x). Default is 1024 bytes (1 KiB) for ChromeOS,
0 otherwise.
BUG=b:332445618
TEST=Built and booted google/rex (32-bit/64-bit).
Change-Id: I019bf6896d84b2a84dff6f22323f0f446c0740b5
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/arch/x86/Kconfig
M src/arch/x86/bootblock.ld
2 files changed, 12 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/81886/1
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index d2ae320..2f64f21 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -412,4 +412,15 @@
If not set, both CPU and SoC physical address width are
assume to be the same.
+config PROGRAM_SZ_EXTRA_SPACE
+ hex
+ default 1024 if CHROMEOS
+ default 0
+ help
+ Add extra space to prevent overlap between .text and .init sections.
+ This is necessary for older linkers (pre-binutils 2.4x) like those used
+ on ChromeOS platforms.
+
+ The default value is 1024 bytes (1 KiB) for ChromeOS and 0 for other platforms.
+
endif
diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld
index 73a3d18..ce70f58 100644
--- a/src/arch/x86/bootblock.ld
+++ b/src/arch/x86/bootblock.ld
@@ -26,7 +26,7 @@
INCLUDE "bootblock/lib/program.ld"
- PROGRAM_SZ = SIZEOF(.text) + SIZEOF(.data);
+ PROGRAM_SZ = SIZEOF(.text) + SIZEOF(.data) + CONFIG_PROGRAM_SZ_EXTRA_SPACE;
. = MIN(_ECFW_PTR, MIN(_ID_SECTION, _FIT_POINTER)) - EARLYASM_SZ;
. = CONFIG(SIPI_VECTOR_IN_ROM) ? ALIGN(4096) : ALIGN(16);
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81846?usp=email )
Change subject: soc/intel/common: Add Lunar Lake CNVI device IDs
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
(I’d be nice, if these formal things would have been caught before the submitting the patch to save reviewers some time.)
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Change subject: soc/intel/{common, lunarlake}: Add support for new MCH
......................................................................
Patch Set 2:
(7 comments)
Commit Message:
PS2:
Just reading the commit message, I would have thought the diff to be different. Maybe mention, that it’s another stepping(?) for Lunar Lake. Now idea about the correct term.
https://review.coreboot.org/c/coreboot/+/81847/comment/801147d4_8bf70cee :
PS2, Line 7: soc/intel/{common, lunarlake}: Add support for new MCH
The prefix does not need to be the path. Maybe:
> soc/intel: Add support for new MCH Lunar Lake (0x6410)
After reading the diff:
> soc/intel/lunarlake: Support stepping A0_2
https://review.coreboot.org/c/coreboot/+/81847/comment/f0a3bc46_b74e28a0 :
PS2, Line 10: (ID:0x6410)
I’d write: … with id 0x640
But it’s a minor comment. Feel free to ignore.
https://review.coreboot.org/c/coreboot/+/81847/comment/15251af7_6e0c3d3e :
PS2, Line 10: The patch adds
“The patch” is redundant [1]. Just use the imperative mood:
> Add support for …
[1]: https://cbea.ms/git-commit/https://review.coreboot.org/c/coreboot/+/81847/comment/7b526f30_7eb5192d :
PS2, Line 11: Add new CPU ID (ID:0xb06d1)
Add new CPU id 0xb06d1
https://review.coreboot.org/c/coreboot/+/81847/comment/b9b0904e_60c79d93 :
PS2, Line 16: TEST=Build and boot the system having MCH ID:0x6410.
Which log line is that?
File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/81847/comment/734a48a2_9566e63b :
PS2, Line 4292: #define PCI_DID_INTEL_LNL_M_ID_1 0x6410
Name the above …1, and this one _2 for alignment reasons?
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81597?usp=email )
Change subject: cpu/intel/model_206ax: Allow to configure VR settings
......................................................................
Patch Set 2:
(2 comments)
File src/cpu/intel/model_206ax/model_206ax_init.c:
https://review.coreboot.org/c/coreboot/+/81597/comment/b245eee2_1e95cfcc :
PS2, Line 213: BIOS_INFO
> I feel these messages should be `BIOS_DEBUG`
IMHO all devicetrees should contain those value. Maybe BIOS_WARNING?
File src/mainboard/lenovo/x220/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/81597/comment/d533bf77_fa516a86 :
PS2, Line 41: 98
> Where does this number come from?
As the comment above states, extracted from vendor firmware.
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Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81885?usp=email )
Change subject: mb/asus/p8z77-m: Enable keyboard/mouse swap option
......................................................................
mb/asus/p8z77-m: Enable keyboard/mouse swap option
Feature provided by commit xxxxxxxxxxxx (superio/nuvoton/nct6779d:
Allow swapping PS/2 keyboard/mouse ports)
TEST=PS/2 mouse (Logitech M-S48) works with option turned on.
PS/2 keyboard (IBM Model M #1391401 and Microsoft Natural gen 1)
still works with option turned off.
Change-Id: I21b73da99168e751b1a23485d4b1695963f9eef5
Signed-off-by: Keith Hui <buurin(a)gmail.com>
---
M src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/81885/1
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout
index 3053b8d..0ee3a9f 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout
@@ -51,6 +51,8 @@
#
424 1 e 1 usb3_streams
+426 1 e 1 swap_keyboard_and_mouse
+
# -----------------------------------------------------------------
# Sandy/Ivy Bridge MRC Scrambler Seed values
# note: MUST NOT be covered by checksum!
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Change subject: superio/nuvoton/nct6779d: Allow swapping PS/2 keyboard/mouse ports
......................................................................
superio/nuvoton/nct6779d: Allow swapping PS/2 keyboard/mouse ports
Add nvram option to allow user to manually swap PS/2 keyboard and mouse
ports (i.e. keyboard port serves the mouse instead).
This is intended for mainboards with only one PS/2 port for either
keyboard or mouse. Until coreboot gets improved keyboard and mouse
detection and initialization and can decide on its own when to swap,
this option allows PS/2 mouse connected to this one port a chance
to work in the OS.
Without this support, the one PS/2 port works with keyboards only.
TEST=With nvram option added to asus/p8x7x-series/v/p8z77-m and turned
on, PS/2 mouse works.
Change-Id: I2d58719c207da973ad049cb9151d92f31ff6cd92
Signed-off-by: Keith Hui <buurin(a)gmail.com>
---
M src/superio/nuvoton/nct6779d/superio.c
1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/81884/1
diff --git a/src/superio/nuvoton/nct6779d/superio.c b/src/superio/nuvoton/nct6779d/superio.c
index e908c9c..09942d6 100644
--- a/src/superio/nuvoton/nct6779d/superio.c
+++ b/src/superio/nuvoton/nct6779d/superio.c
@@ -12,6 +12,7 @@
{
uint8_t byte;
uint8_t power_status;
+ uint8_t swap_kbd_mouse;
if (!dev->enabled)
return;
@@ -38,12 +39,20 @@
power_status = get_uint_option("power_on_after_fail",
CONFIG_MAINBOARD_POWER_FAILURE_STATE) & 0x03;
+ swap_kbd_mouse = get_uint_option("swap_keyboard_and_mouse", 0) & 0x1;
pnp_enter_conf_mode(dev);
pnp_set_logical_device(dev);
byte = pnp_read_config(dev, 0xe4);
byte &= ~0x60;
byte |= (power_status << 5);
pnp_write_config(dev, 0xe4, byte);
+ /* Swap keyboard and mouse port if requested */
+ byte = pnp_read_config(dev, 0xe0);
+ if (swap_kbd_mouse)
+ byte |= (1 << 2);
+ else
+ byte &= ~(1 << 2);
+ pnp_write_config(dev, 0xe0, byte);
pnp_exit_conf_mode(dev);
break;
}
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