coreboot-gerrit April 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: arch/x86: Prevent .text/.init overlap with older linkers
by Subrata Banik (Code Review) 13 Apr '24

13 Apr '24

Attention is currently required from: Arthur Heymans, Jérémy Compostella, Nico Huber. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81886?usp=email ) Change subject: arch/x86: Prevent .text/.init overlap with older linkers ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81886/comment/733631e9_ede0ded2 : PS2, Line 11: (binutils 2.3x) > Are you sure this is used with the main branch? I was told ChromeOS > always uses the newest toolchain (and hence we have to restrict > toolchain updates to the releases). binutils was updated to 2.40 > a year ago. we are still using 2.37 version and raised an internal bug https://b.corp.google.com/issues/332445618 to perform an uprev to 2.42 to switch to the new binutil. But as said, the existing EDK2 builds are failing (as Intel FSP/EDK2 code are not supportive of the latest tool chain). https://review.coreboot.org/c/coreboot/+/81886/comment/326aef17_dd5e4619 : PS2, Line 11: Default is 1024 bytes (1 KiB) > There was a comment on another change (CB:81678) stating that > SIZEOF() is returning 0 (with the old binutils). If that's the > case, 1KiB might not be enough (possibly depending on alignment). I have made a test run on all platform using chromium mainline and don't see any issue after picking this CL. but point noted incase we run into any issue in future. -- To view, visit https://review.coreboot.org/c/coreboot/+/81886?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I019bf6896d84b2a84dff6f22323f0f446c0740b5 Gerrit-Change-Number: 81886 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 13 Apr 2024 11:26:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: util/intelp2m: Avoid adding blank line after '{'
by Maxim (Code Review) 13 Apr '24

13 Apr '24

Attention is currently required from: Elyes Haouas. Maxim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81547?usp=email ) Change subject: util/intelp2m: Avoid adding blank line after '{' ...................................................................... Patch Set 1: (1 comment) File util/intelp2m/parser/parser.go: https://review.coreboot.org/c/coreboot/+/81547/comment/0df00351_71cbb92c : PS1, Line 53: if !strings.Contains(info.function, "GPIO Community 0") { If I understand correctly, this is about removing blank line after `static const struct pad_config gpio_table[] = {`. But these changes don't fix this. Need to remove the line break in https://github.com/coreboot/coreboot/blob/main/util/intelp2m/main.go#L24 only: ``` config.OutputGenFile.WriteString(`/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef CFG_GPIO_H #define CFG_GPIO_H #include <gpio.h> /* Pad configuration was generated automatically using intelp2m utility */ static const struct pad_config gpio_table[] = {`) <--- [!] ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/81547?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8105734b1b4776d0eb01b13c80e21e130719fe83 Gerrit-Change-Number: 81547 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 13 Apr 2024 11:17:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: lenovo/haswell: enable ONBOARD_VGA_IS_PRIMARY
by Nico Huber (Code Review) 13 Apr '24

13 Apr '24

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81645?usp=email ) Change subject: lenovo/haswell: enable ONBOARD_VGA_IS_PRIMARY ...................................................................... lenovo/haswell: enable ONBOARD_VGA_IS_PRIMARY Haswell ThinkPads have Nvidia Optimus wired in on some models. With recent coreboot changes, legacy VGA decode is now disabled on the iGPU, and the iGPU itself is disabled, when a dGPU is present. This is a problem on Optimus laptops, because it means that the Intel GPU would be effectively disabled, when it is the one that has to handle the framebuffer. On these boards, you can enable ONBOARD_VGA_IS_PRIMARY so that coreboot does not disable the iGPU. This is because on Optimus laptops, the Nvidia GPU is only used for offloaded rendering. Enable ONBOARD_VGA_IS_PRIMARY by default on these boards. Change-Id: I8f1e0ca2861d1cc9a9ad41e7c9257aeca1a62a31 Signed-off-by: Leah Rowe <info(a)minifree.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81645 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/lenovo/haswell/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Nico Huber: Looks good to me, approved diff --git a/src/mainboard/lenovo/haswell/Kconfig b/src/mainboard/lenovo/haswell/Kconfig index b874452..a5c8054 100644 --- a/src/mainboard/lenovo/haswell/Kconfig +++ b/src/mainboard/lenovo/haswell/Kconfig @@ -60,6 +60,10 @@ default "ThinkPad T440p" if BOARD_LENOVO_THINKPAD_T440P default "ThinkPad W541" if BOARD_LENOVO_THINKPAD_W541 +config ONBOARD_VGA_IS_PRIMARY + bool + default y + config VGA_BIOS_ID string default "8086,0416" if BOARD_LENOVO_THINKPAD_T440P -- To view, visit https://review.coreboot.org/c/coreboot/+/81645?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f1e0ca2861d1cc9a9ad41e7c9257aeca1a62a31 Gerrit-Change-Number: 81645 Gerrit-PatchSet: 2 Gerrit-Owner: Leah Rowe <leahleahrowerowe(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/broadwell/pch/sata.c: Add missing SATA init steps
by Angel Pons (Code Review) 13 Apr '24

13 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47029 ) Change subject: soc/intel/broadwell/pch/sata.c: Add missing SATA init steps ...................................................................... soc/intel/broadwell/pch/sata.c: Add missing SATA init steps WildcatPoint-LP BIOS spec lists them, and are the same for Lynxpoint. Keep the BWG comments for now, since both platforms will be merged soon. Change-Id: Iba28c1591affafeb37097084c2fa58128974bd00 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/sata.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/47029/1 diff --git a/src/soc/intel/broadwell/pch/sata.c b/src/soc/intel/broadwell/pch/sata.c index 91c2ff5..e9d70f1 100644 --- a/src/soc/intel/broadwell/pch/sata.c +++ b/src/soc/intel/broadwell/pch/sata.c @@ -95,6 +95,15 @@ /* Setup register 98h */ reg32 = pci_read_config32(dev, 0x98); + reg32 |= 1 << 19; /* BWG step 6 */ + reg32 |= 1 << 22; /* BWG step 5 */ + reg32 &= ~(0x3f << 7); + reg32 |= 0x04 << 7; /* BWG step 7 */ + reg32 |= 1 << 20; /* BWG step 8 */ + reg32 &= ~(0x03 << 5); + reg32 |= 1 << 5; /* BWG step 9 */ + reg32 |= 1 << 18; /* BWG step 10 */ + reg32 |= 1 << 29; /* BWG step 11 */ reg32 &= ~((1 << 31) | (1 << 30)); reg32 |= 1 << 23; reg32 |= 1 << 24; /* Enable MPHY Dynamic Power Gating */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba28c1591affafeb37097084c2fa58128974bd00 Gerrit-Change-Number: 47029 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: nb/intel/gm45: Fill in memory info
by Nico Huber (Code Review) 13 Apr '24

13 Apr '24

Attention is currently required from: Angel Pons, Jean Lucas, Nicholas Chin. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81861?usp=email ) Change subject: nb/intel/gm45: Fill in memory info ...................................................................... Patch Set 1: Code-Review+2 (2 comments) File src/northbridge/intel/gm45/raminit_meminfo.c: https://review.coreboot.org/c/coreboot/+/81861/comment/4f6610df_bda41035 : PS1, Line 63: 2 Too bad we don't have a constant for this. I suppose it should be `ARRAY_SIZE(sysinfo->spd_map) / TOTAL_CHANNELS`. As we know this won't change, I guess we can just leave the literal 2. https://review.coreboot.org/c/coreboot/+/81861/comment/b4755742_d8a091a9 : PS1, Line 83: mem_info->number_of_devices = 2; Is this like the number of slots? Just curious. -- To view, visit https://review.coreboot.org/c/coreboot/+/81861?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92060ce05bdf0ca617a3383a2db1fdbd43df6fe4 Gerrit-Change-Number: 81861 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jean Lucas Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jean Lucas Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sat, 13 Apr 2024 11:10:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: sandybridge,haswell,broadwell: Use DIV_ROUND_CLOSEST macro
by Nico Huber (Code Review) 13 Apr '24

13 Apr '24

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52651?usp=email ) Change subject: sandybridge,haswell,broadwell: Use DIV_ROUND_CLOSEST macro ...................................................................... sandybridge,haswell,broadwell: Use DIV_ROUND_CLOSEST macro Integer division in C truncates toward zero. When the dividend and the divisor are positive, one can add half of the divisor to the dividend to round the division result towards the closest integer. We already have a macro in commonlib to do just that, so put it to good use. Tested with BUILD_TIMELESS=1, coreboot images for the Asus P8Z77-V LX2 and the Asrock B85M Pro4 do not change. Change-Id: I251af82da15049a3a2aa6ea712ae8c9fe859caf6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52651 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Benjamin Doron <benjamin.doron00(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/intel/haswell/haswell_mrc/raminit.c M src/northbridge/intel/sandybridge/raminit_shared.c M src/soc/intel/broadwell/raminit.c 3 files changed, 4 insertions(+), 3 deletions(-) Approvals: Nico Huber: Looks good to me, approved build bot (Jenkins): Verified Benjamin Doron: Looks good to me, approved diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c index f23e40d..7109e46 100644 --- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c @@ -73,7 +73,7 @@ const u32 addr_decoder_common = mchbar_read32(MAD_CHNL); printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100); + DIV_ROUND_CLOSEST(mchbar_read32(MC_BIOS_DATA) * 13333 * 2, 100)); printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", (addr_decoder_common >> 0) & 3, diff --git a/src/northbridge/intel/sandybridge/raminit_shared.c b/src/northbridge/intel/sandybridge/raminit_shared.c index 543d285..8ba20ac 100644 --- a/src/northbridge/intel/sandybridge/raminit_shared.c +++ b/src/northbridge/intel/sandybridge/raminit_shared.c @@ -29,7 +29,7 @@ printk(BIOS_DEBUG, "memcfg DDR3 ref clock %d MHz\n", refclk); printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (mchbar_read32(MC_BIOS_DATA) * refclk * 100 * 2 + 50) / 100); + DIV_ROUND_CLOSEST(mchbar_read32(MC_BIOS_DATA) * refclk * 100 * 2, 100)); printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", (addr_decoder_common >> 0) & 3, diff --git a/src/soc/intel/broadwell/raminit.c b/src/soc/intel/broadwell/raminit.c index c55e755..cacf8ecc 100644 --- a/src/soc/intel/broadwell/raminit.c +++ b/src/soc/intel/broadwell/raminit.c @@ -16,6 +16,7 @@ #include <soc/romstage.h> #include <soc/systemagent.h> #include <timestamp.h> +#include <types.h> static void save_mrc_data(struct pei_data *pei_data) { @@ -46,7 +47,7 @@ const u32 addr_decoder_common = mchbar_read32(MAD_CHNL); printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100); + DIV_ROUND_CLOSEST(mchbar_read32(MC_BIOS_DATA) * 13333 * 2, 100)); printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", (addr_decoder_common >> 0) & 3, -- To view, visit https://review.coreboot.org/c/coreboot/+/52651?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I251af82da15049a3a2aa6ea712ae8c9fe859caf6 Gerrit-Change-Number: 52651 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <rudolphpatrick05(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: sandybridge,haswell,broadwell: Use DIV_ROUND_CLOSEST macro
by Nico Huber (Code Review) 13 Apr '24

13 Apr '24

Attention is currently required from: Angel Pons. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52651?usp=email ) Change subject: sandybridge,haswell,broadwell: Use DIV_ROUND_CLOSEST macro ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52651?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I251af82da15049a3a2aa6ea712ae8c9fe859caf6 Gerrit-Change-Number: 52651 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <rudolphpatrick05(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sat, 13 Apr 2024 10:53:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/asus/p8z77-m: Enable keyboard/mouse swap option
by Nico Huber (Code Review) 13 Apr '24

13 Apr '24

Attention is currently required from: Keith Hui. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81885?usp=email ) Change subject: mb/asus/p8z77-m: Enable keyboard/mouse swap option ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81885?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I21b73da99168e751b1a23485d4b1695963f9eef5 Gerrit-Change-Number: 81885 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Sat, 13 Apr 2024 10:45:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: superio/nuvoton/nct6779d: Allow swapping PS/2 keyboard/mouse ports
by Nico Huber (Code Review) 13 Apr '24

13 Apr '24

Attention is currently required from: Keith Hui. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81884?usp=email ) Change subject: superio/nuvoton/nct6779d: Allow swapping PS/2 keyboard/mouse ports ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81884?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d58719c207da973ad049cb9151d92f31ff6cd92 Gerrit-Change-Number: 81884 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Sat, 13 Apr 2024 10:45:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: superio/nuvoton/nct6779d: Add power_on_after_fail support
by Nico Huber (Code Review) 13 Apr '24

13 Apr '24

Attention is currently required from: Keith Hui. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81883?usp=email ) Change subject: superio/nuvoton/nct6779d: Add power_on_after_fail support ...................................................................... Patch Set 1: Code-Review+1 (2 comments) Patchset: PS1: We could also make it a common function for Nuvoton SIOs? File src/superio/nuvoton/nct6779d/superio.c: https://review.coreboot.org/c/coreboot/+/81883/comment/2f01506d_1f85abe9 : PS1, Line 37: */ Same for the `cmos.layout` in case it's used. Not sure if it's worth that much commentary only to avoid two lines of code? -- To view, visit https://review.coreboot.org/c/coreboot/+/81883?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia08cf8daac971397e832996ed364d41e9e7b1c5d Gerrit-Change-Number: 81883 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Sat, 13 Apr 2024 10:42:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2024