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[M] Change in coreboot[main]: superio/ite: Add special fan vectors
by Nico Huber (Code Review) 13 Apr '24

13 Apr '24

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81426?usp=email ) Change subject: superio/ite: Add special fan vectors ...................................................................... superio/ite: Add special fan vectors A number of ITE SIOs support "special fan control vectors", which effectively allow non-linear fan speed control. This is for example used by the vendor firmware of the "HP Pro 3500 Series". The special vector registers won't be written to until the mb's devicetree configures `FAN_VECX.tmp_start != 0`. Change-Id: I93df2b5652fc3fde775b6161fa5bebc4a34d5e94 Signed-off-by: Joel Linn <jl(a)conductive.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81426 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/superio/ite/common/Kconfig M src/superio/ite/common/env_ctrl.c M src/superio/ite/common/env_ctrl.h M src/superio/ite/common/env_ctrl_chip.h M src/superio/ite/it8728f/Kconfig M src/superio/ite/it8772f/Kconfig 6 files changed, 95 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, but someone else must approve Nico Huber: Looks good to me, approved diff --git a/src/superio/ite/common/Kconfig b/src/superio/ite/common/Kconfig index 6fde3c8..4701056 100644 --- a/src/superio/ite/common/Kconfig +++ b/src/superio/ite/common/Kconfig @@ -54,4 +54,15 @@ Fan controller does not support running at full speed when limit temperature is reached. +config SUPERIO_ITE_ENV_CTRL_FAN_VECTOR + bool + help + Special fan control that will assist the smart control + +config SUPERIO_ITE_ENV_CTRL_FAN_VECTOR_RANGED + bool + depends on SUPERIO_ITE_ENV_CTRL_FAN_VECTOR + help + Range and negative slope support + endif diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index 1124019..105d6da 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -253,6 +253,49 @@ } } +static void enable_fan_vector(const u16 base, const u8 fan_vector, + const struct ite_ec_fan_vector_config *const conf) +{ + u8 reg; + + u8 start = conf->tmp_start; + if (!start) { + /* When tmp_start is not configured we would set the + * register to it's default of 0xFF here, which would + * effectively disable the vector functionality of the + * SuperIO altogether since that temperature will never + * be reached. We can therefore return here and don't + * need to set any other registers. + */ + return; + } + pnp_write_hwm5_index(base, ITE_EC_FAN_VEC_CTL_LIMIT_START(fan_vector), start); + + const s8 slope = conf->slope; + const bool slope_neg = slope < 0; + if (slope <= -128) + reg = 127; + else if (slope_neg) + reg = -slope; + else + reg = slope; + reg |= ITE_EC_FAN_VEC_CTL_SLOPE_TMPIN0(conf->tmpin); + pnp_write_hwm5_index(base, ITE_EC_FAN_VEC_CTL_SLOPE(fan_vector), reg); + + reg = ITE_EC_FAN_VEC_CTL_DELTA_TEMP_INTRVL(conf->tmp_delta); + reg |= ITE_EC_FAN_VEC_CTL_DELTA_FANOUT(conf->fanout); + reg |= ITE_EC_FAN_VEC_CTL_DELTA_TMPIN1(conf->tmpin); + pnp_write_hwm5_index(base, ITE_EC_FAN_VEC_CTL_DELTA(fan_vector), reg); + + if (CONFIG(SUPERIO_ITE_ENV_CTRL_FAN_VECTOR_RANGED)) { + reg = conf->tmp_range & 0x7f; + reg |= ITE_EC_FAN_VEC_CTL_RANGE_SLOPESIGN(slope_neg); + pnp_write_hwm5_index(base, ITE_EC_FAN_VEC_CTL_RANGE(fan_vector), reg); + } else if (slope_neg) { + printk(BIOS_WARNING, "Unsupported negative slope on fan vector control\n"); + } +} + static void enable_beeps(const u16 base, const struct ite_ec_config *const conf) { u8 reg = 0; @@ -313,6 +356,12 @@ for (i = 0; i < ITE_EC_FAN_CNT; ++i) enable_fan(base, i + 1, &conf->fan[i]); + if (CONFIG(SUPERIO_ITE_ENV_CTRL_FAN_VECTOR)) { + /* Enable Special FAN Vector X if configured */ + for (i = 0; i < ITE_EC_FAN_VECTOR_CNT; ++i) + enable_fan_vector(base, i, &conf->fan_vector[i]); + } + /* Enable beeps if configured */ enable_beeps(base, conf); diff --git a/src/superio/ite/common/env_ctrl.h b/src/superio/ite/common/env_ctrl.h index 5a31e7c..8a461aa 100644 --- a/src/superio/ite/common/env_ctrl.h +++ b/src/superio/ite/common/env_ctrl.h @@ -199,6 +199,17 @@ #define ITE_EC_FAN_CTL_TARGET_ZONE(x) (0x66 + ((x)-1) * 8) #define ITE_EC_FAN_CTL_TARGET_ZONE_MASK 0x0f +#define ITE_EC_FAN_VEC_CTL_LIMIT_START(x) (0x90 + (x) * 4) +#define ITE_EC_FAN_VEC_CTL_SLOPE(x) (0x91 + (x) * 4) +#define ITE_EC_FAN_VEC_CTL_DELTA(x) (0x92 + (x) * 4) +#define ITE_EC_FAN_VEC_CTL_RANGE(x) (0x93 + (x) * 4) + +#define ITE_EC_FAN_VEC_CTL_SLOPE_TMPIN0(x) (((x) & 0x1) << 7) +#define ITE_EC_FAN_VEC_CTL_DELTA_TMPIN1(x) (((x) & 0x2) << 6) +#define ITE_EC_FAN_VEC_CTL_DELTA_TEMP_INTRVL(c) ITE_EC_FAN_CTL_DELTA_TEMP_INTRVL(c) +#define ITE_EC_FAN_VEC_CTL_DELTA_FANOUT(x) (((x) & 0x3) << 5) +#define ITE_EC_FAN_VEC_CTL_RANGE_SLOPESIGN(x) (((x) & 0x1) << 7) + #define ITE_EC_EXTEMP_STATUS 0x88 #define ITE_EC_EXTEMP_STATUS_HOST_BUSY (1 << 0) #define ITE_EC_EXTEMP_ADDRESS 0x89 diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h index 2bb0780..6d716bb 100644 --- a/src/superio/ite/common/env_ctrl_chip.h +++ b/src/superio/ite/common/env_ctrl_chip.h @@ -11,6 +11,8 @@ #define ITE_EC_FAN_CNT 3 #endif +#define ITE_EC_FAN_VECTOR_CNT 2 /* A, B */ + /* Supported thermal mode on TMPINx */ enum ite_ec_thermal_mode { THERMAL_MODE_DISABLED = 0, @@ -69,6 +71,17 @@ struct ite_ec_fan_smartconfig smart; }; +/* Special fan control modes that will assist smart control */ +struct ite_ec_fan_vector_config { + u8 tmpin; /* select TMPINx (1, 2 or 3) */ + u8 fanout; /* select FANx (1, 2 or 3) */ + u8 tmp_start; + u8 tmp_delta; + u8 tmp_range; /* restrict the range of the vector function, + 0x00 to disable */ + s8 slope; +}; + struct ite_ec_config { /* * Enable reading of voltage pins VINx. @@ -85,6 +98,11 @@ */ struct ite_ec_fan_config fan[ITE_EC_FAN_CNT]; + /* + * Enable special FAN vector control. + */ + struct ite_ec_fan_vector_config fan_vector[ITE_EC_FAN_VECTOR_CNT]; + bool tmpin_beep; bool fan_beep; bool vin_beep; @@ -111,4 +129,7 @@ #define FAN4 ec.fan[3] #define FAN5 ec.fan[4] +#define FAN_VECA ec.fan_vector[0] +#define FAN_VECB ec.fan_vector[1] + #endif /* SUPERIO_ITE_ENV_CTRL_CHIP_H */ diff --git a/src/superio/ite/it8728f/Kconfig b/src/superio/ite/it8728f/Kconfig index 6d02c0b..be16a2d 100644 --- a/src/superio/ite/it8728f/Kconfig +++ b/src/superio/ite/it8728f/Kconfig @@ -10,3 +10,4 @@ select SUPERIO_ITE_ENV_CTRL_5FANS select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + select SUPERIO_ITE_ENV_CTRL_FAN_VECTOR diff --git a/src/superio/ite/it8772f/Kconfig b/src/superio/ite/it8772f/Kconfig index 3137cf0..8e9af54 100644 --- a/src/superio/ite/it8772f/Kconfig +++ b/src/superio/ite/it8772f/Kconfig @@ -7,5 +7,7 @@ select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG select SUPERIO_ITE_ENV_CTRL_8BIT_PWM select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + select SUPERIO_ITE_ENV_CTRL_FAN_VECTOR + select SUPERIO_ITE_ENV_CTRL_FAN_VECTOR_RANGED select SUPERIO_ITE_ENV_CTRL_NO_FULLSPEED_SETTING select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81426?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I93df2b5652fc3fde775b6161fa5bebc4a34d5e94 Gerrit-Change-Number: 81426 Gerrit-PatchSet: 8 Gerrit-Owner: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: superio/ite: Unify it8772f with common code
by Nico Huber (Code Review) 13 Apr '24

13 Apr '24

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81310?usp=email ) Change subject: superio/ite: Unify it8772f with common code ...................................................................... superio/ite: Unify it8772f with common code The it8772f is now configured by the much better common code that is used for other chips in the family as well. This mainly concerns the EC, the GPIO functionality was not moved to common as it currently lacks a sane abstraction in any codebase. The datasheets of the it8772e(f) and it8728f (for reference) were studied and verified against the common code, adding exceptions where needed. Change-Id: Ic4d9d5460628e444dc20f620179b39c90dbc28c6 Signed-off-by: Joel Linn <jl(a)conductive.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81310 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/beltino/bootblock.c M src/mainboard/google/beltino/devicetree.cb M src/mainboard/google/beltino/onboard.h M src/mainboard/google/jecht/bootblock.c M src/mainboard/google/jecht/devicetree.cb M src/mainboard/google/jecht/onboard.h M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb M src/mainboard/samsung/stumpy/early_init.c M src/mainboard/samsung/stumpy/smihandler.c M src/superio/ite/common/early_serial.c M src/superio/ite/common/ite.h M src/superio/ite/it8772f/Kconfig M src/superio/ite/it8772f/chip.h M src/superio/ite/it8772f/early_init.c M src/superio/ite/it8772f/it8772f.h M src/superio/ite/it8772f/superio.c 17 files changed, 67 insertions(+), 326 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved Nico Huber: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/beltino/bootblock.c b/src/mainboard/google/beltino/bootblock.c index a68b03f..4139e38 100644 --- a/src/mainboard/google/beltino/bootblock.c +++ b/src/mainboard/google/beltino/bootblock.c @@ -9,7 +9,7 @@ { /* Early SuperIO setup */ ite_kill_watchdog(IT8772F_GPIO_DEV); - it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV); + ite_ac_resume_southbridge(IT8772F_EC_DEV); ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE); /* Turn on Power LED */ diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index cdaab35..d96ee11 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -81,9 +81,9 @@ # Skip keyboard init register "skip_keyboard" = "true" # Enable PECI on TMPIN3 - register "peci_tmpin" = "3" + register "TMPIN3.mode" = "THERMAL_PECI" # Enable FAN2 - register "fan2_enable" = "true" + register "FAN2.mode" = "FAN_SMART_SOFTWARE" device pnp 2e.0 off end # FDC device pnp 2e.1 on # Serial Port 1 diff --git a/src/mainboard/google/beltino/onboard.h b/src/mainboard/google/beltino/onboard.h index 8bd21ce..36295ec 100644 --- a/src/mainboard/google/beltino/onboard.h +++ b/src/mainboard/google/beltino/onboard.h @@ -26,7 +26,7 @@ #define IT8772F_BASE 0x2e #define IT8772F_SERIAL_DEV PNP_DEV(IT8772F_BASE, IT8772F_SP1) #define IT8772F_GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO) -#define IT8772F_SUPERIO_DEV PNP_DEV(IT8772F_BASE, 0) +#define IT8772F_EC_DEV PNP_DEV(IT8772F_BASE, IT8772F_EC) #ifndef __ACPI__ void lan_init(void); diff --git a/src/mainboard/google/jecht/bootblock.c b/src/mainboard/google/jecht/bootblock.c index db590cf..02b078e 100644 --- a/src/mainboard/google/jecht/bootblock.c +++ b/src/mainboard/google/jecht/bootblock.c @@ -8,7 +8,7 @@ void bootblock_mainboard_early_init(void) { /* Early SuperIO setup */ - it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV); + ite_ac_resume_southbridge(IT8772F_EC_DEV); ite_kill_watchdog(IT8772F_GPIO_DEV); ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index 1bf8a2a..ba8167cd 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -75,15 +75,13 @@ # Skip keyboard init register "skip_keyboard" = "true" # Enable PECI on TMPIN3 - register "peci_tmpin" = "3" - # Disable use of TMPIN1 - register "tmpin1_mode" = "0" + register "TMPIN3.mode" = "THERMAL_PECI" # Enable Thermal Diode on TMPIN2 - register "tmpin2_mode" = "1" + register "TMPIN2.mode" = "THERMAL_DIODE" # Enable FAN2 - register "fan2_enable" = "true" + register "FAN2.mode" = "FAN_SMART_SOFTWARE" # Default FAN2 speed - register "fan2_speed" = "0x4d" + register "FAN2.smart.pwm_start" = "30" device pnp 2e.0 off end # FDC device pnp 2e.1 on # Serial Port 1 diff --git a/src/mainboard/google/jecht/onboard.h b/src/mainboard/google/jecht/onboard.h index a6ba80a..ae68fb8 100644 --- a/src/mainboard/google/jecht/onboard.h +++ b/src/mainboard/google/jecht/onboard.h @@ -35,7 +35,7 @@ #define IT8772F_BASE 0x2e #define IT8772F_SERIAL_DEV PNP_DEV(IT8772F_BASE, IT8772F_SP1) #define IT8772F_GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO) -#define IT8772F_SUPERIO_DEV PNP_DEV(IT8772F_BASE, 0) +#define IT8772F_EC_DEV PNP_DEV(IT8772F_BASE, IT8772F_EC) /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ #define GPIO_SPI_WP 58 diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 092115c..87bc5de 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -209,9 +209,9 @@ end device ref lpc_espi on chip superio/ite/it8772f - register "peci_tmpin" = "3" - register "tmpin1_mode" = "THERMAL_RESISTOR" - register "tmpin2_mode" = "THERMAL_RESISTOR" + register "TMPIN1.mode" = "THERMAL_RESISTOR" + register "TMPIN2.mode" = "THERMAL_RESISTOR" + register "TMPIN3.mode" = "THERMAL_PECI" # FAN2 available on fan header but unused device pnp 2e.0 off end # FDC device pnp 2e.1 on # Serial Port 1 diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index ae3aab5..853e519 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -88,9 +88,9 @@ # Skip keyboard init register "skip_keyboard" = "true" # Enable PECI on TMPIN3 - register "peci_tmpin" = "3" + register "TMPIN3.mode" = "THERMAL_PECI" # Enable FAN3 - register "fan3_enable" = "true" + register "FAN3.mode" = "FAN_SMART_SOFTWARE" device pnp 2e.0 off end # FDC device pnp 2e.1 on # Serial Port 1 diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index 681373c..2719e33 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -12,9 +12,9 @@ #include <southbridge/intel/common/gpio.h> #include <superio/smsc/lpc47n207/lpc47n207.h> -#define SUPERIO_DEV PNP_DEV(0x2e, 0) #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) +#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) +#define EC_DEV PNP_DEV(0x2e, IT8772F_EC) void mainboard_late_rcba_config(void) { @@ -58,17 +58,17 @@ * GPIO10 as USBPWRON12# * GPIO12 as USBPWRON13# */ - it8772f_gpio_setup(SUPERIO_DEV, 1, 0x05, 0x05, 0x00, 0x05, 0x05); + it8772f_gpio_setup(GPIO_DEV, 1, 0x05, 0x05, 0x00, 0x05, 0x05); /* * GPIO22 as wake SCI# */ - it8772f_gpio_setup(SUPERIO_DEV, 2, 0x04, 0x04, 0x00, 0x04, 0x04); + it8772f_gpio_setup(GPIO_DEV, 2, 0x04, 0x04, 0x00, 0x04, 0x04); /* * GPIO32 as EXTSMI# */ - it8772f_gpio_setup(SUPERIO_DEV, 3, 0x04, 0x04, 0x00, 0x04, 0x04); + it8772f_gpio_setup(GPIO_DEV, 3, 0x04, 0x04, 0x00, 0x04, 0x04); /* * GPIO45 as LED_POWER# @@ -82,8 +82,8 @@ * GPIO51 as USBPWRON8# * GPIO52 as USBPWRON1# */ - it8772f_gpio_setup(SUPERIO_DEV, 5, 0x06, 0x06, 0x00, 0x06, 0x06); - it8772f_gpio_setup(SUPERIO_DEV, 6, 0x00, 0x00, 0x00, 0x00, 0x00); + it8772f_gpio_setup(GPIO_DEV, 5, 0x06, 0x06, 0x00, 0x06, 0x06); + it8772f_gpio_setup(GPIO_DEV, 6, 0x00, 0x00, 0x00, 0x00, 0x00); } void mainboard_fill_pei_data(struct pei_data *pei_data) @@ -117,7 +117,7 @@ setup_sio_gpios(); /* Early SuperIO setup */ - it8772f_ac_resume_southbridge(SUPERIO_DEV); + ite_ac_resume_southbridge(EC_DEV); ite_kill_watchdog(GPIO_DEV); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/samsung/stumpy/smihandler.c b/src/mainboard/samsung/stumpy/smihandler.c index 5000086..f9b9d3b 100644 --- a/src/mainboard/samsung/stumpy/smihandler.c +++ b/src/mainboard/samsung/stumpy/smihandler.c @@ -9,7 +9,7 @@ /* Include for SIO helper functions */ #include <superio/ite/it8772f/it8772f.h> -#define SUPERIO_DEV PNP_DEV(0x2e, 0) +#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) /* * Change LED_POWER# (SIO GPIO 45) state based on sleep type. @@ -20,14 +20,14 @@ switch (slp_typ) { case ACPI_S3: case ACPI_S4: - it8772f_gpio_led(SUPERIO_DEV, 4 /* set */, (0x1 << 5) /* select */, + it8772f_gpio_led(GPIO_DEV, 4 /* set */, (0x1 << 5) /* select */, (0x1 << 5) /* polarity */, (0x1 << 5) /* 1 = pullup */, (0x1 << 5) /* output */, 0x00, /* 0 = Alternate function */ SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); break; case ACPI_S5: - it8772f_gpio_led(SUPERIO_DEV, 4 /* set */, (0x1 << 5) /* select */, + it8772f_gpio_led(GPIO_DEV, 4 /* set */, (0x1 << 5) /* select */, 0x00 /* polarity: non-inverting */, 0x00 /* 0 = pulldown */, (0x1 << 5) /* output */, (0x1 << 5) /* 1 = Simple IO function */, SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); diff --git a/src/superio/ite/common/early_serial.c b/src/superio/ite/common/early_serial.c index 5ff403f..552f110 100644 --- a/src/superio/ite/common/early_serial.c +++ b/src/superio/ite/common/early_serial.c @@ -15,6 +15,7 @@ #define ITE_CONFIG_REG_WATCHDOG 0x72 /* watchdog config */ #define ITE_CONFIG_REG_WDT_TIMEOUT_LSB 0x73 /* watchdog timeout (LSB) */ #define ITE_CONFIG_REG_WDT_TIMEOUT_MSB 0x74 /* watchdog timeout (MSB) */ +#define ITE_CONFIG_REG_APC_PME_CTL2 0xf4 /* APC_PME Control 2 */ /* Helper procedure */ static void ite_sio_write(pnp_devfn_t dev, u8 reg, u8 value) @@ -136,3 +137,23 @@ ite_sio_write(dev, ITE_CONFIG_REG_WDT_TIMEOUT_MSB, 0x00); pnp_exit_conf_state(dev); } + +/* + * Set AC resume to be up to the Southbridge + * pass EC_DEV + */ +void ite_ac_resume_southbridge(pnp_devfn_t dev) +{ + u8 tmp; + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + tmp = pnp_read_config(dev, ITE_CONFIG_REG_APC_PME_CTL2); + /* + * Set both + * 6: Gate Extra PWRON# Pulse + * 5: PSON# state when 3VSB switched to on + */ + tmp |= 0x60; + pnp_write_config(dev, ITE_CONFIG_REG_APC_PME_CTL2, tmp); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/ite/common/ite.h b/src/superio/ite/common/ite.h index 3e9b5028..19ade4b 100644 --- a/src/superio/ite/common/ite.h +++ b/src/superio/ite/common/ite.h @@ -17,6 +17,7 @@ void ite_enable_3vsbsw(pnp_devfn_t dev); void ite_delay_pwrgd3(pnp_devfn_t dev); void ite_kill_watchdog(pnp_devfn_t dev); +void ite_ac_resume_southbridge(pnp_devfn_t dev); void pnp_enter_conf_state(pnp_devfn_t dev); void pnp_exit_conf_state(pnp_devfn_t dev); diff --git a/src/superio/ite/it8772f/Kconfig b/src/superio/ite/it8772f/Kconfig index 194c736..3137cf0 100644 --- a/src/superio/ite/it8772f/Kconfig +++ b/src/superio/ite/it8772f/Kconfig @@ -3,3 +3,9 @@ config SUPERIO_ITE_IT8772F bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_ENV_CTRL + select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG + select SUPERIO_ITE_ENV_CTRL_8BIT_PWM + select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + select SUPERIO_ITE_ENV_CTRL_NO_FULLSPEED_SETTING + select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 diff --git a/src/superio/ite/it8772f/chip.h b/src/superio/ite/it8772f/chip.h index eb3ccd2..1169b4b 100644 --- a/src/superio/ite/it8772f/chip.h +++ b/src/superio/ite/it8772f/chip.h @@ -3,12 +3,11 @@ #ifndef SUPERIO_ITE_IT8772F_CHIP_H #define SUPERIO_ITE_IT8772F_CHIP_H -#include <device/device.h> -#include <types.h> - -#include "it8772f.h" +#include <superio/ite/common/env_ctrl_chip.h> struct superio_ite_it8772f_config { + struct ite_ec_config ec; + /* GPIO SimpleIO register values via devicetree.cb */ u8 gpio_set1; u8 gpio_set2; @@ -18,31 +17,6 @@ u8 gpio_set6; bool skip_keyboard; - - /* - * Enable external temperature sensor to use PECI GetTemp() - * command and store in register TMPIN 1, 2, or 3. - */ - u8 peci_tmpin; - - /* - * Enable thermal mode on tmpinx. - */ - enum thermal_mode tmpin1_mode; - enum thermal_mode tmpin2_mode; - - /* - * Enable a FAN for software control. - */ - bool fan1_enable; - bool fan2_enable; - bool fan3_enable; - - /* - * Default FAN speed - */ - u8 fan2_speed; - u8 fan3_speed; }; #endif /* SUPERIO_ITE_IT8772F_CHIP_H */ diff --git a/src/superio/ite/it8772f/early_init.c b/src/superio/ite/it8772f/early_init.c index e41b206..efbb035 100644 --- a/src/superio/ite/it8772f/early_init.c +++ b/src/superio/ite/it8772f/early_init.c @@ -5,10 +5,13 @@ #include <device/pnp_ops.h> #include "it8772f.h" +#include "../common/ite.h" + +#define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ /* NOTICE: This file is deprecated, use ite/common instead */ -void it8772f_enter_conf(pnp_devfn_t dev) +static void it8772f_enter_conf(pnp_devfn_t dev) { u16 port = dev >> 8; @@ -18,27 +21,18 @@ outb((port == 0x4e) ? 0xaa : 0x55, port); } -void it8772f_exit_conf(pnp_devfn_t dev) +static void it8772f_exit_conf(pnp_devfn_t dev) { pnp_write_config(dev, IT8772F_CONFIG_REG_CC, 0x02); } -/* Set AC resume to be up to the Southbridge */ -void it8772f_ac_resume_southbridge(pnp_devfn_t dev) -{ - it8772f_enter_conf(dev); - pnp_write_config(dev, IT8772F_CONFIG_REG_LDN, IT8772F_EC); - pnp_write_config(dev, PNP_IDX_MSC4, 0x60); - it8772f_exit_conf(dev); -} - /* Configure a set of GPIOs */ void it8772f_gpio_setup(pnp_devfn_t dev, int set, u8 select, u8 polarity, u8 pullup, u8 output, u8 enable) { set--; /* Set 1 is offset 0 */ it8772f_enter_conf(dev); - pnp_write_config(dev, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); + pnp_set_logical_device(dev); if (set < 5) { pnp_write_config(dev, GPIO_REG_SELECT(set), select); pnp_write_config(dev, GPIO_REG_ENABLE(set), enable); @@ -55,7 +49,7 @@ { set--; /* Set 1 is offset 0 */ it8772f_enter_conf(dev); - pnp_write_config(dev, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); + pnp_set_logical_device(dev); if (set < 5) { pnp_write_config(dev, IT8772F_GPIO_LED_BLINK1_PINMAP, led_pin_map); pnp_write_config(dev, IT8772F_GPIO_LED_BLINK1_CONTROL, led_freq); diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h index 38cfe3b..4df21c5 100644 --- a/src/superio/ite/it8772f/it8772f.h +++ b/src/superio/ite/it8772f/it8772f.h @@ -3,13 +3,6 @@ #ifndef SUPERIO_ITE_IT8772F_H #define SUPERIO_ITE_IT8772F_H -/* Supported thermal mode on TMPINx */ -enum thermal_mode { - THERMAL_MODE_DISABLED = 0, - THERMAL_DIODE, - THERMAL_RESISTOR, -}; - #define IT8772F_FDC 0x00 /* Floppy disk controller */ #define IT8772F_SP1 0x01 /* Com1 */ #define IT8772F_EC 0x04 /* Environment controller */ @@ -18,71 +11,6 @@ #define IT8772F_GPIO 0x07 /* GPIO */ #define IT8772F_IR 0x0a /* Consumer IR */ -/* Environmental Controller interface */ -#define IT8772F_CONFIGURATION 0x00 -#define IT8772F_INTERFACE_SELECT 0x0a -#define IT8772F_INTERFACE_PSEUDO_EOC (1 << 7) -#define IT8772F_INTERFACE_SMB_ENABLE (1 << 6) -#define IT8772F_INTERFACE_SEL_DISABLE (0 << 4) -#define IT8772F_INTERFACE_SEL_SST_SLAVE (1 << 4) -#define IT8772F_INTERFACE_SEL_PECI (2 << 4) -#define IT8772F_INTERFACE_SEL_SST_HOST (3 << 4) -#define IT8772F_INTERFACE_CLOCK_32MHZ (0 << 3) -#define IT8772F_INTERFACE_CLOCK_24MHZ (1 << 3) -#define IT8772F_INTERFACE_SPEED_TOLERANCE (1 << 2) -#define IT8772F_INTERFACE_PECI_AWFCS (1 << 0) -#define IT8772F_FAN_TAC2_READ 0x0e -#define IT8772F_FAN_TAC3_READ 0x0f -#define IT8772F_FAN_MAIN_CTL 0x13 -#define IT8772F_FAN_MAIN_CTL_TAC_SMART(x) (1 << ((x)-1)) -#define IT8772F_FAN_MAIN_CTL_TAC_EN(x) (1 << ((x)+3)) -#define IT8772F_FAN_CTL_MODE 0x14 -#define IT8772F_FAN_CTL_ON(x) (1 << ((x)-1)) -#define IT8772F_FAN_PWM_MIN_DUTY (1 << 3) -#define IT8772F_FAN_PWM_CLOCK_48MHZ (0 << 4) -#define IT8772F_FAN_PWM_CLOCK_24MHZ (1 << 4) -#define IT8772F_FAN_PWM_CLOCK_8MHZ (3 << 4) -#define IT8772F_FAN_PWM_CLOCK_6MHZ (4 << 4) -#define IT8772F_FAN_PWM_CLOCK_3MHZ (5 << 4) -#define IT8772F_FAN_PWM_CLOCK_1_5MHZ (6 << 4) -#define IT8772F_FAN_PWM_CLOCK_51KHZ (7 << 4) -#define IT8772F_FAN_CTL_POLARITY_LOW (0 << 7) -#define IT8772F_FAN_CTL_POLARITY_HIGH (1 << 7) -#define IT8772F_FAN_CTL2_PWM_MODE 0x16 -#define IT8772F_FAN_CTL3_PWM_MODE 0x17 -#define IT8772F_FAN_CTL_PWM_MODE_SOFTWARE (0 << 7) -#define IT8772F_FAN_CTL_PWM_MODE_AUTOMATIC (1 << 7) -#define IT8772F_ADC_TEMP_CHANNEL_ENABLE 0x51 -#define IT8772F_FAN_CTL2_PWM_START 0x6b -#define IT8772F_FAN_CTL2_AUTO_MODE 0x6c -#define IT8772F_FAN_CTL3_PWM_START 0x73 -#define IT8772F_FAN_CTL3_AUTO_MODE 0x74 -#define IT8772F_FAN_CTL_AUTO_SMOOTHING_DIS (0 << 7) -#define IT8772F_FAN_CTL_AUTO_SMOOTHING_EN (1 << 7) -#define IT8772F_EXTEMP_STATUS 0x88 -#define IT8772F_EXTEMP_STATUS_HOST_BUSY (1 << 0) -#define IT8772F_EXTEMP_ADDRESS 0x89 -#define IT8772F_EXTEMP_WRITE_LENGTH 0x8a -#define IT8772F_EXTEMP_READ_LENGTH 0x8b -#define IT8772F_EXTEMP_COMMAND 0x8c -#define IT8772F_EXTEMP_WRITE_DATA_2 0x8d -#define IT8772F_EXTEMP_CONTROL 0x8e -#define IT8772F_EXTEMP_CONTROL_AUTO_32HZ (0 << 6) -#define IT8772F_EXTEMP_CONTROL_AUTO_16HZ (1 << 6) -#define IT8772F_EXTEMP_CONTROL_AUTO_8HZ (2 << 6) -#define IT8772F_EXTEMP_CONTROL_AUTO_4HZ (3 << 6) -#define IT8772F_EXTEMP_CONTROL_AUTO_START (1 << 5) -#define IT8772F_EXTEMP_CONTROL_AUTO_ABORT (1 << 4) -#define IT8772F_EXTEMP_CONTROL_AUTO_TWO_DOMAIN (1 << 3) -#define IT8772F_EXTEMP_CONTROL_CONTENTION (1 << 2) -#define IT8772F_EXTEMP_CONTROL_SST_IDLE_HIGH (1 << 1) -#define IT8772F_EXTEMP_CONTROL_START (1 << 0) - -/* Standard PECI GetTemp */ -#define PECI_CLIENT_ADDRESS 0x30 -#define PECI_GETTEMP_COMMAND 0x01 -#define PECI_GETTEMP_WRITE_LENGTH 0x01 -#define PECI_GETTEMP_READ_LENGTH 0x02 /* GPIO interface */ #define IT8772F_GPIO_LED_BLINK1_PINMAP 0xf8 @@ -115,17 +43,9 @@ #include <device/pnp_type.h> #include <stdint.h> -void it8772f_ac_resume_southbridge(pnp_devfn_t dev); void it8772f_gpio_setup(pnp_devfn_t dev, int set, u8 select, u8 polarity, u8 pullup, u8 output, u8 enable); -/* FIXME: should be static so will be removed later.. */ -/* Global configuration registers. */ -#define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8772F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ - -void it8772f_enter_conf(pnp_devfn_t dev); -void it8772f_exit_conf(pnp_devfn_t dev); void it8772f_gpio_led(pnp_devfn_t dev, int set, u8 select, u8 polarity, u8 pullup, u8 output, u8 enable, u8 led_pin_map, u8 led_freq); diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index 1771368..268df0a 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -4,6 +4,7 @@ #include <device/pnp.h> #include <console/console.h> #include <pc80/keyboard.h> +#include <superio/ite/common/env_ctrl.h> #include <arch/io.h> #include <delay.h> #include <superio/conf_mode.h> @@ -12,155 +13,6 @@ #include "chip.h" /* FIXME */ #include "it8772f.h" -/* FIXME: see if the common ITE environment controller code can be used here */ - -static void it8772f_extemp_force_idle_status(struct resource *res) -{ - u8 reg; - int retries = 10; - - /* Wait up to 10ms for non-busy state. */ - while (retries > 0) { - reg = pnp_read_hwm5_index(res->base, IT8772F_EXTEMP_STATUS); - - if ((reg & IT8772F_EXTEMP_STATUS_HOST_BUSY) == 0x0) - break; - - retries--; - - mdelay(1); - } - - if (retries == 0 && (reg & IT8772F_EXTEMP_STATUS_HOST_BUSY) == 0x1) { - /* - * SIO is busy due to unfinished peci transaction. - * Re-configure Register 0x8E to terminate processes. - */ - pnp_write_hwm5_index(res->base, IT8772F_EXTEMP_CONTROL, - IT8772F_EXTEMP_CONTROL_AUTO_4HZ | - IT8772F_EXTEMP_CONTROL_AUTO_START); - } -} - -/* - * Setup External Temperature to read via PECI into TMPINx register - */ -static void it8772f_enable_peci(struct resource *res, int tmpin) -{ - if (tmpin < 1 || tmpin > 3) - return; - - /* Enable PECI interface */ - pnp_write_hwm5_index(res->base, IT8772F_INTERFACE_SELECT, - IT8772F_INTERFACE_SEL_PECI | - IT8772F_INTERFACE_SPEED_TOLERANCE); - - /* Setup External Temperature using PECI GetTemp */ - pnp_write_hwm5_index(res->base, IT8772F_EXTEMP_ADDRESS, - PECI_CLIENT_ADDRESS); - pnp_write_hwm5_index(res->base, IT8772F_EXTEMP_COMMAND, - PECI_GETTEMP_COMMAND); - pnp_write_hwm5_index(res->base, IT8772F_EXTEMP_WRITE_LENGTH, - PECI_GETTEMP_WRITE_LENGTH); - pnp_write_hwm5_index(res->base, IT8772F_EXTEMP_READ_LENGTH, - PECI_GETTEMP_READ_LENGTH); - pnp_write_hwm5_index(res->base, IT8772F_EXTEMP_CONTROL, - IT8772F_EXTEMP_CONTROL_AUTO_4HZ | - IT8772F_EXTEMP_CONTROL_AUTO_START); - - /* External Temperature reported in TMPINx register */ - pnp_write_hwm5_index(res->base, IT8772F_ADC_TEMP_CHANNEL_ENABLE, - (tmpin & 3) << 6); -} - -/* - * Set up External Temperature to read via thermal diode/resistor - * into TMPINx register - */ -static void it8772f_enable_tmpin(struct resource *res, int tmpin, - enum thermal_mode mode) -{ - u8 reg; - - if (tmpin != 1 && tmpin != 2) - return; - - reg = pnp_read_hwm5_index(res->base, IT8772F_ADC_TEMP_CHANNEL_ENABLE); - - switch (mode) { - case THERMAL_DIODE: - /* Thermal Diode Mode */ - pnp_write_hwm5_index(res->base, IT8772F_ADC_TEMP_CHANNEL_ENABLE, - reg | tmpin); - break; - case THERMAL_RESISTOR: - /* Thermal Resistor Mode */ - pnp_write_hwm5_index(res->base, IT8772F_ADC_TEMP_CHANNEL_ENABLE, - reg | (tmpin << 3)); - break; - default: - printk(BIOS_ERR, "Unsupported thermal mode 0x%x on TMPIN%d\n", - mode, tmpin); - return; - } - - reg = pnp_read_hwm5_index(res->base, IT8772F_CONFIGURATION); - - /* Enable the startup of monitoring operation */ - pnp_write_hwm5_index(res->base, IT8772F_CONFIGURATION, reg | 0x01); -} - -/* - * Setup a FAN PWM interface for software control - */ -static void it8772f_enable_fan(struct resource *res, int fan, u8 fan_speed) -{ - u8 reg; - - if (fan < 1 || fan > 3) - return; - - /* Enable 6MHz (23.43kHz PWM) active high output */ - reg = pnp_read_hwm5_index(res->base, IT8772F_FAN_CTL_MODE); - reg |= IT8772F_FAN_CTL_ON(fan) | - IT8772F_FAN_PWM_CLOCK_6MHZ | - IT8772F_FAN_CTL_POLARITY_HIGH; - pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL_MODE, reg); - - /* Enable output in smart mode */ - reg = pnp_read_hwm5_index(res->base, IT8772F_FAN_MAIN_CTL); - reg |= IT8772F_FAN_MAIN_CTL_TAC_SMART(fan); - reg |= IT8772F_FAN_MAIN_CTL_TAC_EN(fan); - pnp_write_hwm5_index(res->base, IT8772F_FAN_MAIN_CTL, reg); - - switch (fan) { - case 2: - /* Enable software operation */ - pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL2_PWM_MODE, - IT8772F_FAN_CTL_PWM_MODE_SOFTWARE); - /* Disable Smoothing */ - pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL2_AUTO_MODE, - IT8772F_FAN_CTL_AUTO_SMOOTHING_DIS); - /* Set a default fan speed */ - if (fan_speed) - pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL2_PWM_START, - fan_speed); - break; - case 3: - /* Enable software operation */ - pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL3_PWM_MODE, - IT8772F_FAN_CTL_PWM_MODE_SOFTWARE); - /* Disable Smoothing */ - pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL3_AUTO_MODE, - IT8772F_FAN_CTL_AUTO_SMOOTHING_DIS); - /* Set a default fan speed */ - if (fan_speed) - pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL3_PWM_START, - fan_speed); - break; - } -} - static void it8772f_init(struct device *dev) { struct superio_ite_it8772f_config *conf = dev->chip_info; @@ -172,34 +24,9 @@ switch (dev->path.pnp.device) { case IT8772F_EC: res = probe_resource(dev, PNP_IDX_IO0); - if (!res) + if (!conf || !res) break; - - /* Enable PECI if configured */ - it8772f_enable_peci(res, conf->peci_tmpin); - - /* Enable HWM if configured */ - if (conf->tmpin1_mode != THERMAL_MODE_DISABLED) - it8772f_enable_tmpin(res, 1, conf->tmpin1_mode); - if (conf->tmpin2_mode != THERMAL_MODE_DISABLED) - it8772f_enable_tmpin(res, 2, conf->tmpin2_mode); - - /* Enable FANx if configured */ - if (conf->fan1_enable) - it8772f_enable_fan(res, 1, 0); - if (conf->fan2_enable) - it8772f_enable_fan(res, 2, - conf->fan2_speed ? conf->fan2_speed : 0x80); - if (conf->fan3_enable) - it8772f_enable_fan(res, 3, - conf->fan3_speed ? conf->fan3_speed : 0x80); - - /* - * System may get wrong temperature data when SIO is in - * busy state. Therefore, check the status and terminate - * processes if needed. - */ - it8772f_extemp_force_idle_status(res); + ite_ec_init(res->base, &conf->ec); break; case IT8772F_GPIO: /* Set GPIO output levels */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81310?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4d9d5460628e444dc20f620179b39c90dbc28c6 Gerrit-Change-Number: 81310 Gerrit-PatchSet: 8 Gerrit-Owner: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: MrChromebox <mrchromebox(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[main]: soc/amd/glinda : Add support for A0 and B0 steppings
by Anand Vaikar (Code Review) 13 Apr '24

13 Apr '24

Anand Vaikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81887?usp=email ) Change subject: soc/amd/glinda : Add support for A0 and B0 steppings ...................................................................... soc/amd/glinda : Add support for A0 and B0 steppings Update the A0 and B0 stepping IDs in CPU table Change-Id: I0072f25f981ac7d5df2522594c8788bfabcbf24c Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> --- M src/soc/amd/glinda/cpu.c M src/soc/amd/glinda/include/soc/cpu.h 2 files changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/81887/1 diff --git a/src/soc/amd/glinda/cpu.c b/src/soc/amd/glinda/cpu.c index 06e62c5..a716127 100644 --- a/src/soc/amd/glinda/cpu.c +++ b/src/soc/amd/glinda/cpu.c @@ -25,7 +25,8 @@ }; static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, GLINDA_A0_CPUID, CPUID_ALL_STEPPINGS_MASK }, /* TODO: Update for Glinda */ + { X86_VENDOR_AMD, GLINDA_A0_CPUID, CPUID_ALL_STEPPINGS_MASK }, + { X86_VENDOR_AMD, GLINDA_B0_CPUID, CPUID_ALL_STEPPINGS_MASK }, CPU_TABLE_END }; diff --git a/src/soc/amd/glinda/include/soc/cpu.h b/src/soc/amd/glinda/include/soc/cpu.h index e7207da..fa9e56c 100644 --- a/src/soc/amd/glinda/include/soc/cpu.h +++ b/src/soc/amd/glinda/include/soc/cpu.h @@ -3,6 +3,6 @@ #ifndef AMD_GLINDA_CPU_H #define AMD_GLINDA_CPU_H -#define GLINDA_A0_CPUID CPUID_FROM_FMS(0x17, 0xa0, 0) /* TODO: Update for Glinda */ - +#define GLINDA_A0_CPUID CPUID_FROM_FMS(0x1A, 0x20, 0xA0) +#define GLINDA_B0_CPUID CPUID_FROM_FMS(0x1A, 0x24, 0xB0) #endif /* AMD_GLINDA_CPU_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81887?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0072f25f981ac7d5df2522594c8788bfabcbf24c Gerrit-Change-Number: 81887 Gerrit-PatchSet: 1 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: arch/x86: Prevent .text/.init overlap with older linkers
by Subrata Banik (Code Review) 13 Apr '24

13 Apr '24

Attention is currently required from: Arthur Heymans, Jon Murphy, Jérémy Compostella, Nico Huber. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81886?usp=email ) Change subject: arch/x86: Prevent .text/.init overlap with older linkers ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81886/comment/e1e87d2a_2554c577 : PS2, Line 11: Default is 1024 bytes (1 KiB) > Ok, let's wait if others have some input on this. I didn't really look > into it, just notice the similarity to the other change and don't know > what would be a good solution. for sure, we have discussed the potential W/A or solution by this mean (using a dedicated Kconfig) at https://review.coreboot.org/c/coreboot/+/80337/comments/92c6aaf1_04b9a05b (where Arthur suggested to use `Add a Kconfig for a workaround that adds a fixed number to PROGRAM_SZ that makes all your builds succeed?`) https://review.coreboot.org/c/coreboot/+/81886/comment/1fb79509_c211461c : PS2, Line 11: (binutils 2.3x) > There's always a chance that a different project can't be built with the > same toolchain. That's why coreboot has its reference toolchain, because > toolchains aren't always compatible. In the light of this, it seems best > if you'd use separate toolchains for coreboot and edk2. Otherwise, you > can always hit issues like this. valid point. we made our learning the hard way. for us it's easy to maintain coreboot sdk for building all projects including EDK2 but it looks like the latest toolchain is not supported in 2022/2023 Intel projects. -- To view, visit https://review.coreboot.org/c/coreboot/+/81886?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I019bf6896d84b2a84dff6f22323f0f446c0740b5 Gerrit-Change-Number: 81886 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 13 Apr 2024 12:52:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: nb/intel/gm45: Fill in memory info
by Angel Pons (Code Review) 13 Apr '24

13 Apr '24

Attention is currently required from: Jean Lucas, Nicholas Chin. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81861?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: nb/intel/gm45: Fill in memory info ...................................................................... Patch Set 1: (2 comments) File src/northbridge/intel/gm45/raminit_meminfo.c: https://review.coreboot.org/c/coreboot/+/81861/comment/0540bcd7_2b6d9f11 : PS1, Line 61: FOR_EACH_POPULATED_RANK This is wrong, dual-rank DIMMs end up with two entries https://review.coreboot.org/c/coreboot/+/81861/comment/c9b1b780_0fe62767 : PS1, Line 83: mem_info->number_of_devices = 2; > Is this like the number of slots? Just curious. Yes, that should be the number of DIMMs -- To view, visit https://review.coreboot.org/c/coreboot/+/81861?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92060ce05bdf0ca617a3383a2db1fdbd43df6fe4 Gerrit-Change-Number: 81861 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jean Lucas Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jean Lucas Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sat, 13 Apr 2024 12:41:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: util/intelp2m: Avoid adding blank line after '{'
by Nicholas Sudsgaard (Code Review) 13 Apr '24

13 Apr '24

Attention is currently required from: Elyes Haouas, Maxim. Nicholas Sudsgaard has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81547?usp=email ) Change subject: util/intelp2m: Avoid adding blank line after '{' ...................................................................... Patch Set 1: (1 comment) File util/intelp2m/parser/parser.go: https://review.coreboot.org/c/coreboot/+/81547/comment/931c9fec_d7c74b4e : PS1, Line 53: if !strings.Contains(info.function, "GPIO Community 0") { > If I understand correctly, this is about removing blank line after `static const struct pad_config g […] Sorry about that, maybe I should have been more clear that this code was just a suggestion and had not been tested (CB:81484). Although, I gave a +1 as I assumed Elyes had tested this and found it to work. -- To view, visit https://review.coreboot.org/c/coreboot/+/81547?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8105734b1b4776d0eb01b13c80e21e130719fe83 Gerrit-Change-Number: 81547 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 13 Apr 2024 12:27:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maxim <max.senia.poliak(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: util/intelp2m: Avoid adding blank line after '{'
by Nicholas Sudsgaard (Code Review) 13 Apr '24

13 Apr '24

Attention is currently required from: Elyes Haouas. Nicholas Sudsgaard has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81547?usp=email ) Change subject: util/intelp2m: Avoid adding blank line after '{' ...................................................................... Patch Set 1: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/81547?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8105734b1b4776d0eb01b13c80e21e130719fe83 Gerrit-Change-Number: 81547 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 13 Apr 2024 12:20:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: arch/x86: Prevent .text/.init overlap with older linkers
by Nico Huber (Code Review) 13 Apr '24

13 Apr '24

Attention is currently required from: Arthur Heymans, Jon Murphy, Jérémy Compostella, Subrata Banik. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81886?usp=email ) Change subject: arch/x86: Prevent .text/.init overlap with older linkers ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81886/comment/c6352b6c_592ed0d4 : PS2, Line 11: (binutils 2.3x) > > > Are you sure this is used with the main branch? I was told ChromeOS […] There's always a chance that a different project can't be built with the same toolchain. That's why coreboot has its reference toolchain, because toolchains aren't always compatible. In the light of this, it seems best if you'd use separate toolchains for coreboot and edk2. Otherwise, you can always hit issues like this. https://review.coreboot.org/c/coreboot/+/81886/comment/1d08b7c1_dd608f2c : PS2, Line 11: Default is 1024 bytes (1 KiB) > > There was a comment on another change (CB:81678) stating that […] Ok, let's wait if others have some input on this. I didn't really look into it, just notice the similarity to the other change and don't know what would be a good solution. -- To view, visit https://review.coreboot.org/c/coreboot/+/81886?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I019bf6896d84b2a84dff6f22323f0f446c0740b5 Gerrit-Change-Number: 81886 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 13 Apr 2024 12:12:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: intel/alderlake: Add helper functions for Power Management
by Nico Huber (Code Review) 13 Apr '24

13 Apr '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Nick Vaccaro, Sean Rhodes, Subrata Banik. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81638?usp=email ) Change subject: intel/alderlake: Add helper functions for Power Management ...................................................................... Patch Set 4: (5 comments) Patchset: PS4: If the UPDs didn't change, is there a way to write common code? File src/soc/intel/alderlake/chip.h: https://review.coreboot.org/c/coreboot/+/81638/comment/e3a20916_003512bb : PS4, Line 799: }; Why are these declared separately? How should a mainboard dev know where to use them? Should they use them? File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/81638/comment/c00b82e5_00f0dbf5 : PS4, Line 504: default "auto" I assume you are referring to the value in the FSP binary? That's generally unknown because somebody could have set it differently. https://review.coreboot.org/c/coreboot/+/81638/comment/10fb758a_d58c794b : PS4, Line 506: s_cfg->PcieRpAspm[index] = rp_cfg->pcie_rp_aspm; These usually aren't compatible, because coreboot values are off-by-1 to allow the default opt-out. https://review.coreboot.org/c/coreboot/+/81638/comment/a3013a28_f301341f : PS4, Line 517: s_cfg->PcieRpL1Substates[index] = rp_cfg->PcieRpL1Substates; Same here. -- To view, visit https://review.coreboot.org/c/coreboot/+/81638?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9db18859f9a04ad4b7c0c3f7992b09e0f9484a81 Gerrit-Change-Number: 81638 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Sat, 13 Apr 2024 11:52:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: arch/x86: Prevent .text/.init overlap with older linkers
by Subrata Banik (Code Review) 13 Apr '24

13 Apr '24

Attention is currently required from: Arthur Heymans, Jon Murphy, Jérémy Compostella, Nico Huber. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81886?usp=email ) Change subject: arch/x86: Prevent .text/.init overlap with older linkers ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81886/comment/35a86e9b_657e4c31 : PS2, Line 11: (binutils 2.3x) > > Are you sure this is used with the main branch? I was told ChromeOS > > always uses the newest toolchain (and hence we have to restrict > > toolchain updates to the releases). binutils was updated to 2.40 > > a year ago. > > we are still using 2.37 version and raised an internal bug https://b.corp.google.com/issues/332445618 to perform an uprev to 2.42 to switch to the new binutil. But as said, the existing EDK2 builds are failing (as Intel FSP/EDK2 code are not supportive of the latest tool chain). in case you don't have access to the chrome bug to share the context. Possibly one year ago we attempted 2.40 migration but since then we are blocked due to Intel EDK2 related build issue. So far we don't have resolution and it blocked the 2.40 migration for us. This time we reached out to EDK2 folks for fixing the issue. let see how it goes. -- To view, visit https://review.coreboot.org/c/coreboot/+/81886?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I019bf6896d84b2a84dff6f22323f0f446c0740b5 Gerrit-Change-Number: 81886 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 13 Apr 2024 11:40:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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