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Change subject: mb/hp: Add Pro 3500 series (Sandy/Ivy Bridge)
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81368/comment/bcd9cae7_31dec9e9 :
PS5, Line 12: All peripherals should work.
: Automatic fan control as well as S3 are working.
: The board was tested to boot Linux and Windows. EHCI debug is untested.
: When using MrChromebox edk2 with secure boot build in, the board will
: hang on each boot for about 20 seconds before continuing.
Should probably prefix these with bullet points, e.g. `* `.
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Change subject: mb/hp: Add Pro 3500 series (Sandy/Ivy Bridge)
......................................................................
Patch Set 5: Code-Review+2
(3 comments)
Patchset:
PS5:
LGTM
File Documentation/mainboard/hp/pro_3500_series_flash.jpg:
PS2:
> I saved the images locally to AVIF and they are now <40kB. […]
Seems ok to me. Even if there'll be somebody who has trouble viewing it, that's
always a risk (there are even browsers that can't display images at all).
If there are no objections, I'll close this soon.
File src/mainboard/hp/pro_3500_series/led.c:
https://review.coreboot.org/c/coreboot/+/81368/comment/2ad4ed51_6646e933 :
PS5, Line 8: // Board has a dual color LED
Nit, it's preferred to use only one comment style (`//` or `/* */`) throughout a file.
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Change subject: superio/ite: Disable 16-bit tacho counters for IT8728F
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
We should probably try to find somebody with a board with this chip to test.
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Change subject: mb/samsung/stumpy: Set initial fan PWM to 30%
......................................................................
mb/samsung/stumpy: Set initial fan PWM to 30%
Recent changes to the ITE 8772F SIO code caused the initial fan PWM
to change from 0 to 50%; set it to 30% to reduce fan noise while
still providing some temp control before the OS/ACPI takes over.
TEST=build/boot stumpy to payload, verify fan noise is negligible.
Change-Id: I287e46202ee1c112d1da63c0d8b7889958e3807e
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81514
Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
---
M src/mainboard/samsung/stumpy/devicetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
Varshit Pandya: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb
index 853e519..bc24464 100644
--- a/src/mainboard/samsung/stumpy/devicetree.cb
+++ b/src/mainboard/samsung/stumpy/devicetree.cb
@@ -91,6 +91,7 @@
register "TMPIN3.mode" = "THERMAL_PECI"
# Enable FAN3
register "FAN3.mode" = "FAN_SMART_SOFTWARE"
+ register "FAN3.smart.pwm_start" = "30"
device pnp 2e.0 off end # FDC
device pnp 2e.1 on # Serial Port 1
--
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Change subject: mb/samsung/stumpy: Set initial fan PWM to 30%
......................................................................
Patch Set 3: Code-Review+2
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Change subject: mb/google/beltino: Set initial fan PWM to 30%
......................................................................
mb/google/beltino: Set initial fan PWM to 30%
Recent changes to the ITE 8772F SIO code caused the initial fan PWM
to change from 0 to 50%; set it to 30% to reduce fan noise while
still providing some temp control before the OS/ACPI takes over.
TEST=build/boot google/beltino to payload, verify fan noise is
negligible.
Change-Id: I0177235d73e051f02b5333cf1d735556382b919f
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81513
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/beltino/devicetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
Varshit Pandya: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb
index d96ee11..9dacd6d 100644
--- a/src/mainboard/google/beltino/devicetree.cb
+++ b/src/mainboard/google/beltino/devicetree.cb
@@ -84,6 +84,7 @@
register "TMPIN3.mode" = "THERMAL_PECI"
# Enable FAN2
register "FAN2.mode" = "FAN_SMART_SOFTWARE"
+ register "FAN2.smart.pwm_start" = "30"
device pnp 2e.0 off end # FDC
device pnp 2e.1 on # Serial Port 1
--
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Change subject: mb/google/beltino: Set initial fan PWM to 30%
......................................................................
Patch Set 2: Code-Review+2
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Change subject: superio/ite: Add function to disable 3VSBSW# signal
......................................................................
superio/ite: Add function to disable 3VSBSW# signal
The 3VSBSW# signal can now also be disabled again which is necessary to
power components down properly in SMM when entering S5. In such cases
the signal will be enabled only in the SMM S3 handler.
Change-Id: I8535176908ec39e9916774135e028cbc7c203474
Signed-off-by: Joel Linn <jl(a)conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81588
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
---
M src/superio/ite/Makefile.mk
M src/superio/ite/common/early_serial.c
M src/superio/ite/common/ite.h
3 files changed, 15 insertions(+), 3 deletions(-)
Approvals:
Angel Pons: Looks good to me, but someone else must approve
Nico Huber: Looks good to me, approved
Matt DeVillier: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/superio/ite/Makefile.mk b/src/superio/ite/Makefile.mk
index b6d0199..d44ade4 100644
--- a/src/superio/ite/Makefile.mk
+++ b/src/superio/ite/Makefile.mk
@@ -7,6 +7,9 @@
## include generic ite environment controller driver
ramstage-$(CONFIG_SUPERIO_ITE_ENV_CTRL) += common/env_ctrl.c
+## include generic ite driver to smm to control S3-relevant functions
+smm-$(CONFIG_SUPERIO_ITE_COMMON_PRE_RAM) += common/early_serial.c
+
subdirs-y += it8528e
subdirs-y += it8613e
subdirs-y += it8623e
diff --git a/src/superio/ite/common/early_serial.c b/src/superio/ite/common/early_serial.c
index 552f110..b8a6ba5 100644
--- a/src/superio/ite/common/early_serial.c
+++ b/src/superio/ite/common/early_serial.c
@@ -75,6 +75,7 @@
*
* LDN 7, reg 0x2a - needed for S3, or memory power will be cut off
* this was documented only in IT8712F_V0.9.2!
+ * Also documented in IT8728F_V0.4.2 and IT8772E_V0.4
*
* Enable 3VSBSW#. (For System Suspend-to-RAM)
* 0: 3VSBSW# will be always inactive.
@@ -85,13 +86,16 @@
* and pass: GPIO_DEV
*/
-void ite_enable_3vsbsw(pnp_devfn_t dev)
+void ite_set_3vsbsw(pnp_devfn_t dev, bool enable)
{
u8 tmp;
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
tmp = pnp_read_config(dev, ITE_CONFIG_REG_MFC);
- tmp |= 0x80;
+ if (enable)
+ tmp |= 0x80;
+ else
+ tmp &= ~0x80;
pnp_write_config(dev, ITE_CONFIG_REG_MFC, tmp);
pnp_exit_conf_state(dev);
}
diff --git a/src/superio/ite/common/ite.h b/src/superio/ite/common/ite.h
index 19ade4b..1a147be 100644
--- a/src/superio/ite/common/ite.h
+++ b/src/superio/ite/common/ite.h
@@ -4,6 +4,7 @@
#define SUPERIO_ITE_COMMON_PRE_RAM_H
#include <device/pnp_type.h>
+#include <stdbool.h>
#include <stdint.h>
#define ITE_UART_CLK_PREDIVIDE_48 0x00 /* default */
@@ -14,11 +15,15 @@
/* Some boards need to init wdt+gpio's very early */
void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value);
-void ite_enable_3vsbsw(pnp_devfn_t dev);
+void ite_set_3vsbsw(pnp_devfn_t dev, bool enable);
void ite_delay_pwrgd3(pnp_devfn_t dev);
void ite_kill_watchdog(pnp_devfn_t dev);
void ite_ac_resume_southbridge(pnp_devfn_t dev);
+/* Alias for backwards compatibility */
+static inline void ite_enable_3vsbsw(pnp_devfn_t dev) { ite_set_3vsbsw(dev, true); }
+static inline void ite_disable_3vsbsw(pnp_devfn_t dev) { ite_set_3vsbsw(dev, false); }
+
void pnp_enter_conf_state(pnp_devfn_t dev);
void pnp_exit_conf_state(pnp_devfn_t dev);
--
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