coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

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[XL] Change in coreboot[main]: soc/sifive/fu740: Add FU740 SOC
by Philipp Hug (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Maximilian Brune. Philipp Hug has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76689?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/sifive/fu740: Add FU740 SOC ...................................................................... Patch Set 10: Code-Review+1 (6 comments) File src/soc/sifive/fu740/Kconfig: https://review.coreboot.org/c/coreboot/+/76689/comment/724b2095_e03d2576 : PS10, Line 28: # working HART uses U7 core RISCV_WORKING_HARTID is set to 0, which is S7? https://review.coreboot.org/c/coreboot/+/76689/comment/4aea5acd_9c9dd8bd : PS10, Line 47: default 0 # use S7 core as default hart deliberate use of S7 for coreboot? File src/soc/sifive/fu740/clint.c: https://review.coreboot.org/c/coreboot/+/76689/comment/42655258_d666286f : PS10, Line 17: write32((void *)(FU740_CLINT + 4 * (uintptr_t)hartid), !!val); use write32p? File src/soc/sifive/fu740/gpio.c: https://review.coreboot.org/c/coreboot/+/76689/comment/9e1a6cd4_dae2dfdf : PS10, Line 33: uint32_t output_val = read32((void *)SIFIVE_GPIO_OUTPUT_VAL); use read32p/write32p? File src/soc/sifive/fu740/memlayout.ld: https://review.coreboot.org/c/coreboot/+/76689/comment/b6c036f9_f0dcc5ea : PS10, Line 22: //REGION(opensbi, FU740_DRAM, 256K, 4K) comment not needed? File src/soc/sifive/fu740/spi.c: https://review.coreboot.org/c/coreboot/+/76689/comment/01d4332c_98ba2162 : PS10, Line 186: //sckmode.raw_bits = 0; why is this code commented here? delete it? -- To view, visit https://review.coreboot.org/c/coreboot/+/76689?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4a8fe02ef0adcb939aa65377a35874715c5ee58a Gerrit-Change-Number: 76689 Gerrit-PatchSet: 10 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Jan Samek <jan.samek(a)siemens.com> Gerrit-CC: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Fri, 01 Mar 2024 11:40:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/intel/fsp: Work around multi socket Xeon-SP pipe init bug
by Arthur Heymans (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Andrey Petrov, Chen, Gang C, Christian Walter, Felix Singer, Jincheng Li, Johnny Lin, Jérémy Compostella, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, Ray Ni, Ronak Kanabar, Shuo Liu, Tim Chu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80579?usp=email ) Change subject: drivers/intel/fsp: Work around multi socket Xeon-SP pipe init bug ...................................................................... Patch Set 4: (2 comments) File src/arch/x86/car.ld: https://review.coreboot.org/c/coreboot/+/80579/comment/86e5a202_df8656c4 : PS4, Line 15: > To be simple, maybe we could use REGION(fspm_heap ...) here and discard the .car. […] Done https://review.coreboot.org/c/coreboot/+/80579/comment/39fe7450_469a4c69 : PS4, Line 118: _fspm_heap = .; > Can't this be simplified using `REGION(fspm_heap, . […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80579?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I38a4f4b7470556e528a1672044c31f8bd92887d4 Gerrit-Change-Number: 80579 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ray Ni <ray.ni(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Ray Ni <ray.ni(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 01 Mar 2024 10:45:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: arch/x86/car.ld: Move FSP RC heap region into car_region
by Arthur Heymans (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Jérémy Compostella. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80810?usp=email ) Change subject: arch/x86/car.ld: Move FSP RC heap region into car_region ...................................................................... arch/x86/car.ld: Move FSP RC heap region into car_region This fixes linker warnings about the dot moving backwards. Change-Id: I44b127f8cdf5aa00e9f85a26f5abc290d0dfc11b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/car.ld 1 file changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/80810/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 8e1af15..dc46f47 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -8,7 +8,9 @@ . = CONFIG_DCACHE_RAM_BASE; .car.data . (NOLOAD) : { _car_region_start = . ; - . += CONFIG_FSP_M_RC_HEAP_SIZE; +#if CONFIG_FSP_M_RC_HEAP_SIZE > 0 + REGION(fspm_rc_heap, ., CONFIG_FSP_M_RC_HEAP_SIZE, 16) +#endif #if CONFIG(FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND) REGION(fspm_heap, ., CONFIG_FSP_TEMP_RAM_SIZE, 16) #endif @@ -109,11 +111,6 @@ _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start) - CONFIG_FSP_T_RESERVED_SIZE; -. = _car_region_start; -.car.fspm_rc_heap . (NOLOAD) : { - . += CONFIG_FSP_M_RC_HEAP_SIZE; -} - . = _car_region_end; .car.mrc_var . (NOLOAD) : { . += CONFIG_DCACHE_RAM_MRC_VAR_SIZE; -- To view, visit https://review.coreboot.org/c/coreboot/+/80810?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44b127f8cdf5aa00e9f85a26f5abc290d0dfc11b Gerrit-Change-Number: 80810 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: drivers/intel/fsp: Work around multi socket Xeon-SP pipe init bug
by Arthur Heymans (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Chen, Gang C, Christian Walter, Felix Singer, Jincheng Li, Johnny Lin, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, Ray Ni, Ronak Kanabar, Tim Chu. Hello Andrey Petrov, Chen, Gang C, Christian Walter, Felix Singer, Jincheng Li, Johnny Lin, Jérémy Compostella, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, Ray Ni, Ronak Kanabar, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80579?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Code-Review+1 by Felix Singer, Code-Review+1 by Nico Huber, Code-Review+1 by Paul Menzel, Verified+1 by build bot (Jenkins) Change subject: drivers/intel/fsp: Work around multi socket Xeon-SP pipe init bug ...................................................................... drivers/intel/fsp: Work around multi socket Xeon-SP pipe init bug Starting with Intel CPX there is a bug in the reference code during the Pipe init. This code synchronises the CAR between sockets in FSP-M. This code implicitly assumes that the top of FSP heap is FspStackBase + FspStackSize and the bottom is the bottom of CAR. Work around this issue by making that implicit assumption done in FSP explicit in the coreboot linker script and allocation. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I38a4f4b7470556e528a1672044c31f8bd92887d4 --- M src/arch/x86/car.ld M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/memory_init.c M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/spr/Kconfig 5 files changed, 26 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/80579/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/80579?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I38a4f4b7470556e528a1672044c31f8bd92887d4 Gerrit-Change-Number: 80579 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ray Ni <ray.ni(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Ray Ni <ray.ni(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: mb/emulation/qemu-riscv: Change to -bios option
by Philipp Hug (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Arthur Heymans, Maximilian Brune. Philipp Hug has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80746?usp=email ) Change subject: mb/emulation/qemu-riscv: Change to -bios option ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: can you also add the -pflash parameter to the "make qemu" target? -- To view, visit https://review.coreboot.org/c/coreboot/+/80746?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d Gerrit-Change-Number: 80746 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 01 Mar 2024 10:32:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/tigerlake: Add IRQ mapping for PEG PCI-E ports
by Arthur Heymans (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Alicja Michalska, Nick Vaccaro. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80848?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/tigerlake: Add IRQ mapping for PEG PCI-E ports ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80848/comment/c75a4076_c74f7f1b : PS1, Line 16: Boot Linux Did you try without MSI ? Otherwise the OS might just not complain even though the IRQ routing is wrong... -- To view, visit https://review.coreboot.org/c/coreboot/+/80848?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If102522efa1a67b362b14d859d9e27a37bad85a4 Gerrit-Change-Number: 80848 Gerrit-PatchSet: 1 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 01 Mar 2024 10:28:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Drop SPI_BASE_ADDRESS from _CRS
by Shuo Liu (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80795?usp=email ) Change subject: soc/intel/xeon_sp: Drop SPI_BASE_ADDRESS from _CRS ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80795/comment/1b31cc7c_1597d468 : PS1, Line 10: hidden the fast_spi driver will generate the _CRS marking the BAR > Usually only the VENDOR/DEVID changes to 0xffffffff when a device is hidden. […] I see. I suppose if fast_spi is hidden, fast_spi driver will not be called at all, and no CRS will be reported. However, my platform is with fast_spi unhidden hence I cannot test to prove. In an unhidden platform, fast_spi's BAR will be relocated by coreboot's resource allocator in low MMIO space as a normal allocation and the uncore _CRS reporting is not needed. Hence I agree on this patch but suggest to update the commit message to fit for the unhidden case. P.S. pci 0000:00:1f.5: reg 0x10: [mem 0x955fd000-0x955fdfff] pci 0000:00:1f.5: reg 0x14: [mem 0x92000000-0x93ffffff] For the hidden case, we can make additional fix if there is a platform with that configuration is used. Your opinion? -- To view, visit https://review.coreboot.org/c/coreboot/+/80795?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I150397a7ac5d60719f327f6ac6480a38fe295c32 Gerrit-Change-Number: 80795 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 01 Mar 2024 10:21:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/emulation/qemu-riscv: Change to -bios option
by Maximilian Brune (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Arthur Heymans, Philipp Hug. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80746?usp=email ) Change subject: mb/emulation/qemu-riscv: Change to -bios option ...................................................................... Patch Set 5: (1 comment) File src/mainboard/emulation/qemu-riscv/cbmem.c: https://review.coreboot.org/c/coreboot/+/80746/comment/b82ee241_2232a03e : PS5, Line 10: return (uintptr_t)_dram + CONFIG_DRAM_SIZE_MB * MiB; > If you rebase CB:36486 on top of upstream main, then I could rebase on top of that and remove the ha […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80746?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d Gerrit-Change-Number: 80746 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 01 Mar 2024 10:16:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Philipp Hug <philipp(a)hug.cx> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: util: add smmstoretool for editing SMMSTORE
by Arthur Heymans (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Filip Lewiński, Michał Kopeć, Sergii Dmytruk. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79080?usp=email ) Change subject: util: add smmstoretool for editing SMMSTORE ...................................................................... Patch Set 8: Code-Review+1 (2 comments) Patchset: PS8: Some suggestion to make it easier to use, by parsing fmap. Good for a follow-up. LGTM File Documentation/util/smmstoretool/index.md: https://review.coreboot.org/c/coreboot/+/79080/comment/a0e39957_66b33fa4 : PS8, Line 114: cbfstool coreboot.rom read -r SMMSTORE -f SMMSTORE : smmstoretool SMMSTORE set -g dasharo -n NetworkBoot -t bool -v true : cbfstool coreboot.rom write -r SMMSTORE -f SMMSTORE Could FMAP support be added to this tool? That would be easy to get working and remove the need for cbfstool. -- To view, visit https://review.coreboot.org/c/coreboot/+/79080?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6c1c06f1d0c39c13b5be76a3070f09b715aca6e0 Gerrit-Change-Number: 79080 Gerrit-PatchSet: 8 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Filip Lewiński Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Filip Lewiński Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Fri, 01 Mar 2024 10:16:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brya/var/dochi: Add wifi sar table
by Morris Hsu (Code Review) 01 Mar '24

01 Mar '24

Morris Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80809?usp=email ) Change subject: mb/google/brya/var/dochi: Add wifi sar table ...................................................................... mb/google/brya/var/dochi: Add wifi sar table Add wifi sar table for dochi BUG=b:326137130 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Change-Id: Iaf90756eb318bef1ffcda9368a976c0ca209a100 Signed-off-by: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/dochi/variant.c 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/80809/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index eb937523..b2a20b0 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -198,6 +198,7 @@ select SOC_INTEL_RAPTORLAKE select DRIVERS_INTEL_ISH select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS + select CHROMEOS_WIFI_SAR if CHROMEOS config BOARD_GOOGLE_FELWINTER select BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/variants/dochi/variant.c b/src/mainboard/google/brya/variants/dochi/variant.c index 4c24347..b8acc26 100644 --- a/src/mainboard/google/brya/variants/dochi/variant.c +++ b/src/mainboard/google/brya/variants/dochi/variant.c @@ -3,9 +3,15 @@ #include <chip.h> #include <fw_config.h> #include <baseboard/variants.h> +#include <sar.h> void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { if (fw_config_probe(FW_CONFIG(FP_MCU, FP_ABSENT))) config->serial_io_gspi_mode[PchSerialIoIndexGSPI1] = PchSerialIoDisabled; } + +const char *get_wifi_sar_cbfs_filename(void) +{ + return "wifi_sar_0.hex"; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/80809?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf90756eb318bef1ffcda9368a976c0ca209a100 Gerrit-Change-Number: 80809 Gerrit-PatchSet: 1 Gerrit-Owner: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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