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Change subject: mb/google/nissa/var/gothrax: Add probe and GPIO config for touchpanel
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/brya/variants/gothrax/gpio.c:
https://review.coreboot.org/c/coreboot/+/80850/comment/46804098_09b97228 :
PS1, Line 83: nontp
> nit: tp_disable?
We plan not to set up these GPP_C0/GPP_C1 without a touch screen.
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Change subject: soc/intel/common: Support NO_SMM on modern SoCs
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Patch Set 16:
(1 comment)
File src/soc/intel/common/block/cpu/smmrelocate.c:
https://review.coreboot.org/c/coreboot/+/70377/comment/b20e503e_8841a14d :
PS14, Line 217: *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
> An alternative is `goto end` actually, I think that's good.
Nvm I got confused. This code for all EM64t101 users
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Change subject: [WIP]soc/intel/xeon_sp: Use common _CRS code generation
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Patch Set 3:
(1 comment)
File src/soc/intel/xeon_sp/spr/soc_acpi.c:
https://review.coreboot.org/c/coreboot/+/80796/comment/a9ecfb98_7c95531b :
PS3, Line 78: /* For stack with CXL device, the PCIe bus resource is BusBase only. */
: if (is_iio_cxl_stack_res(ri))
: acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusBase, 0x0, 1);
I had a very similar patchtrain to this one. CXL stacks are a problem... Should CXL domains devices be added too to the tree?
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Change subject: soc/intel/xeon_sp: Drop SPI_BASE_ADDRESS from _CRS
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Patch Set 2: Code-Review+2
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Change subject: soc/intel/xeon_sp: Encode domain type
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Change subject: soc/intel/xeon_sp/spr: Fix IOAT resources
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Change subject: soc/intel/xeon_sp: Add ACPI names
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Patch Set 2:
(1 comment)
File src/soc/intel/xeon_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/80794/comment/7185ad91_a55e409a :
PS2, Line 144: char *name = xmalloc(ACPI_NAME_BUFFER_SIZE);
This means you leak memory each time acpi_name is called. have a pointer in soc_info or soc_info itself point to?
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Change subject: cpu/x86/smm/smm_module_loader.c: Pass full SMRAM region info to SMM runtime
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Change subject: soc/intel/xeon_sp: Drop SPI_BASE_ADDRESS from _CRS
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Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80795/comment/e219b659_82629df2 :
PS1, Line 10: hidden the fast_spi driver will generate the _CRS marking the BAR
> Hidden by HW? or not included in uncore _CRS?
Updated the commit message to clarify.
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Change subject: soc/intel/xeon_sp: Drop SPI_BASE_ADDRESS from _CRS
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