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Change subject: mb/google/nissa/var/gothrax: Add probe and GPIO config for touchpanel
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/brya/variants/gothrax/gpio.c:
https://review.coreboot.org/c/coreboot/+/80850/comment/dfbd1b6c_a002c8eb :
PS1, Line 83: nontp
nit: tp_disable?
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Change subject: cpu/x86/smm/smm_module_loader.c: Pass full SMRAM region info to SMM runtime
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80703/comment/6642453a_c5c96b25 :
PS2, Line 17: integrity of the S3 resume path.
I suppose the default region_overlaps_handler() cannot achieve this at the moment. Maybe this could be put into a separate patch.
https://review.coreboot.org/c/coreboot/+/80703/comment/ab14c4da_87c98fe0 :
PS2, Line 19: The consequences to overwriting the chipset-specific area are undefined.
Could you please specify the definition here for 'chipset-specific' area?
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Change subject: soc/intel/xeon_sp: Encode domain type
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Patch Set 1:
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Patchset:
PS1:
It's good we could move ahead into this direction (compatible for GNR changes). Let us move ahead and achieve to merge with priority.
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Change subject: soc/intel/xeon_sp: Add ACPI names
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Patch Set 1:
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Patchset:
PS1:
It's good we could move ahead into this direction (compatible for GNR changes). Let us move ahead and achieve to merge with priority.
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Change subject: arch/riscv: Add SMP support for exception handler
......................................................................
arch/riscv: Add SMP support for exception handler
Change-Id: Ia1f97b82e329f6358061072f98278cf56b503618
Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org>
---
M src/arch/riscv/payload.c
M src/arch/riscv/trap_util.S
2 files changed, 116 insertions(+), 111 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/68841/6
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Change subject: mb/emulation/qemu-riscv: Change to -bios option
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/emulation/qemu-riscv/cbmem.c:
https://review.coreboot.org/c/coreboot/+/80746/comment/2838cc8e_8bfca49a :
PS5, Line 10: return (uintptr_t)_dram + CONFIG_DRAM_SIZE_MB * MiB;
> Can use probing here instead of hard-coding
If you rebase CB:36486 on top of upstream main, then I could rebase on top of that and remove the hard code stuff.
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Change subject: soc/intel/xeon_sp: Drop SPI_BASE from _CRS
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Patch Set 1:
(1 comment)
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https://review.coreboot.org/c/coreboot/+/80795/comment/938587ff_c71d3b4b :
PS1, Line 10: hidden the fast_spi driver will generate the _CRS marking the BAR
Hidden by HW? or not included in uncore _CRS?
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Change subject: lib/rtc: Add sanity check for time and date
......................................................................
Patch Set 3:
(1 comment)
File src/lib/rtc.c:
https://review.coreboot.org/c/coreboot/+/54913/comment/9bad8249_c94bce73 :
PS3, Line 129: month == 2
> First leap year and we already hit this off-by-one error 😊 […]
Done
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Change subject: mb/google/nissa/var/glassway: Select drivers for gpio-keys and GL9750
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Patch Set 3:
(1 comment)
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https://review.coreboot.org/c/coreboot/+/80766/comment/aa54df2f_1c73c6a2 :
PS2, Line 7: Select drivers for gpio-keys and Genesys Logic GL9750
> please shorten the title
Done
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