coreboot-gerrit March 2024

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[S] Change in coreboot[main]: drivers/vpd: Add vpd_get_feature_level() API
by Subrata Banik (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Gwendal Grignou, Kapil Porwal, Nick Vaccaro, Shelley Chen. Hello Gwendal Grignou, Kapil Porwal, Nick Vaccaro, Shelley Chen, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80805?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+2 by Kapil Porwal, Code-Review-1 by Gwendal Grignou, Verified+1 by build bot (Jenkins) Change subject: drivers/vpd: Add vpd_get_feature_level() API ...................................................................... drivers/vpd: Add vpd_get_feature_level() API This patch introduces the vpd_get_feature_level() API to specifically extract the "feature_level" field from the "feature_device_info" VPD key. This is used to distinguish between Chromebook-Plus and regular Chromebook devices. The previous vpd_get_feature_device_info() API is removed as vpd_get_feature_level() is enough to find VPD and extract the data. Note: The new API decodes the base64-encoded "feature_device_info" VPD data. BUG=b:324107408 TEST=Able to build and boot google/rex0. Change-Id: I76fc220ed792abdfefb0b1a37873b5b828bfdda8 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/vpd/vpd.h M src/drivers/vpd/vpd_device_feature.c 2 files changed, 33 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/80805/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80805?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I76fc220ed792abdfefb0b1a37873b5b828bfdda8 Gerrit-Change-Number: 80805 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: vc/google/chromeos: Implement dynamic ChromeOS boot logo selection
by Subrata Banik (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Gwendal Grignou, Kapil Porwal, Paul Menzel, Paz Zcharya. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80738?usp=email ) Change subject: vc/google/chromeos: Implement dynamic ChromeOS boot logo selection ...................................................................... Patch Set 9: (2 comments) File src/vendorcode/google/chromeos/tpm_factory_config.c: https://review.coreboot.org/c/coreboot/+/80738/comment/787d80f9_556ebc38 : PS9, Line 61: return (factory_config & CHROMEBOOK_PLUS_DEVICE) == CHROMEBOOK_PLUS_DEVICE; > That won't work for future device, since feature_level could be 2. […] Acknowledged https://review.coreboot.org/c/coreboot/+/80738/comment/3afdde8c_5659a689 : PS9, Line 80: */ > Let document further to explain the `CAE` magic since we are not going to put protobuf library in th […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/80738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9bb1e868764738333977bd8c990bea4253c9d37b Gerrit-Change-Number: 80738 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Paz Zcharya <pazz(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paz Zcharya <pazz(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Comment-Date: Fri, 01 Mar 2024 16:06:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: superio/acpi: Add SUPERIO_PNP_NO_DIS to support always active LDNs
by Felix Held (Code Review) 01 Mar '24

01 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80496?usp=email ) Change subject: superio/acpi: Add SUPERIO_PNP_NO_DIS to support always active LDNs ...................................................................... superio/acpi: Add SUPERIO_PNP_NO_DIS to support always active LDNs Some LDNs do not implement the activate bit at all, e.g. ITE GPIO LDNs are an example where the LDN is always active. The pnp_generic.asl can be used to describe the GPIO LDN resources configured by the platform, however the register 0x30 is always 0 for these LDNs, so OS will not claim the reported resource for the GPIO device, because _STA will return inactive LDN. Add SUPERIO_PNP_NO_DIS macro to generate _STA method returning an always active LDN and skip _DIS generation. Define the SUPERIO_PNP_NO_DIS for SIOs which use the pnp_generic.asl preserving the previous states, except the ITE GPIO LDNs. Change-Id: Ieb827fdffe7660b875cba6ca99b0560b4cab66b4 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80496 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/superio/acpi/pnp_generic.asl M src/superio/ite/it8720f/acpi/superio.asl M src/superio/ite/it8721f/acpi/superio.asl M src/superio/ite/it8784e/acpi/superio.asl M src/superio/nuvoton/nct6687d/acpi/superio.asl M src/superio/nuvoton/nct6776/acpi/superio.asl M src/superio/winbond/w83627dhg/acpi/superio.asl 7 files changed, 21 insertions(+), 0 deletions(-) Approvals: Felix Held: Looks good to me, approved build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve diff --git a/src/superio/acpi/pnp_generic.asl b/src/superio/acpi/pnp_generic.asl index a5540e3..ebefd2a 100644 --- a/src/superio/acpi/pnp_generic.asl +++ b/src/superio/acpi/pnp_generic.asl @@ -13,6 +13,7 @@ * chip for this device (required) * SUPERIO_PNP_DDN A string literal that identifies the dos device * name (DDN) of this device (e.g. "COM1", optional) + * SUPERIO_PNP_NO_DIS If defined, the PNP device has no Enable/Disable methods * SUPERIO_PNP_PM_REG Identifier of a 1-bit register to power down * the logical device (optional) * SUPERIO_PNP_PM_VAL The value for SUPERIO_PNP_PM_REG to power the logical @@ -54,6 +55,13 @@ Name (_DDN, SUPERIO_PNP_DDN) #endif + +#ifdef SUPERIO_PNP_NO_DIS + Method (_STA) + { + Return (DEVICE_PRESENT_ACTIVE) + } +#else Method (_STA) { PNP_GENERIC_STA(SUPERIO_PNP_LDN) @@ -63,6 +71,7 @@ { PNP_GENERIC_DIS(SUPERIO_PNP_LDN) } +#endif #ifdef SUPERIO_PNP_PM_REG Method (_PSC) { diff --git a/src/superio/ite/it8720f/acpi/superio.asl b/src/superio/ite/it8720f/acpi/superio.asl index fdd8f7e..95b09e1 100644 --- a/src/superio/ite/it8720f/acpi/superio.asl +++ b/src/superio/ite/it8720f/acpi/superio.asl @@ -127,6 +127,7 @@ #undef SUPERIO_PNP_HID #undef SUPERIO_PNP_LDN #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_NO_DIS #undef SUPERIO_PNP_PM_REG #undef SUPERIO_PNP_PM_VAL #undef SUPERIO_PNP_PM_LDN @@ -158,6 +159,7 @@ #undef SUPERIO_PNP_HID #undef SUPERIO_PNP_LDN #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_NO_DIS #undef SUPERIO_PNP_PM_REG #undef SUPERIO_PNP_PM_VAL #undef SUPERIO_PNP_PM_LDN @@ -167,6 +169,7 @@ #undef SUPERIO_PNP_IRQ0 #undef SUPERIO_PNP_IRQ1 #undef SUPERIO_PNP_DMA + #define SUPERIO_PNP_NO_DIS #define SUPERIO_PNP_LDN 7 #define SUPERIO_PNP_IO0 0x08, 0x08 #define SUPERIO_PNP_IO1 0x08, 0x08 @@ -178,6 +181,7 @@ #undef SUPERIO_PNP_HID #undef SUPERIO_PNP_LDN #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_NO_DIS #undef SUPERIO_PNP_PM_REG #undef SUPERIO_PNP_PM_VAL #undef SUPERIO_PNP_PM_LDN diff --git a/src/superio/ite/it8721f/acpi/superio.asl b/src/superio/ite/it8721f/acpi/superio.asl index 065ec52..22746ed 100644 --- a/src/superio/ite/it8721f/acpi/superio.asl +++ b/src/superio/ite/it8721f/acpi/superio.asl @@ -127,6 +127,7 @@ #undef SUPERIO_PNP_HID #undef SUPERIO_PNP_LDN #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_NO_DIS #undef SUPERIO_PNP_PM_REG #undef SUPERIO_PNP_PM_VAL #undef SUPERIO_PNP_PM_LDN diff --git a/src/superio/ite/it8784e/acpi/superio.asl b/src/superio/ite/it8784e/acpi/superio.asl index c145a2b..f79fc32 100644 --- a/src/superio/ite/it8784e/acpi/superio.asl +++ b/src/superio/ite/it8784e/acpi/superio.asl @@ -122,6 +122,7 @@ #undef SUPERIO_PNP_HID #undef SUPERIO_PNP_LDN #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_NO_DIS #undef SUPERIO_PNP_PM_REG #undef SUPERIO_PNP_PM_VAL #undef SUPERIO_PNP_PM_LDN diff --git a/src/superio/nuvoton/nct6687d/acpi/superio.asl b/src/superio/nuvoton/nct6687d/acpi/superio.asl index ebddeae..9de8729 100644 --- a/src/superio/nuvoton/nct6687d/acpi/superio.asl +++ b/src/superio/nuvoton/nct6687d/acpi/superio.asl @@ -102,6 +102,7 @@ #undef SUPERIO_PNP_HID #undef SUPERIO_PNP_LDN #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_NO_DIS #undef SUPERIO_PNP_PM_REG #undef SUPERIO_PNP_PM_VAL #undef SUPERIO_PNP_PM_LDN @@ -157,6 +158,7 @@ #undef SUPERIO_PNP_HID #undef SUPERIO_PNP_LDN #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_NO_DIS #undef SUPERIO_PNP_PM_REG #undef SUPERIO_PNP_PM_VAL #undef SUPERIO_PNP_PM_LDN diff --git a/src/superio/nuvoton/nct6776/acpi/superio.asl b/src/superio/nuvoton/nct6776/acpi/superio.asl index b8c396f..1297aa1 100644 --- a/src/superio/nuvoton/nct6776/acpi/superio.asl +++ b/src/superio/nuvoton/nct6776/acpi/superio.asl @@ -100,6 +100,7 @@ #undef SUPERIO_PNP_HID #undef SUPERIO_PNP_LDN #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_NO_DIS #undef SUPERIO_PNP_PM_REG #undef SUPERIO_PNP_PM_VAL #undef SUPERIO_PNP_PM_LDN @@ -145,6 +146,7 @@ #undef SUPERIO_PNP_HID #undef SUPERIO_PNP_LDN #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_NO_DIS #undef SUPERIO_PNP_PM_REG #undef SUPERIO_PNP_PM_VAL #undef SUPERIO_PNP_PM_LDN @@ -165,6 +167,7 @@ #undef SUPERIO_PNP_HID #undef SUPERIO_PNP_LDN #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_NO_DIS #undef SUPERIO_PNP_PM_REG #undef SUPERIO_PNP_PM_VAL #undef SUPERIO_PNP_PM_LDN diff --git a/src/superio/winbond/w83627dhg/acpi/superio.asl b/src/superio/winbond/w83627dhg/acpi/superio.asl index 298e9a7..18ce2c0 100644 --- a/src/superio/winbond/w83627dhg/acpi/superio.asl +++ b/src/superio/winbond/w83627dhg/acpi/superio.asl @@ -192,6 +192,7 @@ #ifdef W83627DHG_SHOW_HWMON #undef SUPERIO_PNP_LDN #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_NO_DIS #undef SUPERIO_PNP_PM_REG #undef SUPERIO_PNP_PM_VAL #undef SUPERIO_PNP_PM_LDN -- To view, visit https://review.coreboot.org/c/coreboot/+/80496?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieb827fdffe7660b875cba6ca99b0560b4cab66b4 Gerrit-Change-Number: 80496 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: drivers/smm_payload_interface: Add initial support for SMM payload
by Benjamin Doron (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Arthur Heymans, Martin L Roth, Michał Żygowski, Patrick Rudolph, Sean Rhodes. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70378?usp=email ) Change subject: drivers/smm_payload_interface: Add initial support for SMM payload ...................................................................... Patch Set 18: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/70378/comment/ab268084_b18da85b : PS18, Line 37: - coreboot provides register definitions in CBMEM to avoid : silicon-dependence in payload. > I don't think coreboot informing the payload should be done in this case. […] I'd rather avoid the tedious maintenance burden associated with this. At best, whenever Intel/AMD release new chipsets, we'd be adding PCIe device IDs to some long switch case. At worst, we'd be copying a pile of register definitions into the payload, when this was already done as part of coreboot SoC bring-up. I don't mind changing the format, but I think it may become irrelevant if we replace it with our follow-up work. File src/commonlib/include/commonlib/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/70378/comment/0978652b_4e1c2191 : PS18, Line 620: lb_pld_smram_descriptor_block > what is this? Are there systems that can have multiple SMRAM regions? It's an EDK2 concept: it could be used to support multiple SMRAM regions, sure. In practice, it's often used for marking one region as reserved/allocated. Here, we reserve a page of memory to share a struct between bootloader and payload. The offset of the shared region is already shared as part of another table, so, I can rework this so that coreboot is not implementing EDK2-specific details. File src/include/smm_payload_interface.h: https://review.coreboot.org/c/coreboot/+/70378/comment/a936269c_1fd02f49 : PS18, Line 43: truct CPU_SMMBASE { : uint32_t ApicId; : uint32_t SmmBase; : }; : : struct SMM_S3_INFO { : uint8_t SwSmiData; : uint8_t SwSmiTriggerValue; : uint16_t Reserved; : uint32_t CpuCount; : struct CPU_SMMBASE SmmBase[0]; > Any reason to deviate from coreboot style? I copied the struct used from EDK2, and didn't change it. Again, this may become irrelevant if we replace it with our follow-up work. -- To view, visit https://review.coreboot.org/c/coreboot/+/70378?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dd505a154175b6da8929b1157723de1645ca8fa Gerrit-Change-Number: 70378 Gerrit-PatchSet: 18 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 01 Mar 2024 15:26:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: MAINTAINERS: Add Dinesh Gehlot as ADL SOC and BRYA MB maintainer
by Felix Held (Code Review) 01 Mar '24

01 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80778?usp=email ) Change subject: MAINTAINERS: Add Dinesh Gehlot as ADL SOC and BRYA MB maintainer ...................................................................... MAINTAINERS: Add Dinesh Gehlot as ADL SOC and BRYA MB maintainer Change-Id: I6ad9dbe3bd073f3c43878beec201491b87694fc3 Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80778 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M MAINTAINERS 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/MAINTAINERS b/MAINTAINERS index d093071..a1ede9f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -360,6 +360,7 @@ M: Nick Vaccaro <nvaccaro(a)chromium.org> M: Eric Lai <ericllai(a)google.com> M: Kapil Porwal <kapilporwal(a)google.com> +M: Dinesh Gehlot <digehlot(a)google.com> S: Maintained F: src/mainboard/google/brya/ @@ -897,6 +898,7 @@ M: Subrata Banik <subratabanik(a)google.com> M: Nick Vaccaro <nvaccaro(a)chromium.org> M: Kapil Porwal <kapilporwal(a)google.com> +M: Dinesh Gehlot <digehlot(a)google.com> S: Maintained F: src/soc/intel/alderlake/ -- To view, visit https://review.coreboot.org/c/coreboot/+/80778?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6ad9dbe3bd073f3c43878beec201491b87694fc3 Gerrit-Change-Number: 80778 Gerrit-PatchSet: 4 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: lib/ramdetect: Limit probe size to function argument
by Maximilian Brune (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Arthur Heymans, Nico Huber, Philipp Hug. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68842?usp=email ) Change subject: lib/ramdetect: Limit probe size to function argument ...................................................................... Patch Set 10: (1 comment) File src/lib/ramdetect.c: https://review.coreboot.org/c/coreboot/+/68842/comment/5dcc091b_4c19894f : PS7, Line 50: /* Find the MSB + 1. */ > Wouldn't starting with MSB instead achieve the same? I don't think finding MSB+1 should be used either. Because MSB+1 will always trigger the if condition below. I would just make the do-while loop to a generic while loop. ``` while (tmp >>= 1) { msb++; } ``` But that would still require to check that we don't probe something above probe_size. Unless probe_size is a power of 2, but I am not sure if that is a requirement for this function. -- To view, visit https://review.coreboot.org/c/coreboot/+/68842?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7f915c6e150629eff235ee94719172467a54db2 Gerrit-Change-Number: 68842 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 01 Mar 2024 15:11:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: amdfwtool: Set the table size for L1 separately
by Felix Held (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Bao Zheng, Martin Roth, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78274?usp=email ) Change subject: amdfwtool: Set the table size for L1 separately ...................................................................... Patch Set 11: (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/78274/comment/49272842_82e7ae81 : PS11, Line 655: if (cookie == PSP_COOKIE && cb_config->need_ish) : table_size = TABLE_ALIGNMENT; : else haven't traced the code, but from what i've seen, the actual bug seems to be that in integrate_psp_firmwares the new_ish_dir calls increase ctx->current to point to the end of the ish, but fill_dir_header which gets called after new_ish_dir expects ctx->current to point at the end of the psp directory table. saving the ctx->current before the new_ish_dir calls, using that for the fill_dir_header call and then restoring the ctx->current or something like that is probably a more maintainable fix -- To view, visit https://review.coreboot.org/c/coreboot/+/78274?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id4fbc6d57d7ea070a9478649a96af92be9441289 Gerrit-Change-Number: 78274 Gerrit-PatchSet: 11 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 01 Mar 2024 14:55:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: cpu/x86/smm/smm_module_loader.c: Pass full SMRAM region info to SMM r...
by Benjamin Doron (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Jeff Daly, Johnny Lin, Jérémy Compostella, Lean Sheng Tan, Matt DeVillier, Shuo Liu, Tim Chu, Vanessa Eusebio. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80703?usp=email ) Change subject: cpu/x86/smm/smm_module_loader.c: Pass full SMRAM region info to SMM runtime ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80703/comment/2664e08a_cd5002e0 : PS2, Line 17: integrity of the S3 resume path. > I suppose the default region_overlaps_handler() cannot achieve this at the moment. […] smm_region_overlaps_handler() consumes these fields. It's also the only consumer of them, so we don't have to worry about changing behaviour. By updating the value, smm_region_overlaps_handler() will protect the entire SMRAM. https://review.coreboot.org/c/coreboot/+/80703/comment/681fbbca_750af248 : PS2, Line 19: The consequences to overwriting the chipset-specific area are undefined. > Could you please specify the definition here for 'chipset-specific' area? This is common code, there is no specific definition. In practice, I've seen this area used as Intel's IED (Intel Enhanced Debug). -- To view, visit https://review.coreboot.org/c/coreboot/+/80703?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd9ed34fcfd77a4236b5cf122747a6718ce9c91f Gerrit-Change-Number: 80703 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 01 Mar 2024 14:54:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/erying: Add Erying Polestar G613 Pro (TGL-H)
by Alicja Michalska (Code Review) 01 Mar '24

01 Mar '24

Alicja Michalska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80853?usp=email ) Change subject: mb/erying: Add Erying Polestar G613 Pro (TGL-H) ...................................................................... mb/erying: Add Erying Polestar G613 Pro (TGL-H) Erying is a Chinese manufacturer selling desktop motherboards with laptop SoCs and custom shim to mount desktop coolers. Working: - Serial port (IT8613E RS232) - All rear USB ports (3.0, 2.0) - Both HDMI ports - Realtek GbE NIC - Internal audio (ALC897/ TGL-H HDMI) - Environment Controller (SuperIO fan control) - All SATA ports - All PCI-E/M.2 ports (somewhat) - PCI-E Resizable BAR (ReBAR) - VT-x (PCI-E passtrough, broken on stock) WIP/Broken: - PCI-E ASPM (even though I force-disabled it, I'm still getting AERs) - M.2 NGFF WiFi (should be working, but I lost my WiFi card while moving) - S3/s0ix (also broken on stock, setting 3VSB register didn't help - system goes to sleep, but RAM loses power) - DisplayPort on I/O panel (simple fix, need to re-configure GPIOs) - One of USB2 FP connectors, as well as NGFF USB isn't mapped (yet) - Automatic fan control (IT8613E can't read CPU_TIN at the moment) Can be flashed using `flashrom -p internal -w build/coreboot.rom`, as vendor haven't enabled any protections on SPI chip. I'd like to get ASPM working as it makes big difference in idle power consumtion (25 vs 60W measured from the wall at 230V). Likewise, I can't wrap my head around PCI-E AERs I'm getting if I boot the machine without `pcie_aspm=off` parameter: - BadTLP - BadDLLP - Timeout - Rollover Adjusting LaneEq's didn't change anything, all settings are configured in (mostly) the same way as they were on stock firmware. Starting to suspect Intel's FSP might be buggy, as I haven't had those issues when I initially started working on this project when 4.20 tree was current. TEST=Flash coreboot build onto the motherboard, install following PCI-E cards: Radeon RX 7800XT, Kingston KC3000, Optane 900P, Audigy X-Fi. Power the system up and boot into Windows 10 to check ACPI sanity, then reboot into Fedora Linux (kernel 6.7.4) and launch 3D application, disk benchmark, compilation at the same time to check system's stability. Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e Signed-off-by: Alicja Michalska <ahplka19(a)gmail.com> --- A src/mainboard/erying/Kconfig A src/mainboard/erying/Kconfig.name A src/mainboard/erying/tgl/Kconfig A src/mainboard/erying/tgl/Kconfig.name A src/mainboard/erying/tgl/Makefile.inc A src/mainboard/erying/tgl/board_info.txt A src/mainboard/erying/tgl/bootblock.c A src/mainboard/erying/tgl/cmos.layout A src/mainboard/erying/tgl/data.vbt A src/mainboard/erying/tgl/devicetree.cb A src/mainboard/erying/tgl/dsdt.asl A src/mainboard/erying/tgl/gpio.h A src/mainboard/erying/tgl/hda_verb.c A src/mainboard/erying/tgl/ramstage.c A src/mainboard/erying/tgl/romstage_fsp_params.c 15 files changed, 881 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/80853/1 diff --git a/src/mainboard/erying/Kconfig b/src/mainboard/erying/Kconfig new file mode 100644 index 0000000..cff6d31 --- /dev/null +++ b/src/mainboard/erying/Kconfig @@ -0,0 +1,15 @@ +if VENDOR_ERYING + +choice + prompt "Mainboard model" + +source "src/mainboard/erying/*/Kconfig.name" + +endchoice + +source "src/mainboard/erying/*/Kconfig" + +config MAINBOARD_VENDOR + default "Erying" + +endif # VENDOR_ERYING diff --git a/src/mainboard/erying/Kconfig.name b/src/mainboard/erying/Kconfig.name new file mode 100644 index 0000000..16fb6e4 --- /dev/null +++ b/src/mainboard/erying/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_ERYING + bool "Erying" diff --git a/src/mainboard/erying/tgl/Kconfig b/src/mainboard/erying/tgl/Kconfig new file mode 100644 index 0000000..02fdd75 --- /dev/null +++ b/src/mainboard/erying/tgl/Kconfig @@ -0,0 +1,45 @@ +if BOARD_ERYING_TGL + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select SOC_INTEL_TIGERLAKE + select SOC_INTEL_TIGERLAKE_PCH_H + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_COMMON_BLOCK_MEMINIT + select INTEL_GMA_HAVE_VBT + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select SUPERIO_ITE_IT8613E + select DRIVERS_UART_8250IO + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + +config MAINBOARD_DIR + default "erying/tgl" + +config MAINBOARD_PART_NUMBER + default "erying-tgl" + +config DIMM_SPD_SIZE + default 512 + +config CBFS_SIZE + default 0xA00000 + +config PCIEXP_ASPM + default n + +config PCIEXP_CLK_PM + default n + +config PCIEXP_L1_SUB_STATE + default n + +config CONSOLE_POST + default y + +config POST_DEVICE + default n + +endif diff --git a/src/mainboard/erying/tgl/Kconfig.name b/src/mainboard/erying/tgl/Kconfig.name new file mode 100644 index 0000000..2531358 --- /dev/null +++ b/src/mainboard/erying/tgl/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ERYING_TGL + bool "erying-tgl" diff --git a/src/mainboard/erying/tgl/Makefile.inc b/src/mainboard/erying/tgl/Makefile.inc new file mode 100644 index 0000000..9bda2eb --- /dev/null +++ b/src/mainboard/erying/tgl/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +romstage-y += romstage_fsp_params.c + +ramstage-y += ramstage.c diff --git a/src/mainboard/erying/tgl/board_info.txt b/src/mainboard/erying/tgl/board_info.txt new file mode 100644 index 0000000..8a24c36 --- /dev/null +++ b/src/mainboard/erying/tgl/board_info.txt @@ -0,0 +1,7 @@ +Board name: Erying Polestar G613 Pro +Release year: 2022 +Category: desktop +ROM IC: W25Q128FV +ROM package: SOIC-8 +ROM socketed: no +Flashrom support: yes diff --git a/src/mainboard/erying/tgl/bootblock.c b/src/mainboard/erying/tgl/bootblock.c new file mode 100644 index 0000000..3183c67 --- /dev/null +++ b/src/mainboard/erying/tgl/bootblock.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8613e/it8613e.h> +#include <gpio.h> + +#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO) +#define UART_DEV PNP_DEV(0x2e, IT8613E_SP1) + +void bootblock_mainboard_early_init(void) +{ + ite_reg_write(GPIO_DEV, 0x29, 0xc1); /* 3VSB - RAM loses power in S3 anyway */ + ite_reg_write(GPIO_DEV, 0x2c, 0x41); /* disable k8 power seq */ + ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/erying/tgl/cmos.layout b/src/mainboard/erying/tgl/cmos.layout new file mode 100644 index 0000000..a53c3f4 --- /dev/null +++ b/src/mainboard/erying/tgl/cmos.layout @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-only + +entries + +0 384 r 0 reserved_memory + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# RTC_CLK_ALTCENTURY +400 8 r 0 century + +412 4 e 6 debug_level +416 1 e 2 me_state +417 3 h 0 me_state_counter +984 16 h 0 check_sum + +enumerations + +2 0 Enable +2 1 Disable + +4 0 Fallback +4 1 Normal + +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew + +checksums + +checksum 408 983 984 diff --git a/src/mainboard/erying/tgl/data.vbt b/src/mainboard/erying/tgl/data.vbt new file mode 100644 index 0000000..ad77081 --- /dev/null +++ b/src/mainboard/erying/tgl/data.vbt Binary files differ diff --git a/src/mainboard/erying/tgl/devicetree.cb b/src/mainboard/erying/tgl/devicetree.cb new file mode 100755 index 0000000..9b4bd91 --- /dev/null +++ b/src/mainboard/erying/tgl/devicetree.cb @@ -0,0 +1,227 @@ +chip soc/intel/tigerlake + + # Power limits/thermals - adjust according to your needs, but beware of VRM cooling! + # H_6_CORE means Core i5, H_8_CORE means Core i7 or i9. Stock PL1/PL2: 45/109W. + register "power_limits_config[POWER_LIMITS_H_6_CORE]" = "{ + .tdp_pl1_override = 45, + .tdp_pl2_override = 109, + }" + + register "power_limits_config[POWER_LIMITS_H_8_CORE]" = "{ + .tdp_pl1_override = 45, + .tdp_pl2_override = 109, + }" + register "tcc_offset" = "10" + + # FSP configuration + register "eist_enable" = "1" + register "enable_c6dram" = "1" + register "SkipExtGfxScan" = "0" + register "HybridStorageMode" = "1" + + # IT8613E doesn't support s0ix specification, only S3 is possible. + # Sleep is broken, supposedly RAM loses power in S3 state. + register "s0ix_enable" = "0" + + # Power + register "deep_s3_enable_ac" = "1" + register "deep_s3_enable_dc" = "1" + register "deep_s5_enable_ac" = "1" + register "deep_s5_enable_dc" = "1" + register "deep_sx_config" = "DSX_EN_WAKE_PIN" + + device cpu_cluster 0 on end + device domain 0 on + device ref system_agent on end + + # [01.0] PCI-E x16 4.0 (SoC) + device ref peg1 on + register "PcieClkSrcUsage[0]" = "0x41" + register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" + end + + # [02.0] TigerLake-H GT1 + device ref igpu on + register "DdiPortBConfig" = "DDI_PORT_CFG_NO_LFP" # DP + register "DdiPortBHpd" = "1" + register "DdiPortBDdc" = "1" + + register "DdiPortCHpd" = "1" # HDMI + register "DdiPortCDdc" = "1" + + register "DdiPort1Hpd" = "1" # HDMI + register "DdiPort1Ddc" = "1" + end + + # [06.0] M.2 x4 4.0 (SoC) + device ref peg0 on + register "PcieClkSrcUsage[2]" = "0x40" + register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED" + end + + # [0d.0] Tiger Lake-H Thunderbolt 4 USB Controller + device ref north_xhci on + register "TcssXhciEn" = "1" + end + + # [14.0] Tiger Lake-H USB 3.2 Gen 2x1 xHCI Host Controller + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC0), /* Rear, bottom right */ + [1] = USB2_PORT_MID(OC0), /* Rear, bottom left */ + [2] = USB2_PORT_MID(OC2), /* NIC left */ + [3] = USB2_PORT_MID(OC2), /* NIC right */ + [4] = USB2_PORT_MID(OC2), /* Front Panel 1 */ + [5] = USB2_PORT_MID(OC2), /* Front Panel 2 */ + [8] = USB2_PORT_MID(OC0), /* Front Panel 1 (USB3) */ + [9] = USB2_PORT_MID(OC0), /* Front Panel 2 (USB3) */ + [10] = USB2_PORT_MID(OC0), /* Rear, top left */ + [11] = USB2_PORT_MID(OC0), /* Rear, top right */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), /* Rear, bottom right */ + [1] = USB3_PORT_DEFAULT(OC0), /* Rear, bottom left */ + [2] = USB3_PORT_DEFAULT(OC0), /* Front Panel 1 */ + [3] = USB3_PORT_DEFAULT(OC0), /* Front Panel 2 */ + [4] = USB3_PORT_DEFAULT(OC0), /* Rear, top left */ + [5] = USB3_PORT_DEFAULT(OC0), /* Rear, top right */ + }" + end + + # [14.2] Shared SRAM + device ref shared_ram on end + + # [16.0] Management Engine + device ref heci1 off end + + # [17.0] SATA controller + device ref sata on + register "SataMode" = "0" # AHCI mode + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataSalpSupport" = "1" + register "SataPortsDevSlp[0]" = "1" + register "SataPortsDevSlp[1]" = "1" + register "SataPortsDevSlp[2]" = "1" + register "SataPortsDevSlp[3]" = "1" + end + + # [1c.4] PCH RootPort 5 (M.2 x4 Gen3) + device ref pcie_rp5 on + # register "PcieRpLtrEnable[4]" = "1" + register "PcieRpSlotImplemented[4]" = "1" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieClkSrcUsage[4]" = "4" + register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED" + end + + # [1d.0] PCH RootPort 9 (M.2 NGFF "WiFi") + device ref pcie_rp9 on + # register "PcieRpLtrEnable[8]" = "1" + register "PcieRpSlotImplemented[8]" = "1" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieClkSrcUsage[5]" = "8" + register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED" + end + + # [1d.2] PCH RootPort 11 (Realtek RTL8111 NIC) + device ref pcie_rp11 on + register "PcieRpLtrEnable[10]" = "1" + register "PcieClkSrcUsage[3]" = "10" + register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED" + end + + # [1d.3] PCH RootPort 12 (PCI-E x1 Gen3) + device ref pcie_rp12 on + # register "PcieRpLtrEnable[11]" = "1" + register "PcieRpSlotImplemented[11]" = "1" + register "PcieRpAdvancedErrorReporting[11]" = "1" + register "PcieClkSrcUsage[1]" = "11" + register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED" + end + + device ref uart0 on + register "SerialIoUartMode[PchSerialIoIndexUART0]" = "PchSerialIoPci" + end + + device ref gspi1 on + register "SerialIoGSpiMode[PchSerialIoIndexGSPI1]" = "PchSerialIoPci" + end + + device ref pch_espi on + chip superio/ite/it8613e + device pnp 2e.0 off end + device pnp 2e.1 on # COM 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + irq 0xf0 = 1 + end + + # WIP - Fans can be controlled using pwmconfig! + # modprobe it87 force_id=0x8603 + device pnp 2e.4 on # Environment Controller + io 0x60 = 0xa30 + io 0x62 = 0xa20 + irq 0x70 = 0x00 + irq 0xf4 = 0xe0 + irq 0xf5 = 0x00 + irq 0xf6 = 0xf0 + + register "TMPIN1.mode" = "THERMAL_DIODE" + register "TMPIN2.mode" = "THERMAL_DIODE" + + register "FAN2.mode" = "FAN_SMART_AUTOMATIC" # CPU_FAN + register "FAN3.mode" = "FAN_SMART_AUTOMATIC" # SYS_FAN + + register "FAN2.smart.tmpin" = "1" + register "FAN2.smart.tmp_off" = "35" + register "FAN2.smart.tmp_start" = "42" + register "FAN2.smart.tmp_full" = "72" + register "FAN2.smart.tmp_delta" = "2" + register "FAN2.smart.pwm_start" = "26" + register "FAN2.smart.slope" = "24" + + register "FAN3.smart.tmpin" = "1" + register "FAN3.smart.tmp_off" = "35" + register "FAN3.smart.tmp_start" = "42" + register "FAN3.smart.tmp_full" = "72" + register "FAN3.smart.tmp_delta" = "2" + register "FAN3.smart.pwm_start" = "26" + register "FAN3.smart.slope" = "24" + end + + device pnp 2e.5 off end + device pnp 2e.6 off end + + device pnp 2e.7 on # GPIO + irq 0x29 = 0xc0 + irq 0x2c = 0x41 + irq 0x2d = 0x02 + io 0x60 = 0xa10 + io 0x62 = 0xa00 + irq 0x70 = 0x00 + irq 0x71 = 0x01 + irq 0xbc = 0xc0 + irq 0xbd = 0x03 + irq 0xc1 = 0x02 + irq 0xc8 = 0x00 + irq 0xc9 = 0x02 + irq 0xda = 0xb0 + irq 0xdb = 0x44 + end + device pnp 2e.a off end # CIR + end + end + device ref p2sb hidden end + device ref hda on + subsystemid 0x10ec 0x3000 + register "PchHdaAudioLinkHdaEnable" = "1" + register "PchHdaDspEnable" = "0" + end + device ref smbus on end + device ref fast_spi off end + end +end diff --git a/src/mainboard/erying/tgl/dsdt.asl b/src/mainboard/erying/tgl/dsdt.asl new file mode 100644 index 0000000..e6ca367 --- /dev/null +++ b/src/mainboard/erying/tgl/dsdt.asl @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/tigerlake/acpi/southbridge.asl> + #include <soc/intel/tigerlake/acpi/tcss.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Scope (\_SB.PCI0.LPCB) + { + } +} diff --git a/src/mainboard/erying/tgl/gpio.h b/src/mainboard/erying/tgl/gpio.h new file mode 100644 index 0000000..9cce53d --- /dev/null +++ b/src/mainboard/erying/tgl/gpio.h @@ -0,0 +1,288 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* ESPI_IO0 */ + _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* ESPI_IO1 */ + _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* ESPI_IO2 */ + _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* ESPI_IO3 */ + _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* ESPI_CS0# */ + _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* ESPI_CLK */ + _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* ESPI_RESET# */ + _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* ESPI_CS1# */ + _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), /* ESPI_CS2# */ + _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* ESPI_CS3# */ + _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(UP_20K)), /* ESPI_ALERT0# */ + _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), /* ESPI_ALERT1# */ + _PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), /* ESPI_ALERT2# */ + _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), /* ESPI_ALERT3# */ + _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */ + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0 + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST# + PAD_NC(GPP_R5, NONE), /* GPIO */ + _PAD_CFG_STRUCT(GPP_R6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */ + _PAD_CFG_STRUCT(GPP_R7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */ + _PAD_CFG_STRUCT(GPP_R8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */ + _PAD_CFG_STRUCT(GPP_R9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* PCIE_LNK_DOWN */ + _PAD_CFG_STRUCT(GPP_R10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* ISH_UART0_RTS# */ + _PAD_CFG_STRUCT(GPP_R11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* SX_EXIT_HOLDOFF# */ + _PAD_CFG_STRUCT(GPP_R12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CLKOUT_48 */ + _PAD_CFG_STRUCT(GPP_R13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ISH_GP7 */ + PAD_NC(GPP_R14, NONE), /* GPIO */ + PAD_NC(GPP_R15, NONE), /* GPIO */ + PAD_NC(GPP_R16, NONE), /* GPIO */ + PAD_NC(GPP_R17, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_R18, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_R19, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_GPO(GPP_B0, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_B1, NONE), /* GPIO */ + PAD_NC(GPP_B2, NONE), /* GPIO */ + PAD_NC(GPP_B3, NONE), /* GPIO */ + PAD_NC(GPP_B4, NONE), /* GPIO */ + PAD_NC(GPP_B5, NONE), /* SRCCLKREQ0 - Not used */ + PAD_NC(GPP_B6, NONE), /* SRCCLKREQ1 - Not used */ + PAD_NC(GPP_B7, NONE), /* SRCCLKREQ2 - Not used */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* SRCCLKREQ3 */ + PAD_NC(GPP_B9, NONE), /* GPIO */ + PAD_NC(GPP_B10, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_B11, 1, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# + PAD_NC(GPP_B13, NONE), /* GPIO */ + PAD_NC(GPP_B14, NONE), /* GPIO */ + PAD_NC(GPP_B15, NONE), /* GPIO */ + PAD_NC(GPP_B16, NONE), /* GPIO */ + PAD_NC(GPP_B17, NONE), /* GPIO */ + PAD_NC(GPP_B18, NONE), /* GPIO */ + PAD_NC(GPP_B19, NONE), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GSPI1_CLK */ + _PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GSPI1_MISO */ + _PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* GSPI1_MOSI */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), /* GPIO */ + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, NONE), /* GPIO */ + PAD_NC(GPP_D1, NONE), /* GPIO */ + PAD_NC(GPP_D2, NONE), /* GPIO */ + PAD_NC(GPP_D3, NONE), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SML1CLK */ + _PAD_CFG_STRUCT(GPP_D5, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CNV_RF_RESET# */ + _PAD_CFG_STRUCT(GPP_D6, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* MODEM_CLKREQ */ + PAD_NC(GPP_D7, NONE), /* GPIO */ + PAD_NC(GPP_D8, NONE), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SML0CLK */ + _PAD_CFG_STRUCT(GPP_D10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SML0DATA */ + PAD_CFG_GPO(GPP_D11, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_D12, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_D13, NONE), /* GPIO */ + PAD_NC(GPP_D14, NONE), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SML1DATA */ + PAD_NC(GPP_D16, NONE), /* GPIO */ + PAD_NC(GPP_D17, NONE), /* GPIO */ + PAD_NC(GPP_D18, NONE), /* GPIO */ + PAD_NC(GPP_D19, NONE), /* GPIO */ + PAD_NC(GPP_D20, NONE), /* GPIO */ + PAD_NC(GPP_D21, NONE), /* GPIO */ + PAD_NC(GPP_D22, NONE), /* GPIO */ + PAD_NC(GPP_D23, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_C ------- */ + _PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SMBCLK */ + _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SMBDATA */ + PAD_CFG_GPO(GPP_C2, 1, PLTRST), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* I2C2_SDA */ + _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* I2C2_SCL */ + PAD_CFG_GPO(GPP_C5, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C6, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* I2C3_SDA */ + _PAD_CFG_STRUCT(GPP_C7, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* I2C3_SCL */ + PAD_NC(GPP_C8, NONE), /* GPIO */ + PAD_NC(GPP_C9, NONE), /* GPIO */ + PAD_NC(GPP_C10, NONE), /* GPIO */ + PAD_NC(GPP_C11, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_C12, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_C13, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_C14, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_C15, 1, PLTRST), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* I2C0_SDA */ + _PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* I2C0_SCL */ + _PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* I2C1_SDA */ + _PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* I2C1_SCL */ + PAD_NC(GPP_C20, NONE), /* GPIO */ + PAD_NC(GPP_C21, NONE), /* GPIO */ + PAD_NC(GPP_C22, NONE), /* GPIO */ + PAD_NC(GPP_C23, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_S ------- */ + _PAD_CFG_STRUCT(GPP_S0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SNDW1_CLK */ + _PAD_CFG_STRUCT(GPP_S1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SNDW1_DATA */ + _PAD_CFG_STRUCT(GPP_S2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SNDW2_CLK */ + _PAD_CFG_STRUCT(GPP_S3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SNDW2_DATA */ + _PAD_CFG_STRUCT(GPP_S4, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DMIC_CLKA1 */ + _PAD_CFG_STRUCT(GPP_S5, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DMIC_DATA1 */ + _PAD_CFG_STRUCT(GPP_S6, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DMIC_CLKA0 */ + _PAD_CFG_STRUCT(GPP_S7, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DMIC_DATA0 */ + + /* ------- GPIO Group GPP_G ------- */ + PAD_NC(GPP_G0, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_G1, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G2, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_G3, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_G4, 1, PLTRST), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_DRAM# */ + PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_G7, 1, PLTRST), /* GPIO */ + _PAD_CFG_STRUCT(GPP_G8, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDP3_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_G9, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDP3_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_G10, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDP4_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_G11, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDP4_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDP1_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_G13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDP1_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_G14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDP2_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_G15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDP2_CTRLDATA */ + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPD ------- */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), /* BATLOW# */ + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* ACPRESENT */ + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* LAN_WAKE# */ + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* PWRBTN# */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* SLP_S3# */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* SLP_S4# */ + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* SLP_A# */ + PAD_CFG_GPO(GPD7, 0, PWROK), /* GPIO */ + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK */ + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* SLP_WLAN# */ + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* SLP_S5# */ + PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */ + PAD_NC(GPD12, NONE), /* GPIO */ + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* SATAXPCIE0 */ + PAD_CFG_NF(GPP_E1, NONE, PLTRST, NF1), /* SATAXPCIE1 */ + PAD_CFG_GPO(GPP_E2, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_E3, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_E4, 1, PLTRST), /* SATA_DEVSLP0 */ + PAD_CFG_NF(GPP_E5, NONE, RSMRST, NF1), /* SATA_DEVSLP1 */ + PAD_CFG_GPO(GPP_E6, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_E7, NONE), /* GPIO */ + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2), /* SATALED# */ + PAD_CFG_NF(GPP_E9, NONE, PLTRST, NF1), /* USB_OC0# */ + PAD_CFG_NF(GPP_E10, NONE, PLTRST, NF1), /* USB_OC1# */ + PAD_CFG_NF(GPP_E11, NONE, PLTRST, NF1), /* USB_OC2# */ + PAD_CFG_NF(GPP_E12, NONE, PLTRST, NF1), /* USB_OC3# */ + + /* ------- GPIO Group GPP_F ------- */ + _PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SATAXPCIE3 */ + _PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SATAXPCIE4 */ + _PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SATAXPCIE5 */ + PAD_CFG_GPO(GPP_F3, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_F4, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_F5, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_F6, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_F8, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_F9, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_F10, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_F11, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_F12, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F13, 1, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_F14, NONE, PLTRST, NF1), /* PS_ON# */ + PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_F16, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_F17, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_F18, 1, PLTRST), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* eDP_VDDEN */ + _PAD_CFG_STRUCT(GPP_F20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* eDP_BKLTEN */ + _PAD_CFG_STRUCT(GPP_F21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* eDP_BKLTCTL */ + PAD_NC(GPP_F22, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_F23, 1, PLTRST), /* GPIO */ + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_H ------- */ + PAD_NC(GPP_H0, NONE), /* SRCCLKREQ6 - Not used */ + PAD_NC(GPP_H1, NONE), /* SRCCLKREQ7 - Not used */ + PAD_NC(GPP_H2, NONE), /* SRCCLKREQ8 - Not used */ + PAD_NC(GPP_H3, NONE), /* SRCCLKREQ9 - Not used */ + PAD_NC(GPP_H4, NONE), /* SRCCLKREQ10 - Not used */ + PAD_NC(GPP_H5, NONE), /* SRCCLKREQ11 - Not used */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* SRCCLKREQ12 */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* SRCCLKREQ13 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* SRCCLKREQ14 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* SRCCLKREQ15 */ + PAD_CFG_GPO(GPP_H10, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_H11, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_H12, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H13, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H14, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H15, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H16, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H17, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H18, 0, PLTRST), /* GPIO */ + PAD_NC(GPP_H19, NONE), /* GPIO */ + PAD_NC(GPP_H20, NONE), /* GPIO */ + PAD_NC(GPP_H21, NONE), /* GPIO */ + PAD_NC(GPP_H22, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_H23, 1, PLTRST), /* GPIO */ + + /* ------- GPIO Group GPP_J ------- */ + PAD_CFG_GPO(GPP_J0, 1, PLTRST), /* GPIO */ + _PAD_CFG_STRUCT(GPP_J1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CPU_C10_GATE# */ + _PAD_CFG_STRUCT(GPP_J2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CNV_BRI_DT */ + _PAD_CFG_STRUCT(GPP_J3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* CNV_BRI_RSP */ + _PAD_CFG_STRUCT(GPP_J4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CNV_RGI_DT */ + _PAD_CFG_STRUCT(GPP_J5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* CNV_RGI_RSP */ + PAD_NC(GPP_J6, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_J7, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_J8, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_J9, 1, PLTRST), /* GPIO */ + + /* ------- GPIO Group GPP_K ------- */ + PAD_CFG_GPO(GPP_K0, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_K1, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_K2, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_K3, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_K4, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_K5, 1, PLTRST), /* GPIO */ + _PAD_CFG_STRUCT(GPP_K6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DDSP_HPDA */ + _PAD_CFG_STRUCT(GPP_K7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DDSP_HPDB */ + _PAD_CFG_STRUCT(GPP_K8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CORE_VID0 */ + _PAD_CFG_STRUCT(GPP_K9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CORE_VID1 */ + PAD_CFG_GPO(GPP_K10, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_K11, NONE), /* GPIO */ + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_I ------- */ + _PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* PMCALERT# */ + _PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DDSP_HPD1 */ + _PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* DDSP_HPD2 */ + _PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DDSP_HPD3 */ + _PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DDSP_HPD4 */ + _PAD_CFG_STRUCT(GPP_I5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPB_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* DDPB_CTRLDATA */ + PAD_NC(GPP_I7, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_I8, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_I9, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_I10, 1, PLTRST), /* GPIO */ + _PAD_CFG_STRUCT(GPP_I11, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* I2C4_SDA */ + _PAD_CFG_STRUCT(GPP_I12, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* I2C4_SCL */ + _PAD_CFG_STRUCT(GPP_I13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB_OC6# */ + _PAD_CFG_STRUCT(GPP_I14, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* I2C5_SCL */ +}; diff --git a/src/mainboard/erying/tgl/hda_verb.c b/src/mainboard/erying/tgl/hda_verb.c new file mode 100644 index 0000000..cb0c3ac --- /dev/null +++ b/src/mainboard/erying/tgl/hda_verb.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek ALC897 */ + 0x10ec0897, /* Vendor ID */ + 0x10ec3000, /* Subsystem ID */ + 15, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x10ec3000), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014020), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19030), + AZALIA_PIN_CFG(0, 0x19, 0x02a1903f), + AZALIA_PIN_CFG(0, 0x1a, 0x01813040), + AZALIA_PIN_CFG(0, 0x1b, 0x02214010), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4024c601), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + /* Tigerlake HDMI */ + 0x80862812, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 2, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x04, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/erying/tgl/ramstage.c b/src/mainboard/erying/tgl/ramstage.c new file mode 100755 index 0000000..a12a048 --- /dev/null +++ b/src/mainboard/erying/tgl/ramstage.c @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <soc/pci_devs.h> +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + // PEG0 - Gen4 NVME + params->CpuPcieRpSlotImplemented[0] = 1; + params->CpuPcieRpAdvancedErrorReporting[0] = 1; + params->CpuPcieRpMaxPayload[0] = 2; + params->CpuPcieRpPeerToPeerMode[0] = 1; + params->CpuPcieRpPtmEnabled[0] = 1; + params->CpuPcieRpLtrEnable[0] = 1; + params->CpuPcieRpPmSci[0] = 1; + params->CpuPcieRpTransmitterHalfSwing[0] = 0; + + // PEG1 - PCI-E x16 + params->CpuPcieRpSlotImplemented[1] = 1; + params->CpuPcieRpAdvancedErrorReporting[1] = 1; + params->CpuPcieRpMaxPayload[1] = 2; + params->CpuPcieRpPeerToPeerMode[1] = 1; + params->CpuPcieRpPtmEnabled[1] = 1; + params->CpuPcieRpLtrEnable[1] = 1; + params->CpuPcieRpPmSci[1] = 1; + params->CpuPcieRpTransmitterHalfSwing[1] = 0; + + // Power management - ASPM is broken even on vendor FW + params->PchLegacyIoLowLatency = 1; + params->PchDmiAspmCtrl = 0; + + // PCH RootPorts + params->PcieRpMaxPayload[4] = 2; // M.2 Gen3 + params->PcieRpPmSci[4] = 1; + // params->PcieRpEnableCpm[4] = 0; + // params->PcieRpL1Substates[4] = 0; + // params->PcieRpAspm[4] = 0; + + params->PcieRpMaxPayload[8] = 1; + params->PcieRpPmSci[8] = 1;// M.2 NGFF + // params->PcieRpEnableCpm[8] = 0; + // params->PcieRpL1Substates[8] = 0; + // params->PcieRpAspm[8] = 0; + + params->PcieRpMaxPayload[10] = 1; // RTL8111 NIC + params->PcieRpPmSci[10] = 1; + // params->PcieRpEnableCpm[10] = 0; + // params->PcieRpL1Substates[10] = 0; + // params->PcieRpAspm[10] = 0; + + params->PcieRpMaxPayload[11] = 1; // PCI-E x1 Gen3 + params->PcieRpPmSci[11] = 1; + // params->PcieRpEnableCpm[11] = 0; + // params->PcieRpL1Substates[11] = 0; + // params->PcieRpAspm[11] = 0; + + // FSP settings + params->CpuPcieRpFunctionSwap = 1; + params->PcieRpFunctionSwap = 0; + params->ITbtPcieTunnelingForUsb4 = 0; + params->PchUsbOverCurrentEnable = 0; + params->RC1pFreqEnable = 1; + params->PavpEnable = 1; + params->CdynmaxClampEnable = 0; + params->PchEspiHostC10ReportEnable = 1; +} diff --git a/src/mainboard/erying/tgl/romstage_fsp_params.c b/src/mainboard/erying/tgl/romstage_fsp_params.c new file mode 100755 index 0000000..cd47786 --- /dev/null +++ b/src/mainboard/erying/tgl/romstage_fsp_params.c @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/meminit.h> +#include <soc/romstage.h> +#include "gpio.h" + +static const struct mb_cfg mem_config = { + .type = MEM_TYPE_DDR4, + .ddr4_config = { .dq_pins_interleaved = true }, +}; + +static const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, +}; + +const bool half_populated = false; + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + // Performance settings + mupd->FspmConfig.HyperThreading = 1; + mupd->FspmConfig.EnableAbove4GBMmio = 1; + mupd->FspmConfig.OcSupport = 1; + mupd->FspmConfig.OcLock = 0; + + // XMP/Memory + mupd->FspmConfig.SpdProfileSelected = 0; // Default profile + mupd->FspmConfig.RefClk = 0; // 133MHz + mupd->FspmConfig.VddVoltage = 1350; // 1.35V (Applicable only with XMP Profile 1) + mupd->FspmConfig.Ratio = 0; // Auto + mupd->FspmConfig.RingDownBin = 0; + mupd->FspmConfig.GearRatio = 0; // Auto + + // iGPU + mupd->FspmConfig.GttSize = 3; // 8MB + mupd->FspmConfig.ApertureSize = 3; // 512MB + mupd->FspmConfig.GtPsmiSupport = 0; + mupd->FspmConfig.IgdDvmt50PreAlloc = 2; // 64MB + + // SoC PCI-Express configuration (4.0) + mupd->FspmConfig.CpuPcieRpPcieSpeed[0] = 0; // Auto + mupd->FspmConfig.CpuPcieRpPcieSpeed[1] = 0; // Auto + mupd->FspmConfig.CpuPcieRpCdrRelock[0] = 1; + mupd->FspmConfig.CpuPcieRpCdrRelock[1] = 1; + mupd->FspmConfig.CpuPcieNewFom[0] = 1; + mupd->FspmConfig.CpuPcieNewFom[1] = 1; + + // DMI (SoC - PCH) Link settings + mupd->FspmConfig.DmiMaxLinkSpeed = 3; + mupd->FspmConfig.DmiAspm = 0; + mupd->FspmConfig.DmiAspmCtrl = 0; + + // FSP Configuration + mupd->FspmConfig.VmxEnable = 1; + mupd->FspmConfig.SmbusEnable = 1; + + // Memory training - based on stock + mupd->FspmConfig.ECT = 1; + mupd->FspmConfig.LCT = 1; + mupd->FspmConfig.SOT = 1; + mupd->FspmConfig.ERDMPRTC2D = 0; + mupd->FspmConfig.RDMPRT = 1; + mupd->FspmConfig.RCVET = 1; + mupd->FspmConfig.JWRL = 1; + mupd->FspmConfig.EWRTC2D = 1; + mupd->FspmConfig.ERDTC2D = 1; + mupd->FspmConfig.WRTC2D = 1; + mupd->FspmConfig.WRVC1D = 1; + mupd->FspmConfig.WRVC1D = 1; + mupd->FspmConfig.DIMMODTT = 1; + mupd->FspmConfig.DIMMRONT = 1; + mupd->FspmConfig.WRDSEQT = 1; + mupd->FspmConfig.WRSRT = 0; + mupd->FspmConfig.RDODTT = 1; + mupd->FspmConfig.RDEQT = 1; + mupd->FspmConfig.RDAPT = 1; + mupd->FspmConfig.RDTC2D = 1; + mupd->FspmConfig.WRVC2D = 1; + mupd->FspmConfig.RDVC2D = 1; + mupd->FspmConfig.CMDVC = 1; + mupd->FspmConfig.MrcSafeConfig = 0; + mupd->FspmConfig.LpDdrDqDqsReTraining = 1; + mupd->FspmConfig.SafeMode = 0; + mupd->FspmConfig.OverrideDowngradeForMixedMemory = 0; + mupd->FspmConfig.MemTestOnWarmBoot = 1; + mupd->FspmConfig.DdrFreqLimit = 2933; // Setting to auto for now. + mupd->FspmConfig.SaGv = 0; + // mupd->FspmConfig.RetrainOnFastFail = 1; - Commenting out for now, can't find an equivalent in FSP-M headers. + mupd->FspmConfig.NModeSupport = 1; // Board type is 1N (1DPC). + mupd->FspmConfig.RhPrevention = 0; + mupd->FspmConfig.RefreshWm = 1; + mupd->FspmConfig.ExitOnFailure = 1; + + memcfg_init(mupd, &mem_config, &spd_info, half_populated); + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/80853?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e Gerrit-Change-Number: 80853 Gerrit-PatchSet: 1 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: drivers/mrc_cache: Deselect MRC_CACHE_USING_MRC_VERSION by default
by Felix Held (Code Review) 01 Mar '24

01 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80693?usp=email ) Change subject: drivers/mrc_cache: Deselect MRC_CACHE_USING_MRC_VERSION by default ...................................................................... drivers/mrc_cache: Deselect MRC_CACHE_USING_MRC_VERSION by default EDK2 version binding is irrelevant for MRC_CACHE_USING_MRC_VERSION as this is SoC FSP choice to enable/disable this feature. So deselect the option and leave it to SoC codes to enable it depending on needs. Change-Id: I84fdcfbf3c833a7ccb259a1a1d4be0bcfe291dc3 Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80693 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/mrc_cache/Kconfig 1 file changed, 1 insertion(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/drivers/mrc_cache/Kconfig b/src/drivers/mrc_cache/Kconfig index e12a3a5..afe1dc0 100644 --- a/src/drivers/mrc_cache/Kconfig +++ b/src/drivers/mrc_cache/Kconfig @@ -56,14 +56,12 @@ config MRC_CACHE_USING_MRC_VERSION bool - default y if UDK_VERSION >= 202302 default n help Use the MRC version info from FSP extended header to store the MRC cache data. This method relies on the FSP_PRODUCER_DATA_TABLES belongs to the `FspProducerDataHeader.h`file to get the MRC version. - Intel FSP built with EDK2 version 202302 onwards has support to retrieve the - MRC version by directly parsing the binary. + Supported platform can retrieve the MRC version by directly parsing the binary. endif # CACHE_MRC_SETTINGS -- To view, visit https://review.coreboot.org/c/coreboot/+/80693?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I84fdcfbf3c833a7ccb259a1a1d4be0bcfe291dc3 Gerrit-Change-Number: 80693 Gerrit-PatchSet: 7 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: merged

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coreboot-gerrit March 2024