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Hello Felix Singer,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: mb/erying/tgl: Add blobs necessary for platform bring-up
......................................................................
mb/erying/tgl: Add blobs necessary for platform bring-up
Flash Descriptor and Management Engine blobs extracted from stock.
Microcodes from public GitHub repository, as Intel doesn't carry
microcode for D0 stepping in their tree.
Change-Id: I9ee9e031969b477d2d9f63f7e49a113bd4380f91
Signed-off-by: Alicja Michalska <ahplka19(a)gmail.com>
---
A mainboard/erying/tgl/cpu806D0_platC2_ver00000054_2021-05-07_PRD_B0F9E245.bin
A mainboard/erying/tgl/cpu806D1_platC2_ver00000046_2023-02-27_PRD_08E6188A.bin
A mainboard/erying/tgl/fd.bin
A mainboard/erying/tgl/me.bin
4 files changed, 0 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/blobs refs/changes/52/80852/2
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Change subject: mb/erying/tgl: Add blobs necessary for platform bring-up.
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/blobs/+/80852/comment/91d9848f_4b24fc07 :
PS1, Line 7: .
Remove, don't end the title with a period
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Change subject: mb/erying/tgl: Add blobs necessary for platform bring-up.
......................................................................
Patch Set 1: Verified+1
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Change subject: mb/erying/tgl: Add blobs necessary for platform bring-up.
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/sifive/fu740: Add FU740 SOC
......................................................................
Patch Set 10: Code-Review+1
(6 comments)
File src/soc/sifive/fu740/Kconfig:
https://review.coreboot.org/c/coreboot/+/76689/comment/724b2095_e03d2576 :
PS10, Line 28: # working HART uses U7 core
RISCV_WORKING_HARTID is set to 0, which is S7?
https://review.coreboot.org/c/coreboot/+/76689/comment/4aea5acd_9c9dd8bd :
PS10, Line 47: default 0 # use S7 core as default hart
deliberate use of S7 for coreboot?
File src/soc/sifive/fu740/clint.c:
https://review.coreboot.org/c/coreboot/+/76689/comment/42655258_d666286f :
PS10, Line 17: write32((void *)(FU740_CLINT + 4 * (uintptr_t)hartid), !!val);
use write32p?
File src/soc/sifive/fu740/gpio.c:
https://review.coreboot.org/c/coreboot/+/76689/comment/9e1a6cd4_dae2dfdf :
PS10, Line 33: uint32_t output_val = read32((void *)SIFIVE_GPIO_OUTPUT_VAL);
use read32p/write32p?
File src/soc/sifive/fu740/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/76689/comment/b6c036f9_f0dcc5ea :
PS10, Line 22: //REGION(opensbi, FU740_DRAM, 256K, 4K)
comment not needed?
File src/soc/sifive/fu740/spi.c:
https://review.coreboot.org/c/coreboot/+/76689/comment/01d4332c_98ba2162 :
PS10, Line 186: //sckmode.raw_bits = 0;
why is this code commented here? delete it?
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80579?usp=email )
Change subject: drivers/intel/fsp: Work around multi socket Xeon-SP pipe init bug
......................................................................
Patch Set 4:
(2 comments)
File src/arch/x86/car.ld:
https://review.coreboot.org/c/coreboot/+/80579/comment/86e5a202_df8656c4 :
PS4, Line 15:
> To be simple, maybe we could use REGION(fspm_heap ...) here and discard the .car. […]
Done
https://review.coreboot.org/c/coreboot/+/80579/comment/39fe7450_469a4c69 :
PS4, Line 118: _fspm_heap = .;
> Can't this be simplified using `REGION(fspm_heap, . […]
Done
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Hello Andrey Petrov, Chen, Gang C, Christian Walter, Felix Singer, Jincheng Li, Johnny Lin, Jérémy Compostella, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, Ray Ni, Ronak Kanabar, Shuo Liu, Tim Chu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80579?usp=email
to look at the new patch set (#5).
The following approvals got outdated and were removed:
Code-Review+1 by Felix Singer, Code-Review+1 by Nico Huber, Code-Review+1 by Paul Menzel, Verified+1 by build bot (Jenkins)
Change subject: drivers/intel/fsp: Work around multi socket Xeon-SP pipe init bug
......................................................................
drivers/intel/fsp: Work around multi socket Xeon-SP pipe init bug
Starting with Intel CPX there is a bug in the reference code during
the Pipe init. This code synchronises the CAR between sockets in FSP-M.
This code implicitly assumes that the top of FSP heap is FspStackBase +
FspStackSize and the bottom is the bottom of CAR.
Work around this issue by making that implicit assumption done in FSP
explicit in the coreboot linker script and allocation.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I38a4f4b7470556e528a1672044c31f8bd92887d4
---
M src/arch/x86/car.ld
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/memory_init.c
M src/soc/intel/xeon_sp/cpx/Kconfig
M src/soc/intel/xeon_sp/spr/Kconfig
5 files changed, 26 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/80579/5
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Change subject: mb/emulation/qemu-riscv: Change to -bios option
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
can you also add the -pflash parameter to the "make qemu" target?
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