coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: mb/emulation/qemu-riscv: Change to -bios option
by Maximilian Brune (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Arthur Heymans, Philipp Hug. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80746?usp=email ) Change subject: mb/emulation/qemu-riscv: Change to -bios option ...................................................................... Patch Set 5: (1 comment) File src/mainboard/emulation/qemu-riscv/cbmem.c: https://review.coreboot.org/c/coreboot/+/80746/comment/2838cc8e_8bfca49a : PS5, Line 10: return (uintptr_t)_dram + CONFIG_DRAM_SIZE_MB * MiB; > Can use probing here instead of hard-coding If you rebase CB:36486 on top of upstream main, then I could rebase on top of that and remove the hard code stuff. -- To view, visit https://review.coreboot.org/c/coreboot/+/80746?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d Gerrit-Change-Number: 80746 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 01 Mar 2024 02:56:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Drop SPI_BASE from _CRS
by Shuo Liu (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80795?usp=email ) Change subject: soc/intel/xeon_sp: Drop SPI_BASE from _CRS ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80795/comment/938587ff_c71d3b4b : PS1, Line 10: hidden the fast_spi driver will generate the _CRS marking the BAR Hidden by HW? or not included in uncore _CRS? -- To view, visit https://review.coreboot.org/c/coreboot/+/80795?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I150397a7ac5d60719f327f6ac6480a38fe295c32 Gerrit-Change-Number: 80795 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 01 Mar 2024 02:53:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/nissa/var/gothrax: Add probe and GPIO config for touchpanel
by Yunlong Jia (Code Review) 01 Mar '24

01 Mar '24

Yunlong Jia has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80850?usp=email ) Change subject: mb/google/nissa/var/gothrax: Add probe and GPIO config for touchpanel ...................................................................... mb/google/nissa/var/gothrax: Add probe and GPIO config for touchpanel Add FW_CONFIG probe to separate touch panel settings. TOUCH_PANEL_ENABLE/TOUCH_PANEL_DISABLE Use different gpio tables based on the value of TOUCH_PANEL. BUG=b:325987249 TEST=emerge-nissa coreboot and run in DUT Change-Id: I23c62406a932815ff1cfafe05b70468b1f9cca54 Signed-off-by: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> --- M src/mainboard/google/brya/variants/gothrax/gpio.c M src/mainboard/google/brya/variants/gothrax/overridetree.cb 2 files changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/80850/1 diff --git a/src/mainboard/google/brya/variants/gothrax/gpio.c b/src/mainboard/google/brya/variants/gothrax/gpio.c index 0bf1b52..71a211e 100644 --- a/src/mainboard/google/brya/variants/gothrax/gpio.c +++ b/src/mainboard/google/brya/variants/gothrax/gpio.c @@ -80,6 +80,13 @@ PAD_CFG_GPO(GPP_H20, 1, DEEP), }; +static const struct pad_config romstage_gpio_table_nontp[] = { + /* H12 : UART0_RTS# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H12, 1, DEEP), + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 1, DEEP), +}; + const struct pad_config *variant_gpio_override_table(size_t *num) { *num = ARRAY_SIZE(override_gpio_table); @@ -94,6 +101,10 @@ const struct pad_config *variant_romstage_gpio_table(size_t *num) { + if (fw_config_probe(FW_CONFIG(TOUCH_PANEL, TOUCH_PANEL_DISABLE))) { + *num = ARRAY_SIZE(romstage_gpio_table_nontp); + return romstage_gpio_table_nontp; + } *num = ARRAY_SIZE(romstage_gpio_table); return romstage_gpio_table; } diff --git a/src/mainboard/google/brya/variants/gothrax/overridetree.cb b/src/mainboard/google/brya/variants/gothrax/overridetree.cb index b36ff07..77be31c 100644 --- a/src/mainboard/google/brya/variants/gothrax/overridetree.cb +++ b/src/mainboard/google/brya/variants/gothrax/overridetree.cb @@ -24,6 +24,10 @@ option WFC_PRESENT 0 option WFC_ABSENT 1 end + field TOUCH_PANEL 9 + option TOUCH_PANEL_ENABLE 0 + option TOUCH_PANEL_DISABLE 1 + end end chip soc/intel/alderlake @@ -226,7 +230,9 @@ register "generic.enable_delay_ms" = "6" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" - device i2c 0x10 on end + device i2c 0x10 on + probe TOUCH_PANEL TOUCH_PANEL_ENABLE + end end end device ref i2c2 on -- To view, visit https://review.coreboot.org/c/coreboot/+/80850?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I23c62406a932815ff1cfafe05b70468b1f9cca54 Gerrit-Change-Number: 80850 Gerrit-PatchSet: 1 Gerrit-Owner: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: lib/rtc: Add sanity check for time and date
by Felix Singer (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Werner Zeh. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54913?usp=email ) Change subject: lib/rtc: Add sanity check for time and date ...................................................................... Patch Set 3: (1 comment) File src/lib/rtc.c: https://review.coreboot.org/c/coreboot/+/54913/comment/9bad8249_c94bce73 : PS3, Line 129: month == 2 > First leap year and we already hit this off-by-one error 😊 […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/54913?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a381d445c894eee4f82b50fe86dad22cc587605 Gerrit-Change-Number: 54913 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Jan Dabros <jsd(a)semihalf.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 01 Mar 2024 01:33:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/nissa/var/glassway: Select drivers for gpio-keys and GL9750
by Daniel Peng (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. Daniel Peng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80766?usp=email ) Change subject: mb/google/nissa/var/glassway: Select drivers for gpio-keys and GL9750 ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80766/comment/aa54df2f_1c73c6a2 : PS2, Line 7: Select drivers for gpio-keys and Genesys Logic GL9750 > please shorten the title Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80766?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id7e358d2f472cd435d2828f6256f5ee91dfb8ef6 Gerrit-Change-Number: 80766 Gerrit-PatchSet: 3 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 01 Mar 2024 01:33:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/nissa/var/glassway: Select drivers for gpio-keys and GL9750
by Daniel Peng (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Daniel Peng, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. Hello Eric Lai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Shawn Ku, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80766?usp=email to look at the new patch set (#3). Change subject: mb/google/nissa/var/glassway: Select drivers for gpio-keys and GL9750 ...................................................................... mb/google/nissa/var/glassway: Select drivers for gpio-keys and GL9750 Add 2 configuration on Kconfig for glassway. - DRIVERS_GENERIC_GPIO_KEYS - DRIVERS_GENESYSLOGIC_GL9750 BUG=b:319071869 BRANCH=firmware-nissa-15217.B TEST=Local build successfully and boot to OOBE normally. Change-Id: Id7e358d2f472cd435d2828f6256f5ee91dfb8ef6 Signed-off-by: Daniel Peng <Daniel_Peng(a)pegatron.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/80766/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/80766?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id7e358d2f472cd435d2828f6256f5ee91dfb8ef6 Gerrit-Change-Number: 80766 Gerrit-PatchSet: 3 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: payloads/depthcharge: Add DEPTHCHARGE_REPO and DEPTHCHARGE_BRANCH
by Zhixing Ma (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Cliff Huang, Hannah Williams, Martin L Roth, Stefan Reinauer, Subrata Banik. Zhixing Ma has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80726?usp=email ) Change subject: payloads/depthcharge: Add DEPTHCHARGE_REPO and DEPTHCHARGE_BRANCH ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/80726?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icca10aa770b7b7a6e010f58bcf1e4f0a3401681a Gerrit-Change-Number: 80726 Gerrit-PatchSet: 2 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Mar 2024 01:32:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: treewide: Change I2C/SMBUS master/slave to controller/target
by Yidi Lin (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Arthur Heymans, Caveh Jalali, Cliff Huang, Felix Singer, Julius Werner, Martin L Roth, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77098?usp=email ) Change subject: treewide: Change I2C/SMBUS master/slave to controller/target ...................................................................... Patch Set 5: (2 comments) File src/southbridge/intel/ibexpeak/smbus.c: https://review.coreboot.org/c/coreboot/+/77098/comment/13f8af8a_ba99734d : PS5, Line 20: Slave Target File src/southbridge/intel/lynxpoint/smbus.c: https://review.coreboot.org/c/coreboot/+/77098/comment/496a7f1d_74c63d81 : PS5, Line 20: Slave Target -- To view, visit https://review.coreboot.org/c/coreboot/+/77098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6c141fa4322de9e9ed208589f591560fed609825 Gerrit-Change-Number: 77098 Gerrit-PatchSet: 5 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 01 Mar 2024 01:23:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel: Add definition of D0 stepping for TigerLake Halo
by Alicja Michalska (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Nick Vaccaro, Subrata Banik. Alicja Michalska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80849?usp=email ) Change subject: soc/intel: Add definition of D0 stepping for TigerLake Halo ...................................................................... soc/intel: Add definition of D0 stepping for TigerLake Halo Change-Id: Ic080ffe7912ad71c77af09d2f3d1d9b08d9ffac8 Signed-off-by: Alicja Michalska <ahplka19(a)gmail.com> --- M src/include/cpu/intel/cpu_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/tigerlake/bootblock/report_platform.c 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/80849/1 diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index d74cf1e..ddb4e54 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -46,6 +46,7 @@ #define CPUID_COMETLAKE_H_S_10_2_Q0 0xa0655 #define CPUID_TIGERLAKE_A0 0x806c0 #define CPUID_TIGERLAKE_B0 0x806c1 +#define CPUID_TIGERLAKE_P0 0x806d0 #define CPUID_TIGERLAKE_R0 0x806d1 #define CPUID_SAPPHIRERAPIDS_SP_A 0x806f0 #define CPUID_SAPPHIRERAPIDS_SP_B 0x806f1 diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index bd43545..3cff621 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -71,6 +71,7 @@ { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_Q0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_TIGERLAKE_A0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_TIGERLAKE_B0, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_TIGERLAKE_P0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_TIGERLAKE_R0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_A0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_B0, CPUID_EXACT_MATCH_MASK }, diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index 1ecaf77..137e2d5 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -25,6 +25,7 @@ } cpu_table[] = { { CPUID_TIGERLAKE_A0, "Tigerlake A0" }, { CPUID_TIGERLAKE_B0, "Tigerlake B0" }, + { CPUID_TIGERLAKE_B0, "Tigerlake P0" }, { CPUID_TIGERLAKE_R0, "Tigerlake R0" }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/80849?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic080ffe7912ad71c77af09d2f3d1d9b08d9ffac8 Gerrit-Change-Number: 80849 Gerrit-PatchSet: 1 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/intel/tigerlake: Add IRQ mapping for PEG PCI-E ports
by Alicja Michalska (Code Review) 01 Mar '24

01 Mar '24

Alicja Michalska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80848?usp=email ) Change subject: soc/intel/tigerlake: Add IRQ mapping for PEG PCI-E ports ...................................................................... soc/intel/tigerlake: Add IRQ mapping for PEG PCI-E ports ACPI _PRT method was missing from PEG (SoC PCI-E) links, resulting in OS complaining about interrupt routing. 'pcieport 0000:00:06.0: can't derive routing for PCI INT A' 'nvme 0000:04:00.0: PCI INT A: not connected' 'Interrupt: pin A routed to IRQ -2147483648' TEST=Boot Linux and Windows 10 on TGL-H platform with PEG0/PEG1 populated with PCI-E devices - Radeon RX 7800XT and Kingston KC3000 NVME SSD. Check logs and stability while running 3D application and disk benchmark at the same time. Change-Id: If102522efa1a67b362b14d859d9e27a37bad85a4 Signed-off-by: Alicja Michalska <ahplka19(a)gmail.com> --- M src/soc/intel/tigerlake/acpi/pcie.asl 1 file changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/80848/1 diff --git a/src/soc/intel/tigerlake/acpi/pcie.asl b/src/soc/intel/tigerlake/acpi/pcie.asl index a25335c..86d53fe 100644 --- a/src/soc/intel/tigerlake/acpi/pcie.asl +++ b/src/soc/intel/tigerlake/acpi/pcie.asl @@ -115,22 +115,70 @@ Device (PEG0) { Name (_ADR, 0x00060000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } } #if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H) Device (PEG1) { Name (_ADR, 0x00010000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } } Device (PEG2) { Name (_ADR, 0x00010001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } } Device (PEG3) { Name (_ADR, 0x00010002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/80848?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If102522efa1a67b362b14d859d9e27a37bad85a4 Gerrit-Change-Number: 80848 Gerrit-PatchSet: 1 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-MessageType: newchange

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