coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

1 participants
3667 discussions

[XS] Change in coreboot[main]: soc/intel/xeon_sp: Drop SPI_BASE_ADDRESS from _CRS
by Patrick Rudolph (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80795?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Drop SPI_BASE_ADDRESS from _CRS ...................................................................... soc/intel/xeon_sp: Drop SPI_BASE_ADDRESS from _CRS Drop SPI_BASE_ADDRESS since this address is just a regular BAR on the SPI PCI device. In case the PCI device is hidden in PCI config space the fast_spi driver will generate the _CRS and thus mark the SPI_BASE_ADDRESS as reserved. Thus there's no need to include it unconditionally in the xeon-sp host bridge for socket 0. Change-Id: I150397a7ac5d60719f327f6ac6480a38fe295c32 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/cpx/soc_acpi.c M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/soc/intel/xeon_sp/spr/soc_acpi.c 3 files changed, 0 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/80795/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80795?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I150397a7ac5d60719f327f6ac6480a38fe295c32 Gerrit-Change-Number: 80795 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[main]: soc/intel/xeon_sp: Drop SPI_BASE_ADDRESS from _CRS
by Patrick Rudolph (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80851?usp=email ) Change subject: soc/intel/xeon_sp: Drop SPI_BASE_ADDRESS from _CRS ...................................................................... soc/intel/xeon_sp: Drop SPI_BASE_ADDRESS from _CRS Drop SPI_BASE_ADDRESS since this address is just a regular BAR on the SPI PCI device. In case the PCI device is hidden in PCI config space the fast_spi driver will generate the _CRS and thus mark the SPI_BASE_ADDRESS as reserved. Thus there's no need to include it unconditionally in the xeon-sp host bridge for socket 0. hange-Id: I150397a7ac5d60719f327f6ac6480a38fe295c32 Change-Id: I54ae5d098a94e53204f132ec19eeab56a58734b2 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/cpx/soc_acpi.c M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/soc/intel/xeon_sp/spr/soc_acpi.c 3 files changed, 0 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/80851/1 diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index 8b24ba2..93b4c60 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -89,9 +89,6 @@ if (stack == 0) { acpigen_resource_dword(0, 0xc, 3, 0, VGA_MMIO_BASE, VGA_MMIO_LIMIT, 0x0, VGA_MMIO_SIZE); - acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS, - (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, - SPI_BASE_SIZE); } /* Mem32 resource */ diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 2e2b14a..247d1dd 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -111,9 +111,6 @@ if (socket == 0 && stack == 0) { acpigen_resource_dword(0, 0xc, 3, 0, VGA_MMIO_BASE, VGA_MMIO_LIMIT, 0x0, VGA_MMIO_SIZE); - acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS, - (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, - SPI_BASE_SIZE); } /* Mem32 resource */ diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c index ca1cdf9..42927c0 100644 --- a/src/soc/intel/xeon_sp/spr/soc_acpi.c +++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c @@ -107,9 +107,6 @@ if (socket == 0 && stack == 0) { acpigen_resource_dword(0, 0xc, 3, 0, VGA_MMIO_BASE, VGA_MMIO_LIMIT, 0x0, VGA_MMIO_SIZE); - acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS, - (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, - SPI_BASE_SIZE); } /* Mem32 resource */ -- To view, visit https://review.coreboot.org/c/coreboot/+/80851?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I54ae5d098a94e53204f132ec19eeab56a58734b2 Gerrit-Change-Number: 80851 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: soc/intel/xeon_sp: Add ACPI names
by Patrick Rudolph (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80794?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Add ACPI names ...................................................................... soc/intel/xeon_sp: Add ACPI names Prepare for SSDT PCI domain generation by providing the domain names using the 'device' property of each domain device. The 'device' property is being used since change Ic4cc81d198fb88300394055682a3954bf22db570 to identify the domain and by coincidence the name can also be used to generate the ACPI name. The ACPI names match the existing names defined in DSDT and thus allow to generate proper SSDT code. Change-Id: I4353db33e7ac98db41728bcf61ee01e21433dded Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/spr/chip.c M src/soc/intel/xeon_sp/spr/ioat.c 6 files changed, 47 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/80794/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80794?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4353db33e7ac98db41728bcf61ee01e21433dded Gerrit-Change-Number: 80794 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[main]: soc/intel/tigerlake: Add IRQ mapping for PEG PCI-E ports
by Subrata Banik (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Alicja Michalska, Nick Vaccaro. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80848?usp=email ) Change subject: soc/intel/tigerlake: Add IRQ mapping for PEG PCI-E ports ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80848?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If102522efa1a67b362b14d859d9e27a37bad85a4 Gerrit-Change-Number: 80848 Gerrit-PatchSet: 1 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 01 Mar 2024 05:58:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: mb/google/nissa/var/glassway: Select drivers for gpio-keys and GL9750
by Subrata Banik (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Daniel Peng, Kapil Porwal, Nick Vaccaro, Paul Menzel. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80766?usp=email ) Change subject: mb/google/nissa/var/glassway: Select drivers for gpio-keys and GL9750 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80766?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id7e358d2f472cd435d2828f6256f5ee91dfb8ef6 Gerrit-Change-Number: 80766 Gerrit-PatchSet: 3 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Fri, 01 Mar 2024 05:58:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: mb/google/nissa/var/gothrax: Add probe and GPIO config for touchpanel
by Subrata Banik (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Eric Lai, Kapil Porwal, Nick Vaccaro, Yunlong Jia. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80850?usp=email ) Change subject: mb/google/nissa/var/gothrax: Add probe and GPIO config for touchpanel ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/gothrax/gpio.c: https://review.coreboot.org/c/coreboot/+/80850/comment/dfbd1b6c_a002c8eb : PS1, Line 83: nontp nit: tp_disable? -- To view, visit https://review.coreboot.org/c/coreboot/+/80850?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I23c62406a932815ff1cfafe05b70468b1f9cca54 Gerrit-Change-Number: 80850 Gerrit-PatchSet: 1 Gerrit-Owner: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 01 Mar 2024 05:57:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: cpu/x86/smm/smm_module_loader.c: Pass full SMRAM region info to SMM r...
by Shuo Liu (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Angel Pons, Arthur Heymans, Benjamin Doron, Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Jeff Daly, Johnny Lin, Jérémy Compostella, Lean Sheng Tan, Matt DeVillier, Patrick Rudolph, Tim Chu, Vanessa Eusebio. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80703?usp=email ) Change subject: cpu/x86/smm/smm_module_loader.c: Pass full SMRAM region info to SMM runtime ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80703/comment/6642453a_c5c96b25 : PS2, Line 17: integrity of the S3 resume path. I suppose the default region_overlaps_handler() cannot achieve this at the moment. Maybe this could be put into a separate patch. https://review.coreboot.org/c/coreboot/+/80703/comment/ab14c4da_87c98fe0 : PS2, Line 19: The consequences to overwriting the chipset-specific area are undefined. Could you please specify the definition here for 'chipset-specific' area? -- To view, visit https://review.coreboot.org/c/coreboot/+/80703?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd9ed34fcfd77a4236b5cf122747a6718ce9c91f Gerrit-Change-Number: 80703 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 01 Mar 2024 04:10:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: soc/intel/xeon_sp: Encode domain type
by Shuo Liu (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80792?usp=email ) Change subject: soc/intel/xeon_sp: Encode domain type ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: It's good we could move ahead into this direction (compatible for GNR changes). Let us move ahead and achieve to merge with priority. -- To view, visit https://review.coreboot.org/c/coreboot/+/80792?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4cc81d198fb88300394055682a3954bf22db570 Gerrit-Change-Number: 80792 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 01 Mar 2024 03:48:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: soc/intel/xeon_sp: Add ACPI names
by Shuo Liu (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80794?usp=email ) Change subject: soc/intel/xeon_sp: Add ACPI names ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: It's good we could move ahead into this direction (compatible for GNR changes). Let us move ahead and achieve to merge with priority. -- To view, visit https://review.coreboot.org/c/coreboot/+/80794?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4353db33e7ac98db41728bcf61ee01e21433dded Gerrit-Change-Number: 80794 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 01 Mar 2024 03:47:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: arch/riscv: Add SMP support for exception handler
by Maximilian Brune (Code Review) 01 Mar '24

01 Mar '24

Attention is currently required from: Arthur Heymans, Philipp Hug, Xiang W, ron minnich. Maximilian Brune has uploaded a new patch set (#6) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/68841?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: arch/riscv: Add SMP support for exception handler ...................................................................... arch/riscv: Add SMP support for exception handler Change-Id: Ia1f97b82e329f6358061072f98278cf56b503618 Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org> --- M src/arch/riscv/payload.c M src/arch/riscv/trap_util.S 2 files changed, 116 insertions(+), 111 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/68841/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/68841?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia1f97b82e329f6358061072f98278cf56b503618 Gerrit-Change-Number: 68841 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Xiang W <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Xiang W <wxjstz(a)126.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2024