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Change subject: nb/intel/sandybridge/raminit: Update PM_DLL_CONFIG to match MRC.bin
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79759/comment/80e09273_3cb4451a :
PS2, Line 9: A register dump between native and MRC.bin raminit showed
: a difference in the PM_DLL_CONFIG register.
: Use the same value as MRC.bin uses.
> Could be two lines, but feel free to ignore.
Done
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Hello Angel Pons, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: nb/intel/sandybridge/raminit: Add tCPDED corner case
......................................................................
nb/intel/sandybridge/raminit: Add tCPDED corner case
tCPDED is always 1, except for steppings earlier than Sandy Bridge D0.
Reduces the differences to MRC.bin.
Tested on Lenovo X220: Still boots and runs fine.
Change-Id: I5294173c02f06c601fdb13ed785ee33d7a4e3eca
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/northbridge/intel/sandybridge/raminit_common.c
1 file changed, 5 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/79762/3
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Hello Angel Pons, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: nb/intel/sandybridge/raminit: Only write register on Ivy Bridge
......................................................................
nb/intel/sandybridge/raminit: Only write register on Ivy Bridge
Only write register WMM_READ_CONFIG on Ivy Bridge as it's
reserved on Sandy Bridge.
Tested on Lenovo X220: Still boots and runs fine.
Change-Id: Ie14ea06d744b1a8368d32803c6c1ccfb1262532e
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/northbridge/intel/sandybridge/raminit_common.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/79761/3
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Hello Angel Pons, Arthur Heymans, Felix Singer, Maximilian Brune, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/79759?usp=email
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Change subject: nb/intel/sandybridge/raminit: Update PM_DLL_CONFIG to match MRC.bin
......................................................................
nb/intel/sandybridge/raminit: Update PM_DLL_CONFIG to match MRC.bin
A register dump between native and MRC.bin raminit showed a difference
in the PM_DLL_CONFIG register. Use the same value as MRC.bin uses.
Tested on Lenovo X220: Still boots and works fine.
Change-Id: Iaf6334814c5748e5a3691a572213f433c79f382d
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/northbridge/intel/sandybridge/raminit_common.c
1 file changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/79759/3
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Hello Alexander Couzens, build bot (Jenkins),
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The following approvals got outdated and were removed:
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Change subject: cpu/intel/model_206ax: Allow to configure VR settings
......................................................................
cpu/intel/model_206ax: Allow to configure VR settings
Allow to set board specific CPU voltage regulator settings.
The VR12 compatible voltage regulator for the CPU can be configured
by two MSRs. Currently a default value is applied, which mimics the
Intel reference code and is what the BWG suggest. However most board
vendors fill in the actual VR parameters to support OC or ULV board
variants.
When the mainboard design is too different from the Intel reference
design, not updating the VR settings might result in:
- unstable system behaviour
- limited turbo performance
- excessive battery drain
- no over-clocking capability
This patch adds support to set the board specific current limit for
Icc and Igfx.
It also allows to adjust PSI1, PSI2 and PSI3, which are powerstates
used by the VR, that consume less energy when the system is idle.
Test on Lenovo X220 with full CPU load after 1 minute, compared to
previous code with default settings:
- Limiting PP0 max current below Iccmax results in less CPU performance.
RAPL readings show that less power is drawn over time.
- Limiting PP0 max current to Iccmax results in equal CPU performance.
RAPL readings show that the same power is drawn over time.
- Setting the PP0 max current to a value >> Iccmax results in equal CPU
performance. RAPL readings show that the same power is drawn over
time.
- Updating the MSR at runtime has no effect.
Change-Id: I59edab47fc4fbe0240e1dd7d25647f7549b4def2
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/cpu/intel/model_206ax/chip.h
M src/cpu/intel/model_206ax/model_206ax_init.c
M src/mainboard/lenovo/x220/devicetree.cb
3 files changed, 102 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/81597/2
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Change subject: mb/google/corsola/var/wugtrio: Enable the MIPI panel KD_KD101NE3_40TI
......................................................................
Patch Set 2:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81585/comment/aaa085cd_5caffb20 :
PS1, Line 7: for Wugtrio
> Please put it into the prefix.
Done
File src/mainboard/google/corsola/Makefile.mk:
https://review.coreboot.org/c/coreboot/+/81585/comment/093ebb3c_b5b78e80 :
PS1, Line 29:
> remove blank line
Done
File src/mainboard/google/corsola/panel_wugtrio.c:
https://review.coreboot.org/c/coreboot/+/81585/comment/e7cf4323_d28b2bfb :
PS1, Line 15:
> remove blank line
Done
https://review.coreboot.org/c/coreboot/+/81585/comment/aaae0f65_f45316f2 :
PS1, Line 23: mdelay(15);
> Is that mentioned in the spec?
Yes,it is based on the power on sequence of the spec KD101NE3-40TI-A003 _Pre SPEC_20231218.pdf
https://review.coreboot.org/c/coreboot/+/81585/comment/49ef9832_008856f5 :
PS1, Line 30: KingDisplay
> K&D Technology […]
Done
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