coreboot-gerrit March 2024

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[XS] Change in coreboot[main]: mb/dell/optiplex_9020: Fix SATA port maps
by Máté Kukri (Code Review) 31 Mar '24

31 Mar '24

Attention is currently required from: Arthur Heymans, Felix Singer, Máté Kukri, Paul Menzel. Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81550?usp=email ) Change subject: mb/dell/optiplex_9020: Fix SATA port maps ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/81550?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32cb236b8f8140fba4a04c23161363d21741dcbc Gerrit-Change-Number: 81550 Gerrit-PatchSet: 2 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 31 Mar 2024 10:53:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: cpu/intel/model_206ax: Allow to configure VR settings
by Patrick Rudolph (Code Review) 31 Mar '24

31 Mar '24

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81597?usp=email ) Change subject: cpu/intel/model_206ax: Allow to configure VR settings ...................................................................... cpu/intel/model_206ax: Allow to configure VR settings Allow to set board specific CPU voltage regulator settings. The VR12 compatible voltage regulator for the CPU can be configured by two MSRs. Currently a default value is applied, which mimics the Intel reference code and is what the BWG suggest. However most board vendors fill in the actual VR parameters to support OC or ULV board variants. When the mainboard design is too different from the Intel reference design, not updating the VR settings might result in: - unstable system behaviour - limited turbo performance - excessive battery drain - no over-clocking capability This patch adds support to set the board specific current limit for Icc and Igfx. It also allows to adjust PSI1, PSI2 and PSI3, which are powerstates used by the VR, that consume less energy when the system is idle. Test on Lenovo X220 with full CPU load after 1 minute, compared to previous code with default settings: - Limiting PP0 max current below Iccmax results in less CPU performance. RAPL readings show that less power is drawn over time. - Limiting PP0 max current to Iccmax results in equal CPU performance. RAPL readings show that the same power is drawn over time. - Setting the PP0 max current to a value >> Iccmax results in equal CPU performance. RAPL readings show that the same power is drawn over time. - Updating the MSR at runtime has no effect. Change-Id: I59edab47fc4fbe0240e1dd7d25647f7549b4def2 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/model_206ax/chip.h M src/cpu/intel/model_206ax/model_206ax_init.c M src/mainboard/lenovo/x220/devicetree.cb 3 files changed, 100 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/81597/1 diff --git a/src/cpu/intel/model_206ax/chip.h b/src/cpu/intel/model_206ax/chip.h index 57e145e..9080e2f 100644 --- a/src/cpu/intel/model_206ax/chip.h +++ b/src/cpu/intel/model_206ax/chip.h @@ -14,12 +14,40 @@ CPU_ACPI_C7S, }; +/* VR12 PSI codes */ +enum vr12_phases { + VR12_KEEP_DEFAULT = 0, /* For device-trees missing the setting */ + VR12_ALL_PHASES, + VR12_2_PHASES, + VR12_1_PHASE, + VR12_LIGHT_LOAD, +}; + +/* VR12 power state listing */ +enum vr12_psi { + VR12_PSI1 = 0, + VR12_PSI2, + VR12_PSI3, + VR12_PSI_MAX, +}; + +struct psi_state { + enum vr12_phases phases; + int current; /* In Amps */ +}; + struct cpu_intel_model_206ax_config { enum cpu_acpi_level acpi_c1; enum cpu_acpi_level acpi_c2; enum cpu_acpi_level acpi_c3; int tcc_offset; /* TCC Activation Offset */ + int pp0_current_limit; /* Primary Plane Current Limit (Icc) in Amps */ + int pp1_current_limit; /* Secondary Plane Current Limit (IAXG) in Amps */ + + /* PSI states only have an effect when in Package C3 or higher */ + struct psi_state pp0_psi[3]; /* Power states for Primary Plane (Icc) */ + struct psi_state pp1_psi[3]; /* Power states for Secondary Plane (IAXG) */ }; #endif /* __CPU_INTEL_MODEL_206AX_CHIP_H__ */ diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index d9340ff..cdec3a6 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -156,8 +156,9 @@ } } -static void configure_c_states(void) +static void configure_c_states(struct device *dev) { + struct cpu_intel_model_206ax_config *conf = dev->upstream->dev->chip_info; msr_t msr; msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); @@ -202,20 +203,70 @@ msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D; wrmsr(MSR_PKGC7_IRTL, msr); - /* Primary Plane Current Limit */ + /* Primary Plane Current Limit (Icc) */ msr = rdmsr(MSR_PP0_CURRENT_CONFIG); msr.lo &= ~0x1fff; - msr.lo |= PP0_CURRENT_LIMIT; + if (conf->pp0_current_limit) { + /* Fill in board specific maximum current supported by VR */ + msr.lo |= conf->pp0_current_limit * 8; + } else { + printk(BIOS_INFO, "%s: PP0 current limit not set in devicetree\n", dev_path(dev)); + /* + * The default value might over-stress the voltage regulator or + * prevent OC on boards with regulators that can handle currents + * above the Intel recommendation. + */ + msr.lo |= PP0_CURRENT_LIMIT; + } + for (int i = 0; i < VR12_PSI_MAX; i++) { + /* + * Light load optimization. Depending on the VR output filter the + * number of phases can be reduced at light load. This is a board + * specific setting. + */ + if (conf->pp0_psi[i].phases != VR12_KEEP_DEFAULT) { + msr.hi &= ~(0x3ff << (i * 10)); + msr.hi |= (conf->pp0_psi[i].phases - 1) << (i * 10 + 7); + msr.hi |= conf->pp0_psi[i].current << (i * 10); + } else { + printk(BIOS_INFO, "%s: PP0 PSI%d not set in devicetree\n", dev_path(dev), i); + } + } msr.lo |= PP0_CURRENT_LIMIT_LOCK; wrmsr(MSR_PP0_CURRENT_CONFIG, msr); - /* Secondary Plane Current Limit */ + /* Secondary Plane Current Limit (IAXG) */ msr = rdmsr(MSR_PP1_CURRENT_CONFIG); msr.lo &= ~0x1fff; - if (IS_IVY_CPU(cpu_get_cpuid())) - msr.lo |= PP1_CURRENT_LIMIT_IVB; - else - msr.lo |= PP1_CURRENT_LIMIT_SNB; + if (conf->pp1_current_limit) { + /* Fill in board specific maximum current supported by VR */ + msr.lo |= conf->pp1_current_limit * 8; + } else { + printk(BIOS_INFO, "%s: PP1 current limit not set in devicetree\n", dev_path(dev)); + /* + * The default value might over-stress the voltage regulator or + * prevent OC on boards with regulators that can handle currents + * above the Intel recommendation. + */ + if (IS_IVY_CPU(cpu_get_cpuid())) + msr.lo |= PP1_CURRENT_LIMIT_IVB; + else + msr.lo |= PP1_CURRENT_LIMIT_SNB; + } + for (int i = 0; i < VR12_PSI_MAX; i++) { + /* + * Light load optimization. Depending on the VR output filter the + * number of phases can be reduced at light load. This is a board + * specific setting. + */ + if (conf->pp1_psi[i].phases != VR12_KEEP_DEFAULT) { + msr.hi &= ~(0x3ff << (i * 10)); + msr.hi |= (conf->pp1_psi[i].phases - 1) << (i * 10 + 7); + msr.hi |= conf->pp1_psi[i].current << (i * 10); + } else { + printk(BIOS_INFO, "%s: PP1 PSI%d not set in devicetree\n", dev_path(dev), i); + } + } msr.lo |= PP1_CURRENT_LIMIT_LOCK; wrmsr(MSR_PP1_CURRENT_CONFIG, msr); } @@ -354,7 +405,7 @@ set_vmx_and_lock(); /* Configure C States */ - configure_c_states(); + configure_c_states(cpu); /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 233f690..aa2dc80 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -35,6 +35,18 @@ { 1, 7, 0x0080 }, { 1, 6, 0x0080 },}" + chip cpu/intel/model_206ax + # Values obtained from vendor BIOS v1.46 + register "pp0_current_limit" = "98" + register "pp1_current_limit" = "32" + register "pp0_psi[VR12_PSI1]" = "{VR12_2_PHASES, 20}" + register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + register "pp1_psi[VR12_PSI1]" = "{VR12_2_PHASES, 20}" + register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + device cpu_cluster 0 on end + end device domain 0 on subsystemid 0x17aa 0x21db inherit -- To view, visit https://review.coreboot.org/c/coreboot/+/81597?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I59edab47fc4fbe0240e1dd7d25647f7549b4def2 Gerrit-Change-Number: 81597 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: mb/cwwk: Add CWWK CW-ADL-4L-V2.0 board
by Paul Menzel (Code Review) 31 Mar '24

31 Mar '24

Attention is currently required from: Brandon Weeks. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81595?usp=email ) Change subject: mb/cwwk: Add CWWK CW-ADL-4L-V2.0 board ...................................................................... Patch Set 2: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81595/comment/baf8a4a0_4d161910 : PS2, Line 8: Maybe summarize the board features? https://review.coreboot.org/c/coreboot/+/81595/comment/c16ab8ec_ac8f4b39 : PS2, Line 9: Working: What payload and OS? https://review.coreboot.org/c/coreboot/+/81595/comment/f368cbbe_c8dafa66 : PS2, Line 12: - DisplayPort / HDMI How did yo get the VBT? https://review.coreboot.org/c/coreboot/+/81595/comment/6dc2a51f_5c12a40b : PS2, Line 18: - Fan (ITE IT8613E) There are some ITE patches up for review. https://review.coreboot.org/c/coreboot/+/81595/comment/3e40aff5_483eb226 : PS2, Line 21: What about ACPI S3 and S0ix? Patchset: PS2: Welcome to coreboot and thank you for this board. If you have any questions, please feel free to ask on the mailing list or the other forums like IRC. -- To view, visit https://review.coreboot.org/c/coreboot/+/81595?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ice9174d95c10afc6a22ddd15fb3be4fa38d329be Gerrit-Change-Number: 81595 Gerrit-PatchSet: 2 Gerrit-Owner: Brandon Weeks <bweeks(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-CC: Matthew Garrett <mjgarrett59(a)googlemail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Brandon Weeks <bweeks(a)google.com> Gerrit-Comment-Date: Sun, 31 Mar 2024 06:43:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: riscv: remove test for OPENSBI_TEXT_START == linker address
by ron minnich (Code Review) 31 Mar '24

31 Mar '24

ron minnich has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81596?usp=email ) Change subject: riscv: remove test for OPENSBI_TEXT_START == linker address ...................................................................... riscv: remove test for OPENSBI_TEXT_START == linker address In older OpenSBI, the opensbi linker address had to equal its location in cbfs. Since OpenSBI can now relocate itself, this restriction can be removed. Change-Id: Ib16ae611ebaa9e532c86bc8a88e2352665e5b2fd Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/include/arch/memlayout.h 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/81596/1 diff --git a/src/arch/riscv/include/arch/memlayout.h b/src/arch/riscv/include/arch/memlayout.h index 0c539d2..b100c41 100644 --- a/src/arch/riscv/include/arch/memlayout.h +++ b/src/arch/riscv/include/arch/memlayout.h @@ -22,8 +22,6 @@ #endif #define OPENSBI(addr, size) \ - _ = ASSERT(addr == CONFIG_OPENSBI_TEXT_START, \ - "opensbi linker address must equal CONFIG_OPENSBI_TEXT_START"); \ REGION(opensbi, addr, size, 4K) /* TODO: Need to add DMA_COHERENT region like on ARM? */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81596?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib16ae611ebaa9e532c86bc8a88e2352665e5b2fd Gerrit-Change-Number: 81596 Gerrit-PatchSet: 1 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: util/crossgcc: Also build LLVM LD
by Felix Singer (Code Review) 31 Mar '24

31 Mar '24

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80732?usp=email ) Change subject: util/crossgcc: Also build LLVM LD ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: > The CI uses coreboot-sdk:2024-03-30_cccada28f7 now, which includes this patch. See https://hub.docker.com/r/coreboot/coreboot-sdk/tags -- To view, visit https://review.coreboot.org/c/coreboot/+/80732?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3242585f8b5c3426fc6568d3dc47300164d56e3a Gerrit-Change-Number: 80732 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 31 Mar 2024 03:21:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: util/crossgcc: Also build LLVM LD
by Felix Singer (Code Review) 31 Mar '24

31 Mar '24

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80732?usp=email ) Change subject: util/crossgcc: Also build LLVM LD ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: The CI uses coreboot-sdk:2024-03-30_cccada28f7 now, which includes this patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/80732?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3242585f8b5c3426fc6568d3dc47300164d56e3a Gerrit-Change-Number: 80732 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 31 Mar 2024 03:21:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/cwwk: Add CWWK CW-ADL-4L-V2.0 board
by Brandon Weeks (Code Review) 31 Mar '24

31 Mar '24

Brandon Weeks has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/81595?usp=email ) Change subject: mb/cwwk: Add CWWK CW-ADL-4L-V2.0 board ...................................................................... mb/cwwk: Add CWWK CW-ADL-4L-V2.0 board Working: - Serial port - USB ports - DisplayPort / HDMI - 4x Intel I226 2.5 GbE NICs - M.2 ports - Micro SD slot Not working / not tested: - Fan (ITE IT8613E) - Audio - Power management / power usage Change-Id: Ice9174d95c10afc6a22ddd15fb3be4fa38d329be Signed-off-by: Brandon Weeks <me(a)brandonweeks.com> --- A src/mainboard/cwwk/Kconfig A src/mainboard/cwwk/Kconfig.name A src/mainboard/cwwk/adl/Kconfig A src/mainboard/cwwk/adl/Kconfig.name A src/mainboard/cwwk/adl/Makefile.inc A src/mainboard/cwwk/adl/board.fmd A src/mainboard/cwwk/adl/board_info.txt A src/mainboard/cwwk/adl/bootblock.c A src/mainboard/cwwk/adl/data.vbt A src/mainboard/cwwk/adl/devicetree.cb A src/mainboard/cwwk/adl/dsdt.asl A src/mainboard/cwwk/adl/gpio.h A src/mainboard/cwwk/adl/mainboard.c A src/mainboard/cwwk/adl/romstage_fsp_params.c 14 files changed, 561 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/81595/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81595?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ice9174d95c10afc6a22ddd15fb3be4fa38d329be Gerrit-Change-Number: 81595 Gerrit-PatchSet: 2 Gerrit-Owner: Brandon Weeks <bweeks(a)google.com> Gerrit-CC: Matthew Garrett <mjgarrett59(a)googlemail.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: mb/cwwk: Add CWWK CW-ADL-4L-V2.0 board
by Brandon Weeks (Code Review) 31 Mar '24

31 Mar '24

Brandon Weeks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81595?usp=email ) Change subject: mb/cwwk: Add CWWK CW-ADL-4L-V2.0 board ...................................................................... mb/cwwk: Add CWWK CW-ADL-4L-V2.0 board Change-Id: Ice9174d95c10afc6a22ddd15fb3be4fa38d329be Signed-off-by: Brandon Weeks <me(a)brandonweeks.com> --- A src/mainboard/cwwk/Kconfig A src/mainboard/cwwk/Kconfig.name A src/mainboard/cwwk/adl/Kconfig A src/mainboard/cwwk/adl/Kconfig.name A src/mainboard/cwwk/adl/Makefile.inc A src/mainboard/cwwk/adl/board.fmd A src/mainboard/cwwk/adl/board_info.txt A src/mainboard/cwwk/adl/bootblock.c A src/mainboard/cwwk/adl/data.vbt A src/mainboard/cwwk/adl/devicetree.cb A src/mainboard/cwwk/adl/dsdt.asl A src/mainboard/cwwk/adl/gpio.h A src/mainboard/cwwk/adl/mainboard.c A src/mainboard/cwwk/adl/romstage_fsp_params.c 14 files changed, 561 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/81595/1 diff --git a/src/mainboard/cwwk/Kconfig b/src/mainboard/cwwk/Kconfig new file mode 100644 index 0000000..ccbe902 --- /dev/null +++ b/src/mainboard/cwwk/Kconfig @@ -0,0 +1,15 @@ +if VENDOR_CWWK + +choice + prompt "Mainboard model" + +source "src/mainboard/cwwk/*/Kconfig.name" + +endchoice + +source "src/mainboard/cwwk/*/Kconfig" + +config MAINBOARD_VENDOR + default "CWWK" + +endif # VENDOR_CWWK diff --git a/src/mainboard/cwwk/Kconfig.name b/src/mainboard/cwwk/Kconfig.name new file mode 100644 index 0000000..5262d06 --- /dev/null +++ b/src/mainboard/cwwk/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_CWWK + bool "CWWK" diff --git a/src/mainboard/cwwk/adl/Kconfig b/src/mainboard/cwwk/adl/Kconfig new file mode 100644 index 0000000..3a5d064 --- /dev/null +++ b/src/mainboard/cwwk/adl/Kconfig @@ -0,0 +1,40 @@ +if BOARD_CWWK_ADL_N + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_UART_8250IO + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select SOC_INTEL_ALDERLAKE_PCH_N + select SUPERIO_ITE_IT8613E + +config MAINBOARD_DIR + default "cwwk/adl" + +config MAINBOARD_PART_NUMBER + default "CW-AL-4L-V1.0" + +config DEVICETREE + default "devicetree.cb" + +config DIMM_MAX + default 2 + +config DIMM_SPD_SIZE + default 512 + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" + +config NO_POST + default y + +config USE_PM_ACPI_TIMER + default n + +config EDK2_BOOT_TIMEOUT + default 5 + +endif diff --git a/src/mainboard/cwwk/adl/Kconfig.name b/src/mainboard/cwwk/adl/Kconfig.name new file mode 100644 index 0000000..6b0ce7c --- /dev/null +++ b/src/mainboard/cwwk/adl/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_CWWK_ADL_N + bool "CW-ADL-4L-V1.0" diff --git a/src/mainboard/cwwk/adl/Makefile.inc b/src/mainboard/cwwk/adl/Makefile.inc new file mode 100644 index 0000000..89eb072db --- /dev/null +++ b/src/mainboard/cwwk/adl/Makefile.inc @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +bootblock-y += bootblock.c + +romstage-y += romstage_fsp_params.c + +ramstage-y += mainboard.c diff --git a/src/mainboard/cwwk/adl/board.fmd b/src/mainboard/cwwk/adl/board.fmd new file mode 100644 index 0000000..b305b9b --- /dev/null +++ b/src/mainboard/cwwk/adl/board.fmd @@ -0,0 +1,13 @@ +FLASH 16M { + SI_ALL 6M { + SI_DESC 4K + SI_ME 4172K + SI_DEVICEEXT2 + } + SI_BIOS 10M { + RW_MRC_CACHE 64K + SMMSTORE(PRESERVE) 256K + FMAP 4K + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/cwwk/adl/board_info.txt b/src/mainboard/cwwk/adl/board_info.txt new file mode 100644 index 0000000..b53863c --- /dev/null +++ b/src/mainboard/cwwk/adl/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: CWWK +Board name: CW-ADL-4L-V1.0 +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/cwwk/adl/bootblock.c b/src/mainboard/cwwk/adl/bootblock.c new file mode 100644 index 0000000..f19b383 --- /dev/null +++ b/src/mainboard/cwwk/adl/bootblock.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootblock_common.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8613e/it8613e.h> + +#define UART_DEV PNP_DEV(0x2e, IT8613E_SP1) + +void bootblock_mainboard_early_init(void) +{ + ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/cwwk/adl/data.vbt b/src/mainboard/cwwk/adl/data.vbt new file mode 100644 index 0000000..2a6c207 --- /dev/null +++ b/src/mainboard/cwwk/adl/data.vbt Binary files differ diff --git a/src/mainboard/cwwk/adl/devicetree.cb b/src/mainboard/cwwk/adl/devicetree.cb new file mode 100644 index 0000000..b933a94 --- /dev/null +++ b/src/mainboard/cwwk/adl/devicetree.cb @@ -0,0 +1,91 @@ +chip soc/intel/alderlake + + register "s0ix_enable" = "1" + + # TODO: disable audio + #register "DspEnable" = "0" + + register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" + register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" + register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" + register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" + register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # microSD card reader + + register "pch_pcie_rp[PCH_RP(1)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, + .pcie_rp_aspm = ASPM_DISABLE, + }" + + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, + .pcie_rp_aspm = ASPM_DISABLE, + }" + + register "pch_pcie_rp[PCH_RP(10)]" = "{ + .clk_src = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, + .pcie_rp_aspm = ASPM_DISABLE, + }" + + register "pch_pcie_rp[PCH_RP(11)]" = "{ + .clk_src = 4, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, + .pcie_rp_aspm = ASPM_DISABLE, + }" + + register "pch_pcie_rp[PCH_RP(12)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + + # Enable EDP in PortA + register "ddi_portA_config" = "1" + + # Enable HDMI in Port B + # register "ddi_ports_config" = "{ + # [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + # }" + + device domain 0 on + device ref igpu on end + device ref dtt on end + device ref crashlog off end + device ref xhci on end + device ref shared_sram on end + device ref heci1 on end + device ref emmc off end + device ref pcie_rp1 on end + device ref pcie_rp7 on end + device ref pcie_rp9 on end + device ref pcie_rp10 on end + device ref pcie_rp11 on end + device ref pcie_rp12 on end # M.2 E key port + device ref pch_espi on + chip superio/ite/it8613e + device pnp 2e.0 off end + device pnp 2e.1 on # COM 1 + io 0x60 = 0x3f8 + irq 0x70 = 0x4 + irq 0xf0 = 0x1 + end + device pnp 2e.4 off end # Environment Controller + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # CIR + end + end + device ref hda on end + device ref smbus on end + end +end + diff --git a/src/mainboard/cwwk/adl/dsdt.asl b/src/mainboard/cwwk/adl/dsdt.asl new file mode 100644 index 0000000..e612ec0 --- /dev/null +++ b/src/mainboard/cwwk/adl/dsdt.asl @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/alderlake/acpi/southbridge.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/cwwk/adl/gpio.h b/src/mainboard/cwwk/adl/gpio.h new file mode 100644 index 0000000..fc3d7ea --- /dev/null +++ b/src/mainboard/cwwk/adl/gpio.h @@ -0,0 +1,297 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include <soc/gpio.h> + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* CORE_VID1 */ + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), /* VRALERT# */ + PAD_NC(GPP_B3, NONE), /* GPIO */ + PAD_NC(GPP_B4, NONE), /* GPIO */ + PAD_NC(GPP_B5, NONE), /* GPIO */ + PAD_NC(GPP_B6, NONE), /* GPIO */ + PAD_NC(GPP_B7, NONE), /* GPIO */ + PAD_NC(GPP_B8, NONE), /* GPIO */ + PAD_NC(GPP_B9, NONE), /* GPIO */ + PAD_NC(GPP_B10, NONE), /* GPIO */ + //PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1), /* PMCALERT# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLTRST# */ + PAD_CFG_GPO(GPP_B14, 0, PLTRST), /* GPIO */ + PAD_NC(GPP_B15, NONE), /* GPIO */ + PAD_NC(GPP_B16, NONE), /* GPIO */ + PAD_NC(GPP_B17, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_B18, 0, PLTRST), /* GPIO */ + PAD_NC(GPP_B19, NONE), /* GPIO */ + PAD_NC(GPP_B20, NONE), /* GPIO */ + PAD_NC(GPP_B21, NONE), /* GPIO */ + PAD_NC(GPP_B22, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1), /* GSPI0_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B25, NONE, DEEP, NF1), /* GSPI1_CLK_LOOPBK */ + + /* ------- GPIO Group GPP_T ------- */ + PAD_NC(GPP_T0, NONE), /* GPIO */ + PAD_NC(GPP_T1, NONE), /* GPIO */ + PAD_CFG_NF(GPP_T2, DN_20K, DEEP, NF2), /* FUSA_DIAGTEST_EN */ + PAD_CFG_NF(GPP_T3, DN_20K, DEEP, NF2), /* FUSA_DIAGTEST_MODE */ + PAD_NC(GPP_T4, NONE), /* GPIO */ + PAD_NC(GPP_T5, NONE), /* GPIO */ + PAD_NC(GPP_T6, NONE), /* GPIO */ + PAD_NC(GPP_T7, NONE), /* GPIO */ + PAD_NC(GPP_T8, NONE), /* GPIO */ + PAD_NC(GPP_T9, NONE), /* GPIO */ + PAD_NC(GPP_T10, NONE), /* GPIO */ + PAD_NC(GPP_T11, NONE), /* GPIO */ + PAD_NC(GPP_T12, NONE), /* GPIO */ + PAD_NC(GPP_T13, NONE), /* GPIO */ + PAD_NC(GPP_T14, NONE), /* GPIO */ + PAD_NC(GPP_T15, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), /* ESPI_IO0 */ + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), /* ESPI_IO1 */ + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), /* ESPI_IO2 */ + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), /* ESPI_IO3 */ + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* ESPI_CS0# */ + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), /* ESPI_ALERT0# */ + PAD_CFG_NF(GPP_A6, UP_20K, DEEP, NF1), /* ESPI_ALERT1# */ + PAD_CFG_GPO(GPP_A7, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_A8, NONE), /* GPIO */ + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* ESPI_CLK */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* ESPI_RESET# */ + PAD_NC(GPP_A11, NONE), /* GPIO */ + PAD_NC(GPP_A12, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), /* GPIO */ + PAD_NC(GPP_A14, NONE), /* GPIO */ + PAD_NC(GPP_A15, NONE), /* GPIO */ + PAD_NC(GPP_A16, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_A17, 1, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* DDSP_HPDB */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* DDSP_HPD1 */ + PAD_NC(GPP_A20, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_A21, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_A22, NONE), /* GPIO */ + PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1), /* ESPI_CS1# */ + PAD_CFG_NF(GPP_ESPI_CLK_LOOPBK, NONE, DEEP, NF1), /* GPP_ESPI_CLK_LOOPBK */ + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), /* GPIO */ + PAD_NC(GPP_S1, NONE), /* GPIO */ + PAD_NC(GPP_S2, NONE), /* GPIO */ + PAD_NC(GPP_S3, NONE), /* GPIO */ + PAD_NC(GPP_S4, NONE), /* GPIO */ + PAD_NC(GPP_S5, NONE), /* GPIO */ + PAD_NC(GPP_S6, NONE), /* GPIO */ + PAD_NC(GPP_S7, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_I ------- */ + PAD_NC(GPP_I0, NONE), /* GPIO */ + PAD_NC(GPP_I1, NONE), /* GPIO */ + PAD_NC(GPP_I2, NONE), /* GPIO */ + PAD_NC(GPP_I3, NONE), /* GPIO */ + PAD_NC(GPP_I4, NONE), /* GPIO */ + PAD_NC(GPP_I5, NONE), /* GPIO */ + PAD_NC(GPP_I6, NONE), /* GPIO */ + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), /* EMMC_CMD */ + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), /* EMMC_DATA0 */ + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), /* EMMC_DATA1 */ + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), /* EMMC_DATA2 */ + PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1), /* EMMC_DATA3 */ + PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1), /* EMMC_DATA4 */ + PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), /* EMMC_DATA5 */ + PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1), /* EMMC_DATA6 */ + PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1), /* EMMC_DATA7 */ + PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1), /* EMMC_RCLK */ + PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1), /* EMMC_CLK */ + PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1), /* EMMC_RESET# */ + PAD_NC(GPP_I19, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H1, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H2, 1, RSMRST), /* GPIO */ + PAD_NC(GPP_H3, NONE), /* GPIO */ + PAD_NC(GPP_H4, NONE), /* GPIO */ + PAD_NC(GPP_H5, NONE), /* GPIO */ + PAD_NC(GPP_H6, NONE), /* GPIO */ + PAD_NC(GPP_H7, NONE), /* GPIO */ + PAD_NC(GPP_H8, NONE), /* GPIO */ + PAD_NC(GPP_H9, NONE), /* GPIO */ + PAD_NC(GPP_H10, NONE), /* GPIO */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* UART0_TXD */ + PAD_NC(GPP_H12, NONE), /* GPIO */ + PAD_NC(GPP_H13, NONE), /* GPIO */ + PAD_NC(GPP_H14, NONE), /* GPIO */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ + PAD_NC(GPP_H16, NONE), /* GPIO */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* PROC_C10_GATE# */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), /* SRCCLKREQ4# */ + PAD_NC(GPP_H20, NONE), /* GPIO */ + PAD_NC(GPP_H21, NONE), /* GPIO */ + PAD_NC(GPP_H22, NONE), /* GPIO */ + PAD_NC(GPP_H23, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D1, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_NC(GPP_D2, NONE), /* GPIO */ + PAD_NC(GPP_D3, NONE), /* GPIO */ + PAD_NC(GPP_D4, NONE), /* GPIO */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* SRCCLKREQ0# */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* SRCCLKREQ1# */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* SRCCLKREQ2# */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* SRCCLKREQ3# */ + PAD_CFG_NF(GPP_D9, NATIVE, DEEP, NF5), /* BSSB_LS2_RX */ + PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF5), /* BSSB_LS2_TX */ + PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF5), /* BSSB_LS3_RX */ + PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF5), /* BSSB_LS3_TX */ + PAD_NC(GPP_D13, NONE), /* GPIO */ + PAD_NC(GPP_D14, NONE), /* GPIO */ + PAD_NC(GPP_D15, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_D16, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_D17, NONE), /* GPIO */ + PAD_NC(GPP_D18, NONE), /* GPIO */ + PAD_NC(GPP_D19, NONE), /* GPIO */ + PAD_CFG_NF(GPP_GSPI2_CLK_LOOPBK, NONE, DEEP, NF1), /* GPP_GSPI2_CLK_LOOPBK */ + + /* ------- GPIO Group vGPIO ------- */ + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPP_GPD ------- */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), /* BATLOW# */ + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* ACPRESENT */ + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* LAN_WAKE# */ + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* PWRBTN# */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* SLP_S3# */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* SLP_S4# */ + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* SLP_A# */ + PAD_CFG_GPO(GPD7, 0, PWROK), /* GPIO */ + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK */ + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* SLP_WLAN# */ + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* SLP_S5# */ + PAD_CFG_GPO(GPD11, 0, PWROK), /* GPIO */ + PAD_CFG_NF(GPD_INPUT3VSEL, NONE, PWROK, NF1), /* GPD_INPUT3VSEL */ + PAD_CFG_NF(GPD_SLP_LANB, NONE, PWROK, NF1), /* GPD_SLP_LANB */ + PAD_CFG_NF(GPD_SLP_SUSB, NONE, PWROK, NF1), /* GPD_SLP_SUSB */ + PAD_CFG_NF(GPD_WAKEB, NONE, PWROK, NF1), /* GPD_WAKEB */ + PAD_CFG_NF(GPD_DRAM_RESETB, NONE, PWROK, NF1), /* GPD_DRAM_RESETB */ + + /* ------- GPIO Group PCIe vGPIO ------- */ + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA */ + PAD_CFG_GPO(GPP_C2, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0CLK */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0DATA */ + PAD_CFG_GPO(GPP_C5, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_C6, NONE, RSMRST, NF1), /* SML1CLK */ + PAD_CFG_NF(GPP_C7, NONE, RSMRST, NF1), /* SML1DATA */ + PAD_NC(GPP_C8, NONE), /* GPIO */ + PAD_NC(GPP_C9, NONE), /* GPIO */ + PAD_NC(GPP_C10, NONE), /* GPIO */ + PAD_NC(GPP_C11, NONE), /* GPIO */ + PAD_NC(GPP_C12, NONE), /* GPIO */ + PAD_NC(GPP_C13, NONE), /* GPIO */ + PAD_NC(GPP_C14, NONE), /* GPIO */ + PAD_NC(GPP_C15, NONE), /* GPIO */ + PAD_NC(GPP_C16, NONE), /* GPIO */ + PAD_NC(GPP_C17, NONE), /* GPIO */ + PAD_NC(GPP_C18, NONE), /* GPIO */ + PAD_NC(GPP_C19, NONE), /* GPIO */ + PAD_NC(GPP_C20, NONE), /* GPIO */ + PAD_NC(GPP_C21, NONE), /* GPIO */ + PAD_NC(GPP_C22, NONE), /* GPIO */ + PAD_NC(GPP_C23, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_BRI_DT */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), /* CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* CNV_RGI_DT */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), /* CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_RF_RESET# */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), /* MODEM_CLKREQ */ + PAD_NC(GPP_F6, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_F7, 0, DEEP), /* GPIO */ + PAD_NC(GPP_F8, NONE), /* GPIO */ + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* BOOTMPC */ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_F11, NONE), /* GPIO */ + PAD_NC(GPP_F12, NONE), /* GPIO */ + PAD_NC(GPP_F13, NONE), /* GPIO */ + PAD_NC(GPP_F14, NONE), /* GPIO */ + PAD_NC(GPP_F15, NONE), /* GPIO */ + PAD_NC(GPP_F16, NONE), /* GPIO */ + PAD_NC(GPP_F17, NONE), /* GPIO */ + PAD_NC(GPP_F18, NONE), /* GPIO */ + PAD_NC(GPP_F19, NONE), /* GPIO */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* Reserved */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* Reserved */ + PAD_NC(GPP_F22, NONE), /* GPIO */ + PAD_NC(GPP_F23, NONE), /* GPIO */ + PAD_NC(GPP_F_CLK_LOOPBK, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_HVCMOS ------- */ + PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_L_BKLTCTL, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_L_VDDEN, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_SYS_PWROK, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_SYS_RESETB, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_MLK_RSTB, NONE, DEEP, NF1), /* n/a */ + + /* ------- GPIO Group GPP_E ------- */ + PAD_NC(GPP_E0, NONE), /* GPIO */ + PAD_NC(GPP_E1, NONE), /* GPIO */ + PAD_NC(GPP_E2, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), /* GPIO */ + PAD_NC(GPP_E4, NONE), /* GPIO */ + PAD_NC(GPP_E5, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_E6, 0, DEEP), /* GPIO */ + PAD_NC(GPP_E7, NONE), /* GPIO */ + PAD_NC(GPP_E8, NONE), /* GPIO */ + PAD_NC(GPP_E9, NONE), /* GPIO */ + PAD_NC(GPP_E10, NONE), /* GPIO */ + PAD_NC(GPP_E11, NONE), /* GPIO */ + PAD_NC(GPP_E12, NONE), /* GPIO */ + PAD_NC(GPP_E13, NONE), /* GPIO */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDSP_HPDA */ + PAD_CFG_GPO(GPP_E15, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_E16, 0, PLTRST), /* GPIO */ + PAD_NC(GPP_E17, NONE), /* GPIO */ + PAD_CFG_NF(GPP_E18, NATIVE, DEEP, NF5), /* BSSB_LS0_RX */ + PAD_CFG_NF(GPP_E19, NATIVE, DEEP, NF5), /* BSSB_LS0_TX */ + PAD_CFG_GPO(GPP_E20, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_E21, 0, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF1), /* DDPA_CTRLCLK */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), /* DDPA_CTRLDATA */ + PAD_NC(GPP_E_CLK_LOOPBK, NONE), /* GPIO */ + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), /* HDA_BCLK */ + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), /* HDA_SYNC */ + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), /* HDA_SDO */ + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), /* HDA_SDI0 */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), /* HDA_RST# */ + PAD_NC(GPP_R5, NONE), /* GPIO */ + PAD_NC(GPP_R6, NONE), /* GPIO */ + PAD_NC(GPP_R7, NONE), /* GPIO */ +}; + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/cwwk/adl/mainboard.c b/src/mainboard/cwwk/adl/mainboard.c new file mode 100644 index 0000000..439661d --- /dev/null +++ b/src/mainboard/cwwk/adl/mainboard.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + params->PchEspiLgmrEnable = 0; +} + +static void mainboard_init(void *chip_info) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/cwwk/adl/romstage_fsp_params.c b/src/mainboard/cwwk/adl/romstage_fsp_params.c new file mode 100644 index 0000000..614c9f5 --- /dev/null +++ b/src/mainboard/cwwk/adl/romstage_fsp_params.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <fsp/api.h> +#include <soc/meminit.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + static const struct mb_cfg ddr5_mem_config = { + .type = MEM_TYPE_DDR5, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, + + .LpDdrDqDqsReTraining = 1, + }; + + const struct mem_spd dimm_module_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { + .addr_dimm[0] = 0x50, + }, + [1] = { + .addr_dimm[0] = 0x52, + }, + }, + }; + + const bool half_populated = false; + memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, half_populated); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/81595?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ice9174d95c10afc6a22ddd15fb3be4fa38d329be Gerrit-Change-Number: 81595 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Weeks <bweeks(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: Update opensbi submodule to upstream master branch
by Maximilian Brune (Code Review) 31 Mar '24

31 Mar '24

Attention is currently required from: Martin L Roth, Philipp Hug, ron minnich. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81543?usp=email ) Change subject: Update opensbi submodule to upstream master branch ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > yes, a range pmp would cover that just fine. […] I am strongly against using OpenSBI's relocation feature. It is a huge pain for debugging. -- To view, visit https://review.coreboot.org/c/coreboot/+/81543?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I50ce0ba3b6409247a94b49565cc04454903e88d0 Gerrit-Change-Number: 81543 Gerrit-PatchSet: 4 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Sun, 31 Mar 2024 00:06:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/erying: Add Erying Polestar G613 Pro (TGL-H)
by Alicja Michalska (Code Review) 30 Mar '24

30 Mar '24

Attention is currently required from: Alicja Michalska, Felix Singer, Michał Żygowski, Nicholas Chin, Paul Menzel. Hello Felix Singer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80853?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/erying: Add Erying Polestar G613 Pro (TGL-H) ...................................................................... mb/erying: Add Erying Polestar G613 Pro (TGL-H) Erying is a Chinese manufacturer selling desktop motherboards with laptop SoCs and custom shim to mount desktop coolers. Working: - Serial port (IT8613E RS232) - All rear USB ports (3.0, 2.0) - Both HDMI ports - Realtek GbE NIC - Internal audio (ALC897/ TGL-H HDMI) - Environment Controller (SuperIO fan control) - All SATA ports - All PCI-E/M.2 ports (somewhat) - PCI-E Resizable BAR (ReBAR) - VT-x (PCI-E passtrough, broken on stock) WIP/Broken: - PCI-E ASPM (even though I force-disabled it, I'm still getting AERs) - M.2 NGFF WiFi (should be working, but I lost my WiFi card while moving) - S3/s0ix (also broken on stock, setting 3VSB register didn't help - system goes to sleep, but RAM loses power) - DisplayPort on I/O panel (simple fix, need to re-configure GPIOs) - One of USB2 FP connectors, as well as NGFF USB isn't mapped (yet) - Automatic fan control (IT8613E can't read CPU_TIN at the moment) Can be flashed using `flashrom -p internal -w build/coreboot.rom`, as vendor haven't enabled any protections on SPI chip. I'd like to get ASPM working as it makes big difference in idle power consumtion (25 vs 60W measured from the wall at 230V). Likewise, I can't wrap my head around PCI-E AERs I'm getting if I boot the machine without `pcie_aspm=off` parameter: - BadTLP - BadDLLP - Timeout - Rollover Adjusting LaneEq's didn't change anything, all settings are configured in (mostly) the same way as they were on stock firmware. Starting to suspect Intel's FSP might be buggy, as I haven't had those issues when I initially started working on this project when 4.20 tree was current. TEST=Flash coreboot build onto the motherboard, install following PCI-E cards: Radeon RX 7800XT, Kingston KC3000, Optane 900P, Audigy X-Fi. Power the system up and boot into Windows 10 to check ACPI sanity, then reboot into Fedora Linux (kernel 6.7.4) and launch 3D application, disk benchmark, compilation at the same time to check system's stability. Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e Signed-off-by: Alicja Michalska <ahplka19(a)gmail.com> --- A src/mainboard/erying/Kconfig A src/mainboard/erying/Kconfig.name A src/mainboard/erying/tgl/Kconfig A src/mainboard/erying/tgl/Kconfig.name A src/mainboard/erying/tgl/Makefile.inc A src/mainboard/erying/tgl/board_info.txt A src/mainboard/erying/tgl/bootblock.c A src/mainboard/erying/tgl/cmos.layout A src/mainboard/erying/tgl/data.vbt A src/mainboard/erying/tgl/devicetree.cb A src/mainboard/erying/tgl/dsdt.asl A src/mainboard/erying/tgl/gpio.h A src/mainboard/erying/tgl/hda_verb.c A src/mainboard/erying/tgl/ramstage.c A src/mainboard/erying/tgl/romstage_fsp_params.c 15 files changed, 861 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/80853/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/80853?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e Gerrit-Change-Number: 80853 Gerrit-PatchSet: 6 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newpatchset

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