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Hello Felix Singer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80853?usp=email
to look at the new patch set (#6).
The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: mb/erying: Add Erying Polestar G613 Pro (TGL-H)
......................................................................
mb/erying: Add Erying Polestar G613 Pro (TGL-H)
Erying is a Chinese manufacturer selling desktop motherboards with
laptop SoCs and custom shim to mount desktop coolers.
Working:
- Serial port (IT8613E RS232)
- All rear USB ports (3.0, 2.0)
- Both HDMI ports
- Realtek GbE NIC
- Internal audio (ALC897/ TGL-H HDMI)
- Environment Controller (SuperIO fan control)
- All SATA ports
- All PCI-E/M.2 ports (somewhat)
- PCI-E Resizable BAR (ReBAR)
- VT-x (PCI-E passtrough, broken on stock)
WIP/Broken:
- PCI-E ASPM (even though I force-disabled it, I'm still getting AERs)
- M.2 NGFF WiFi (should be working, but I lost my WiFi card while
moving)
- S3/s0ix (also broken on stock, setting 3VSB register didn't help -
system goes to sleep, but RAM loses power)
- DisplayPort on I/O panel (simple fix, need to re-configure GPIOs)
- One of USB2 FP connectors, as well as NGFF USB isn't mapped (yet)
- Automatic fan control (IT8613E can't read CPU_TIN at the moment)
Can be flashed using `flashrom -p internal -w build/coreboot.rom`, as
vendor haven't enabled any protections on SPI chip.
I'd like to get ASPM working as it makes big difference in idle power
consumtion (25 vs 60W measured from the wall at 230V).
Likewise, I can't wrap my head around PCI-E AERs I'm getting if I boot
the machine without `pcie_aspm=off` parameter:
- BadTLP
- BadDLLP
- Timeout
- Rollover
Adjusting LaneEq's didn't change anything, all settings are configured
in (mostly) the same way as they were on stock firmware.
Starting to suspect Intel's FSP might be buggy, as I haven't had those
issues when I initially started working on this project when 4.20 tree
was current.
TEST=Flash coreboot build onto the motherboard, install following PCI-E
cards: Radeon RX 7800XT, Kingston KC3000, Optane 900P, Audigy X-Fi.
Power the system up and boot into Windows 10 to check ACPI sanity, then
reboot into Fedora Linux (kernel 6.7.4) and launch 3D application, disk
benchmark, compilation at the same time to check system's stability.
Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e
Signed-off-by: Alicja Michalska <ahplka19(a)gmail.com>
---
A src/mainboard/erying/Kconfig
A src/mainboard/erying/Kconfig.name
A src/mainboard/erying/tgl/Kconfig
A src/mainboard/erying/tgl/Kconfig.name
A src/mainboard/erying/tgl/Makefile.inc
A src/mainboard/erying/tgl/board_info.txt
A src/mainboard/erying/tgl/bootblock.c
A src/mainboard/erying/tgl/cmos.layout
A src/mainboard/erying/tgl/data.vbt
A src/mainboard/erying/tgl/devicetree.cb
A src/mainboard/erying/tgl/dsdt.asl
A src/mainboard/erying/tgl/gpio.h
A src/mainboard/erying/tgl/hda_verb.c
A src/mainboard/erying/tgl/ramstage.c
A src/mainboard/erying/tgl/romstage_fsp_params.c
15 files changed, 861 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/80853/6
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Change subject: mb/erying: Add Erying Polestar G613 Pro (TGL-H)
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/erying/tgl/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/80853/comment/5343ae8a_040c7252 :
PS2, Line 197: end
> It seems so, my bad for not building locally to test it. […]
For future reference: Yes, it is needed after all.
Removing this entry from devicetree breaks mp_init.
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Hello Felix Singer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80853?usp=email
to look at the new patch set (#5).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/erying: Add Erying Polestar G613 Pro (TGL-H)
......................................................................
mb/erying: Add Erying Polestar G613 Pro (TGL-H)
Erying is a Chinese manufacturer selling desktop motherboards with
laptop SoCs and custom shim to mount desktop coolers.
Working:
- Serial port (IT8613E RS232)
- All rear USB ports (3.0, 2.0)
- Both HDMI ports
- Realtek GbE NIC
- Internal audio (ALC897/ TGL-H HDMI)
- Environment Controller (SuperIO fan control)
- All SATA ports
- All PCI-E/M.2 ports (somewhat)
- PCI-E Resizable BAR (ReBAR)
- VT-x (PCI-E passtrough, broken on stock)
WIP/Broken:
- PCI-E ASPM (even though I force-disabled it, I'm still getting AERs)
- M.2 NGFF WiFi (should be working, but I lost my WiFi card while
moving)
- S3/s0ix (also broken on stock, setting 3VSB register didn't help -
system goes to sleep, but RAM loses power)
- DisplayPort on I/O panel (simple fix, need to re-configure GPIOs)
- One of USB2 FP connectors, as well as NGFF USB isn't mapped (yet)
- Automatic fan control (IT8613E can't read CPU_TIN at the moment)
Can be flashed using `flashrom -p internal -w build/coreboot.rom`, as
vendor haven't enabled any protections on SPI chip.
I'd like to get ASPM working as it makes big difference in idle power
consumtion (25 vs 60W measured from the wall at 230V).
Likewise, I can't wrap my head around PCI-E AERs I'm getting if I boot
the machine without `pcie_aspm=off` parameter:
- BadTLP
- BadDLLP
- Timeout
- Rollover
Adjusting LaneEq's didn't change anything, all settings are configured
in (mostly) the same way as they were on stock firmware.
Starting to suspect Intel's FSP might be buggy, as I haven't had those
issues when I initially started working on this project when 4.20 tree
was current.
TEST=Flash coreboot build onto the motherboard, install following PCI-E
cards: Radeon RX 7800XT, Kingston KC3000, Optane 900P, Audigy X-Fi.
Power the system up and boot into Windows 10 to check ACPI sanity, then
reboot into Fedora Linux (kernel 6.7.4) and launch 3D application, disk
benchmark, compilation at the same time to check system's stability.
Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e
Signed-off-by: Alicja Michalska <ahplka19(a)gmail.com>
---
A src/mainboard/erying/Kconfig
A src/mainboard/erying/Kconfig.name
A src/mainboard/erying/tgl/Kconfig
A src/mainboard/erying/tgl/Kconfig.name
A src/mainboard/erying/tgl/Makefile.inc
A src/mainboard/erying/tgl/board_info.txt
A src/mainboard/erying/tgl/bootblock.c
A src/mainboard/erying/tgl/cmos.layout
A src/mainboard/erying/tgl/data.vbt
A src/mainboard/erying/tgl/devicetree.cb
A src/mainboard/erying/tgl/dsdt.asl
A src/mainboard/erying/tgl/gpio.h
A src/mainboard/erying/tgl/hda_verb.c
A src/mainboard/erying/tgl/ramstage.c
A src/mainboard/erying/tgl/romstage_fsp_params.c
15 files changed, 861 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/80853/5
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ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81543?usp=email )
Change subject: Update opensbi submodule to upstream master branch
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> Yes that is the requirement I was talking about. […]
yes, a range pmp would cover that just fine. But coreboot is also wrong about the requirements on opensbi now -- sbi can relocate itself. So I need to first submit another PR for coreboot to remove the check on the definition of OPENSBI
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Change subject: Update opensbi submodule to upstream master branch
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> dying here: […]
Yes that is the requirement I was talking about. As far as I know this check is for the PMP regions that are set up later to cover both segments (text + data). It is a bit too restrictive though (even though it doesn't need to be).
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Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80633?usp=email )
Change subject: vc/intel/fsp/fsp2_0: Add GNR N-1 FSP headers
......................................................................
vc/intel/fsp/fsp2_0: Add GNR N-1 FSP headers
GNR N-1 FSP headers are a set of stub headers used to fulfill
build sanity check for GNR SoC and CRB codes before the formal
FSP headers are published. The N-1 headers are forward compatible
with the later formal headers.
Change-Id: I1c8125dd64e5a9619073c2f17aeade1d33607870
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80633
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com>
---
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/CxlNodeHob.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/EnhancedWarningLogLib.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FirmwareVersionInfoHob.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspAcpiHobs.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspEas.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspErrorInfoHob.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspUpd.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspiUpd.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspmUpd.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspsUpd.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FsptUpd.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioPcieConfigUpd.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioUniversalDataHob.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/MemoryMapDataHob.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/PrevBootErrSrcHob.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/SystemInfoHob.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/CxlNodeHob.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/EnhancedWarningLogLib.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FirmwareVersionInfoHob.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspAcpiHobs.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspEas.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspErrorInfoHob.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspUpd.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspiUpd.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspmUpd.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspsUpd.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FsptUpd.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioPcieConfigUpd.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioUniversalDataHob.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/MemoryMapDataHob.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/PrevBootErrSrcHob.h
A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/SystemInfoHob.h
32 files changed, 7,286 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Lean Sheng Tan: Looks good to me, approved
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Change subject: device/device_util: Rename dev_get_pci_domain
......................................................................
Patch Set 6: Code-Review+2
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Change subject: drivers/pc80/tpm: Support Xeon-SP
......................................................................
Patch Set 5:
(1 comment)
File src/drivers/pc80/tpm/tis.c:
https://review.coreboot.org/c/coreboot/+/81276/comment/51674326_06943ae4 :
PS5, Line 806: assert(domain);
: if (domain)
Why both?
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Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Martin L Roth, Patrick Rudolph, Paul Menzel, Shuo Liu, TangYiwei, Tim Chu.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81312?usp=email )
Change subject: soc/intel/xeon_sp: Unshare Xeon-SP chip common codes
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Patch Set 26: Code-Review+1
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