coreboot-gerrit March 2024

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[S] Change in coreboot[main]: Update opensbi submodule to upstream master branch
by Maximilian Brune (Code Review) 30 Mar '24

30 Mar '24

Attention is currently required from: Martin L Roth, Philipp Hug, ron minnich. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81543?usp=email ) Change subject: Update opensbi submodule to upstream master branch ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > dying here: […] Yes that is the requirement I was talking about. As far as I know this check is for the PMP regions that are set up later to cover both segments (text + data). It is a bit too restrictive though (even though it doesn't need to be). -- To view, visit https://review.coreboot.org/c/coreboot/+/81543?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I50ce0ba3b6409247a94b49565cc04454903e88d0 Gerrit-Change-Number: 81543 Gerrit-PatchSet: 4 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Sat, 30 Mar 2024 16:58:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: vc/intel/fsp/fsp2_0: Add GNR N-1 FSP headers
by Lean Sheng Tan (Code Review) 30 Mar '24

30 Mar '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80633?usp=email ) Change subject: vc/intel/fsp/fsp2_0: Add GNR N-1 FSP headers ...................................................................... vc/intel/fsp/fsp2_0: Add GNR N-1 FSP headers GNR N-1 FSP headers are a set of stub headers used to fulfill build sanity check for GNR SoC and CRB codes before the formal FSP headers are published. The N-1 headers are forward compatible with the later formal headers. Change-Id: I1c8125dd64e5a9619073c2f17aeade1d33607870 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80633 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/CxlNodeHob.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/EnhancedWarningLogLib.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FirmwareVersionInfoHob.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspAcpiHobs.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspEas.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspErrorInfoHob.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspUpd.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspiUpd.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspmUpd.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspsUpd.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FsptUpd.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioPcieConfigUpd.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioUniversalDataHob.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/MemoryMapDataHob.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/PrevBootErrSrcHob.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/SystemInfoHob.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/CxlNodeHob.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/EnhancedWarningLogLib.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FirmwareVersionInfoHob.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspAcpiHobs.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspEas.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspErrorInfoHob.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspUpd.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspiUpd.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspmUpd.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspsUpd.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FsptUpd.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioPcieConfigUpd.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioUniversalDataHob.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/MemoryMapDataHob.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/PrevBootErrSrcHob.h A src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/SystemInfoHob.h 32 files changed, 7,286 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved -- To view, visit https://review.coreboot.org/c/coreboot/+/80633?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c8125dd64e5a9619073c2f17aeade1d33607870 Gerrit-Change-Number: 80633 Gerrit-PatchSet: 27 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Unshare Xeon-SP chip common codes
by Lean Sheng Tan (Code Review) 30 Mar '24

30 Mar '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81312?usp=email ) Change subject: soc/intel/xeon_sp: Unshare Xeon-SP chip common codes ...................................................................... soc/intel/xeon_sp: Unshare Xeon-SP chip common codes GraniteRapids (6th Gen Xeon-SP) FSP contains changes in IIO stack descriptors impacting the way of coreboot's creation of domains. Separates the codes as preparation for 6th Gen and later platforms. Change-Id: Iab6acaa5e5c090c8d821bd7c2d3e0e0ad7486bdc Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81312 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/soc/intel/xeon_sp/chip_common.c A src/soc/intel/xeon_sp/chip_gen1.c M src/soc/intel/xeon_sp/cpx/Makefile.mk M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/skx/Makefile.mk M src/soc/intel/xeon_sp/spr/Makefile.mk M src/soc/intel/xeon_sp/spr/ioat.c 7 files changed, 221 insertions(+), 194 deletions(-) Approvals: Nico Huber: Looks good to me, but someone else must approve build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index 3ca0eca..66f7169 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -12,19 +12,6 @@ #include <soc/util.h> #include <stdlib.h> -static const STACK_RES *domain_to_stack_res(const struct device *dev) -{ - assert(dev->path.type == DEVICE_PATH_DOMAIN); - const union xeon_domain_path dn = { - .domain_path = dev->path.domain.domain - }; - - const IIO_UDS *hob = get_iio_uds(); - assert(hob != NULL); - - return &hob->PlatformData.IIO_resource[dn.socket].StackRes[dn.stack]; -} - /** * Find all device of a given vendor and type for the specified socket. * The function iterates over all PCI domains of the specified socket @@ -189,81 +176,7 @@ return dn.stack; } -void iio_pci_domain_read_resources(struct device *dev) -{ - struct resource *res; - const STACK_RES *sr = domain_to_stack_res(dev); - - if (!sr) - return; - - int index = 0; - - if (is_domain0(dev)) { - /* The 0 - 0xfff IO range is not reported by the HOB but still gets decoded */ - res = new_resource(dev, index++); - res->base = 0; - res->size = 0x1000; - res->limit = 0xfff; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - } - - if (sr->PciResourceIoBase < sr->PciResourceIoLimit) { - res = new_resource(dev, index++); - res->base = sr->PciResourceIoBase; - res->limit = sr->PciResourceIoLimit; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED; - } - - if (sr->PciResourceMem32Base < sr->PciResourceMem32Limit) { - res = new_resource(dev, index++); - res->base = sr->PciResourceMem32Base; - res->limit = sr->PciResourceMem32Limit; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } - - if (sr->PciResourceMem64Base < sr->PciResourceMem64Limit) { - res = new_resource(dev, index++); - res->base = sr->PciResourceMem64Base; - res->limit = sr->PciResourceMem64Limit; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } -} - -/* - * Used by IIO stacks for PCIe bridges. Those contain 1 PCI host bridges, - * all the bus numbers on the IIO stack can be used for this bridge - */ -static struct device_operations iio_pcie_domain_ops = { - .read_resources = iio_pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .scan_bus = pci_host_bridge_scan_bus, -#if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = soc_acpi_name, - .write_acpi_tables = northbridge_write_acpi_tables, - .acpi_fill_ssdt = pci_domain_fill_ssdt, -#endif -}; - -/* - * Used by UBOX stacks. Those contain multiple PCI host bridges, each having - * only one bus with UBOX devices. UBOX devices have no resources. - */ -static struct device_operations ubox_pcie_domain_ops = { - .read_resources = noop_read_resources, - .set_resources = noop_set_resources, - .scan_bus = pci_host_bridge_scan_bus, -#if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = soc_acpi_name, - .write_acpi_tables = northbridge_write_acpi_tables, - .acpi_fill_ssdt = pci_domain_fill_ssdt, -#endif -}; - -static void soc_create_domains(const union xeon_domain_path dp, struct bus *upstream, +void create_domain(const union xeon_domain_path dp, struct bus *upstream, int bus_base, int bus_limit, const char *type, struct device_operations *ops, const size_t pci_segment_group) @@ -285,92 +198,6 @@ bus->segment_group = pci_segment_group; } - -static void soc_create_pcie_domains(const union xeon_domain_path dp, struct bus *upstream, - const STACK_RES *sr, const size_t pci_segment_group) -{ - soc_create_domains(dp, upstream, sr->BusBase, sr->BusLimit, DOMAIN_TYPE_PCIE, - &iio_pcie_domain_ops, pci_segment_group); -} - -/* - * On the first Xeon-SP generations there are no separate UBOX stacks, - * and the UBOX devices reside on the first and second IIO. Starting - * with 3rd gen Xeon-SP the UBOX devices are located on their own IIO. - */ -static void soc_create_ubox_domains(const union xeon_domain_path dp, struct bus *upstream, - const STACK_RES *sr, const size_t pci_segment_group) -{ - /* Only expect 2 UBOX buses here */ - assert(sr->BusBase + 1 == sr->BusLimit); - - soc_create_domains(dp, upstream, sr->BusBase, sr->BusBase, DOMAIN_TYPE_UBX0, - &ubox_pcie_domain_ops, pci_segment_group); - soc_create_domains(dp, upstream, sr->BusLimit, sr->BusLimit, DOMAIN_TYPE_UBX1, - &ubox_pcie_domain_ops, pci_segment_group); -} - -#if CONFIG(SOC_INTEL_HAS_CXL) -void iio_cxl_domain_read_resources(struct device *dev) -{ - struct resource *res; - const STACK_RES *sr = domain_to_stack_res(dev); - - if (!sr) - return; - - int index = 0; - - if (sr->IoBase < sr->PciResourceIoBase) { - res = new_resource(dev, index++); - res->base = sr->IoBase; - res->limit = sr->PciResourceIoBase - 1; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED; - } - - if (sr->Mmio32Base < sr->PciResourceMem32Base) { - res = new_resource(dev, index++); - res->base = sr->Mmio32Base; - res->limit = sr->PciResourceMem32Base - 1; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } - - if (sr->Mmio64Base < sr->PciResourceMem64Base) { - res = new_resource(dev, index++); - res->base = sr->Mmio64Base; - res->limit = sr->PciResourceMem64Base - 1; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } -} - -static struct device_operations iio_cxl_domain_ops = { - .read_resources = iio_cxl_domain_read_resources, - .set_resources = pci_domain_set_resources, - .scan_bus = pci_host_bridge_scan_bus, -#if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = soc_acpi_name, - .write_acpi_tables = northbridge_write_acpi_tables, - .acpi_fill_ssdt = pci_domain_fill_ssdt, -#endif -}; - -void soc_create_cxl_domains(const union xeon_domain_path dp, struct bus *bus, - const STACK_RES *sr, const size_t pci_segment_group) -{ - assert(sr->BusBase + 1 <= sr->BusLimit); - - /* 1st domain contains PCIe RCiEPs */ - soc_create_domains(dp, bus, sr->BusBase, sr->BusBase, DOMAIN_TYPE_PCIE, - &iio_pcie_domain_ops, pci_segment_group); - /* 2nd domain contains CXL 1.1 end-points */ - soc_create_domains(dp, bus, sr->BusBase + 1, sr->BusLimit, DOMAIN_TYPE_CXL, - &iio_cxl_domain_ops, pci_segment_group); -} -#endif //CONFIG(SOC_INTEL_HAS_CXL) - /* Attach stack as domains */ void attach_iio_stacks(void) { @@ -394,14 +221,7 @@ dn.socket = s; dn.stack = x; - if (is_ubox_stack_res(ri)) - soc_create_ubox_domains(dn, root_bus, ri, seg); - else if (CONFIG(SOC_INTEL_HAS_CXL) && is_iio_cxl_stack_res(ri)) - soc_create_cxl_domains(dn, root_bus, ri, seg); - else if (is_pcie_iio_stack_res(ri)) - soc_create_pcie_domains(dn, root_bus, ri, seg); - else if (CONFIG(HAVE_IOAT_DOMAINS) && is_ioat_iio_stack_res(ri)) - soc_create_ioat_domains(dn, root_bus, ri, seg); + create_xeonsp_domains(dn, root_bus, ri, seg); } } } diff --git a/src/soc/intel/xeon_sp/chip_gen1.c b/src/soc/intel/xeon_sp/chip_gen1.c new file mode 100644 index 0000000..80ffdda --- /dev/null +++ b/src/soc/intel/xeon_sp/chip_gen1.c @@ -0,0 +1,201 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpigen_pci.h> +#include <assert.h> +#include <console/console.h> +#include <device/pci.h> +#include <intelblocks/acpi.h> +#include <post.h> +#include <soc/acpi.h> +#include <soc/chip_common.h> +#include <soc/soc_util.h> +#include <soc/util.h> +#include <stdlib.h> + +static const STACK_RES *domain_to_stack_res(const struct device *dev) +{ + assert(dev->path.type == DEVICE_PATH_DOMAIN); + const union xeon_domain_path dn = { + .domain_path = dev->path.domain.domain + }; + + const IIO_UDS *hob = get_iio_uds(); + assert(hob != NULL); + + return &hob->PlatformData.IIO_resource[dn.socket].StackRes[dn.stack]; +} + +static void iio_pci_domain_read_resources(struct device *dev) +{ + struct resource *res; + const STACK_RES *sr = domain_to_stack_res(dev); + + if (!sr) + return; + + int index = 0; + + if (is_domain0(dev)) { + /* The 0 - 0xfff IO range is not reported by the HOB but still gets decoded */ + res = new_resource(dev, index++); + res->base = 0; + res->size = 0x1000; + res->limit = 0xfff; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + } + + if (sr->PciResourceIoBase < sr->PciResourceIoLimit) { + res = new_resource(dev, index++); + res->base = sr->PciResourceIoBase; + res->limit = sr->PciResourceIoLimit; + res->size = res->limit - res->base + 1; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED; + } + + if (sr->PciResourceMem32Base < sr->PciResourceMem32Limit) { + res = new_resource(dev, index++); + res->base = sr->PciResourceMem32Base; + res->limit = sr->PciResourceMem32Limit; + res->size = res->limit - res->base + 1; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; + } + + if (sr->PciResourceMem64Base < sr->PciResourceMem64Limit) { + res = new_resource(dev, index++); + res->base = sr->PciResourceMem64Base; + res->limit = sr->PciResourceMem64Limit; + res->size = res->limit - res->base + 1; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; + } +} + +/* + * Used by IIO stacks for PCIe bridges. Those contain 1 PCI host bridges, + * all the bus numbers on the IIO stack can be used for this bridge + */ +static struct device_operations iio_pcie_domain_ops = { + .read_resources = iio_pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .scan_bus = pci_host_bridge_scan_bus, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = soc_acpi_name, + .write_acpi_tables = northbridge_write_acpi_tables, + .acpi_fill_ssdt = pci_domain_fill_ssdt, +#endif +}; + +/* + * Used by UBOX stacks. Those contain multiple PCI host bridges, each having + * only one bus with UBOX devices. UBOX devices have no resources. + */ +static struct device_operations ubox_pcie_domain_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .scan_bus = pci_host_bridge_scan_bus, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = soc_acpi_name, + .write_acpi_tables = northbridge_write_acpi_tables, + .acpi_fill_ssdt = pci_domain_fill_ssdt, +#endif +}; + +static void create_pcie_domains(const union xeon_domain_path dp, struct bus *upstream, + const STACK_RES *sr, const size_t pci_segment_group) +{ + create_domain(dp, upstream, sr->BusBase, sr->BusLimit, DOMAIN_TYPE_PCIE, + &iio_pcie_domain_ops, pci_segment_group); +} + +/* + * On the first Xeon-SP generations there are no separate UBOX stacks, + * and the UBOX devices reside on the first and second IIO. Starting + * with 3rd gen Xeon-SP the UBOX devices are located on their own IIO. + */ +static void create_ubox_domains(const union xeon_domain_path dp, struct bus *upstream, + const STACK_RES *sr, const size_t pci_segment_group) +{ + /* Only expect 2 UBOX buses here */ + assert(sr->BusBase + 1 == sr->BusLimit); + + create_domain(dp, upstream, sr->BusBase, sr->BusBase, DOMAIN_TYPE_UBX0, + &ubox_pcie_domain_ops, pci_segment_group); + create_domain(dp, upstream, sr->BusLimit, sr->BusLimit, DOMAIN_TYPE_UBX1, + &ubox_pcie_domain_ops, pci_segment_group); +} + +void create_cxl_domains(const union xeon_domain_path dp, struct bus *bus, + const STACK_RES *sr, const size_t pci_segment_group); + +#if CONFIG(SOC_INTEL_HAS_CXL) +static void iio_cxl_domain_read_resources(struct device *dev) +{ + struct resource *res; + const STACK_RES *sr = domain_to_stack_res(dev); + + if (!sr) + return; + + int index = 0; + + if (sr->IoBase < sr->PciResourceIoBase) { + res = new_resource(dev, index++); + res->base = sr->IoBase; + res->limit = sr->PciResourceIoBase - 1; + res->size = res->limit - res->base + 1; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED; + } + + if (sr->Mmio32Base < sr->PciResourceMem32Base) { + res = new_resource(dev, index++); + res->base = sr->Mmio32Base; + res->limit = sr->PciResourceMem32Base - 1; + res->size = res->limit - res->base + 1; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; + } + + if (sr->Mmio64Base < sr->PciResourceMem64Base) { + res = new_resource(dev, index++); + res->base = sr->Mmio64Base; + res->limit = sr->PciResourceMem64Base - 1; + res->size = res->limit - res->base + 1; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; + } +} + +static struct device_operations iio_cxl_domain_ops = { + .read_resources = iio_cxl_domain_read_resources, + .set_resources = pci_domain_set_resources, + .scan_bus = pci_host_bridge_scan_bus, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = soc_acpi_name, + .write_acpi_tables = northbridge_write_acpi_tables, + .acpi_fill_ssdt = pci_domain_fill_ssdt, +#endif +}; + +void create_cxl_domains(const union xeon_domain_path dp, struct bus *bus, + const STACK_RES *sr, const size_t pci_segment_group) +{ + assert(sr->BusBase + 1 <= sr->BusLimit); + + /* 1st domain contains PCIe RCiEPs */ + create_domain(dp, bus, sr->BusBase, sr->BusBase, DOMAIN_TYPE_PCIE, + &iio_pcie_domain_ops, pci_segment_group); + /* 2nd domain contains CXL 1.1 end-points */ + create_domain(dp, bus, sr->BusBase + 1, sr->BusLimit, DOMAIN_TYPE_CXL, + &iio_cxl_domain_ops, pci_segment_group); +} +#endif //CONFIG(SOC_INTEL_HAS_CXL) + +void create_xeonsp_domains(const union xeon_domain_path dp, struct bus *bus, + const STACK_RES *sr, const size_t pci_segment_group) +{ + if (is_ubox_stack_res(sr)) + create_ubox_domains(dp, bus, sr, pci_segment_group); + else if (CONFIG(SOC_INTEL_HAS_CXL) && is_iio_cxl_stack_res(sr)) + create_cxl_domains(dp, bus, sr, pci_segment_group); + else if (is_pcie_iio_stack_res(sr)) + create_pcie_domains(dp, bus, sr, pci_segment_group); + else if (CONFIG(HAVE_IOAT_DOMAINS) && is_ioat_iio_stack_res(sr)) + create_ioat_domains(dp, bus, sr, pci_segment_group); +} diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.mk b/src/soc/intel/xeon_sp/cpx/Makefile.mk index 095ad59..3eccfb0 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.mk +++ b/src/soc/intel/xeon_sp/cpx/Makefile.mk @@ -10,6 +10,7 @@ romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-y += chip.c cpu.c soc_util.c soc_acpi.c +ramstage-y += ../chip_gen1.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index 68dc4f9..ce8e759 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -49,16 +49,19 @@ #define DOMAIN_TYPE_UBX1 "UD" #define DOMAIN_TYPE_CXL "CX" -void iio_pci_domain_read_resources(struct device *dev); -void iio_cxl_domain_read_resources(struct device *dev); void attach_iio_stacks(void); -void soc_create_cxl_domains(const union xeon_domain_path dp, struct bus *bus, - const STACK_RES *sr, const size_t pci_segment_group); -void soc_create_ioat_domains(union xeon_domain_path path, - struct bus *bus, - const STACK_RES *sr, - const size_t pci_segment_group); +void create_ioat_domains(union xeon_domain_path path, + struct bus *bus, + const STACK_RES *sr, + const size_t pci_segment_group); + +void create_xeonsp_domains(const union xeon_domain_path dp, struct bus *bus, + const STACK_RES *sr, const size_t pci_segment_group); + +void create_domain(const union xeon_domain_path dp, struct bus *upstream, + int bus_base, int bus_limit, const char *type, + struct device_operations *ops, const size_t pci_segment_group); struct device *dev_find_device_on_socket(uint8_t socket, u16 vendor, u16 device); struct device *dev_find_all_devices_on_socket(uint8_t socket, diff --git a/src/soc/intel/xeon_sp/skx/Makefile.mk b/src/soc/intel/xeon_sp/skx/Makefile.mk index f7599a3..58d783a 100644 --- a/src/soc/intel/xeon_sp/skx/Makefile.mk +++ b/src/soc/intel/xeon_sp/skx/Makefile.mk @@ -16,6 +16,7 @@ ramstage-y += soc_acpi.c ramstage-y += chip.c +ramstage-y += ../chip_gen1.c ramstage-y += soc_util.c ramstage-y += cpu.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c diff --git a/src/soc/intel/xeon_sp/spr/Makefile.mk b/src/soc/intel/xeon_sp/spr/Makefile.mk index d999f30..d288df6 100644 --- a/src/soc/intel/xeon_sp/spr/Makefile.mk +++ b/src/soc/intel/xeon_sp/spr/Makefile.mk @@ -14,6 +14,7 @@ ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c reset.c ramstage-y += crashlog.c ioat.c +ramstage-y += ../chip_gen1.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/spr/include -I$(src)/soc/intel/xeon_sp/spr diff --git a/src/soc/intel/xeon_sp/spr/ioat.c b/src/soc/intel/xeon_sp/spr/ioat.c index cdf9834..ecfc1f7 100644 --- a/src/soc/intel/xeon_sp/spr/ioat.c +++ b/src/soc/intel/xeon_sp/spr/ioat.c @@ -79,10 +79,10 @@ } } -void soc_create_ioat_domains(const union xeon_domain_path path, - struct bus *const bus, - const STACK_RES *const sr, - const size_t pci_segment_group) +void create_ioat_domains(const union xeon_domain_path path, + struct bus *const bus, + const STACK_RES *const sr, + const size_t pci_segment_group) { if (sr->BusLimit < sr->BusBase + HQM_BUS_OFFSET + HQM_RESERVED_BUS) { printk(BIOS_WARNING, -- To view, visit https://review.coreboot.org/c/coreboot/+/81312?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab6acaa5e5c090c8d821bd7c2d3e0e0ad7486bdc Gerrit-Change-Number: 81312 Gerrit-PatchSet: 27 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: device/device_util: Rename dev_get_pci_domain
by Nico Huber (Code Review) 30 Mar '24

30 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81554?usp=email ) Change subject: device/device_util: Rename dev_get_pci_domain ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81554?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I51b18b30fb41038869ea1384b01091da31a895b9 Gerrit-Change-Number: 81554 Gerrit-PatchSet: 6 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sat, 30 Mar 2024 13:24:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/pc80/tpm: Support Xeon-SP
by Nico Huber (Code Review) 30 Mar '24

30 Mar '24

Attention is currently required from: Christian Walter, Patrick Rudolph, Shuo Liu. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81276?usp=email ) Change subject: drivers/pc80/tpm: Support Xeon-SP ...................................................................... Patch Set 5: (1 comment) File src/drivers/pc80/tpm/tis.c: https://review.coreboot.org/c/coreboot/+/81276/comment/51674326_06943ae4 : PS5, Line 806: assert(domain); : if (domain) Why both? -- To view, visit https://review.coreboot.org/c/coreboot/+/81276?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6130b937ec81bbde78d2619eb859ecf354fc3854 Gerrit-Change-Number: 81276 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Comment-Date: Sat, 30 Mar 2024 13:23:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Unshare Xeon-SP chip common codes
by Nico Huber (Code Review) 30 Mar '24

30 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Martin L Roth, Patrick Rudolph, Paul Menzel, Shuo Liu, TangYiwei, Tim Chu. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81312?usp=email ) Change subject: soc/intel/xeon_sp: Unshare Xeon-SP chip common codes ...................................................................... Patch Set 26: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81312?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab6acaa5e5c090c8d821bd7c2d3e0e0ad7486bdc Gerrit-Change-Number: 81312 Gerrit-PatchSet: 26 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sat, 30 Mar 2024 13:17:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: superio/ite: Add function to disable PME# output
by Nico Huber (Code Review) 30 Mar '24

30 Mar '24

Attention is currently required from: Joel Linn. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81589?usp=email ) Change subject: superio/ite: Add function to disable PME# output ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81589?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I94f023ba6eb24b5fb1c5e0b30eb65738f50a87eb Gerrit-Change-Number: 81589 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Comment-Date: Sat, 30 Mar 2024 13:16:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: superio/ite: Add function to disable 3VSBSW# signal
by Nico Huber (Code Review) 30 Mar '24

30 Mar '24

Attention is currently required from: Joel Linn. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81588?usp=email ) Change subject: superio/ite: Add function to disable 3VSBSW# signal ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/superio/ite/common/ite.h: https://review.coreboot.org/c/coreboot/+/81588/comment/41df9210_a652630d : PS1, Line 23: backwards compatibility I'd rather say "for convenience" if we keep using them. -- To view, visit https://review.coreboot.org/c/coreboot/+/81588?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8535176908ec39e9916774135e028cbc7c203474 Gerrit-Change-Number: 81588 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Comment-Date: Sat, 30 Mar 2024 13:15:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/samsung/stumpy: Set initial fan PWM to 30%
by Nico Huber (Code Review) 30 Mar '24

30 Mar '24

Attention is currently required from: Matt DeVillier. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81514?usp=email ) Change subject: mb/samsung/stumpy: Set initial fan PWM to 30% ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81514?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I287e46202ee1c112d1da63c0d8b7889958e3807e Gerrit-Change-Number: 81514 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Sat, 30 Mar 2024 13:12:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/beltino: Set initial fan PWM to 30%
by Nico Huber (Code Review) 30 Mar '24

30 Mar '24

Attention is currently required from: Matt DeVillier, Varshit Pandya. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81513?usp=email ) Change subject: mb/google/beltino: Set initial fan PWM to 30% ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81513?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0177235d73e051f02b5333cf1d735556382b919f Gerrit-Change-Number: 81513 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Sat, 30 Mar 2024 13:12:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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