Samuel Holland has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44696 )
Change subject: mb/intel/dq45ek: Add new mainboard ......................................................................
mb/intel/dq45ek: Add new mainboard
The Intel DQ45EK is a mini-ITX motherboard featuring the Q45 chipset.
The flash chip is soldered in the center of the bottom of the board, and cannot be flashed in-system, so flashing the board requires overriding the IFD permissions (grounding GPIO33 when powering the board on) or desoldering the chip.
At that point, the ME firmware region can be completely removed (this will break fan control).
Tested, working: * SeaBIOS, Tianocore * libgfxinit (both DVI ports, plus VGA on DVI-I) * PCIe x1 slot * COM1 * Audio, Ethernet, SATA (AHCI/IDE), USB (1.1/2.0) * S3 suspend/resume * power_on_after_fail option
Change-Id: I565690c4ed7b4ae60760b8fa6b1e2d783f8e094b Signed-off-by: Samuel Holland samuel@sholland.org --- A src/mainboard/intel/dq45ek/Kconfig A src/mainboard/intel/dq45ek/Kconfig.name A src/mainboard/intel/dq45ek/Makefile.inc A src/mainboard/intel/dq45ek/acpi/ec.asl A src/mainboard/intel/dq45ek/acpi/ich10_pci_irqs.asl A src/mainboard/intel/dq45ek/acpi/superio.asl A src/mainboard/intel/dq45ek/acpi_tables.c A src/mainboard/intel/dq45ek/board_info.txt A src/mainboard/intel/dq45ek/cmos.default A src/mainboard/intel/dq45ek/cmos.layout A src/mainboard/intel/dq45ek/cstates.c A src/mainboard/intel/dq45ek/data.vbt A src/mainboard/intel/dq45ek/devicetree.cb A src/mainboard/intel/dq45ek/dsdt.asl A src/mainboard/intel/dq45ek/early_init.c A src/mainboard/intel/dq45ek/gma-mainboard.ads A src/mainboard/intel/dq45ek/gpio.c A src/mainboard/intel/dq45ek/hda_verb.c 18 files changed, 487 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/44696/1
diff --git a/src/mainboard/intel/dq45ek/Kconfig b/src/mainboard/intel/dq45ek/Kconfig new file mode 100644 index 0000000..593c878 --- /dev/null +++ b/src/mainboard/intel/dq45ek/Kconfig @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_INTEL_DQ45EK + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_X4X + select SOUTHBRIDGE_INTEL_I82801JX + select SUPERIO_WINBOND_WPCD376I + select BOARD_ROMSIZE_KB_4096 + select DRIVERS_I2C_CK505 + select GFX_GMA_ANALOG_I2C_HDMI_C + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + +config VGA_BIOS_ID + string + default "8086,2e02" + +config MAINBOARD_DIR + string + default "intel/dq45ek" + +config MAINBOARD_PART_NUMBER + string + default "DQ45EK" + +endif # BOARD_INTEL_DQ45EK diff --git a/src/mainboard/intel/dq45ek/Kconfig.name b/src/mainboard/intel/dq45ek/Kconfig.name new file mode 100644 index 0000000..aa065e8 --- /dev/null +++ b/src/mainboard/intel/dq45ek/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_DQ45EK + bool "DQ45EK" diff --git a/src/mainboard/intel/dq45ek/Makefile.inc b/src/mainboard/intel/dq45ek/Makefile.inc new file mode 100644 index 0000000..ede8d87 --- /dev/null +++ b/src/mainboard/intel/dq45ek/Makefile.inc @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += cstates.c +romstage-y += gpio.c + +bootblock-y += early_init.c +romstage-y += early_init.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/intel/dq45ek/acpi/ec.asl b/src/mainboard/intel/dq45ek/acpi/ec.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/intel/dq45ek/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/intel/dq45ek/acpi/ich10_pci_irqs.asl b/src/mainboard/intel/dq45ek/acpi/ich10_pci_irqs.asl new file mode 100644 index 0000000..836523f --- /dev/null +++ b/src/mainboard/intel/dq45ek/acpi/ich10_pci_irqs.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* This is board specific information: + * IRQ routing for the 0:1e.0 PCI bridge of the ICH10 + */ + +If (PICM) { + Return (Package() { + }) +} Else { + Return (Package() { + }) +} diff --git a/src/mainboard/intel/dq45ek/acpi/superio.asl b/src/mainboard/intel/dq45ek/acpi/superio.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/intel/dq45ek/acpi/superio.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/intel/dq45ek/acpi_tables.c b/src/mainboard/intel/dq45ek/acpi_tables.c new file mode 100644 index 0000000..f745951 --- /dev/null +++ b/src/mainboard/intel/dq45ek/acpi_tables.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <southbridge/intel/i82801jx/nvs.h> + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + gnvs->pwrs = 1; /* Power state (AC = 1) */ + gnvs->apic = 1; /* Enable APIC */ + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->cmap = 1; /* Enable COM1 port */ +} diff --git a/src/mainboard/intel/dq45ek/board_info.txt b/src/mainboard/intel/dq45ek/board_info.txt new file mode 100644 index 0000000..eb1f4bf --- /dev/null +++ b/src/mainboard/intel/dq45ek/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://ark.intel.com/products/34688 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2008 diff --git a/src/mainboard/intel/dq45ek/cmos.default b/src/mainboard/intel/dq45ek/cmos.default new file mode 100644 index 0000000..706f5dd --- /dev/null +++ b/src/mainboard/intel/dq45ek/cmos.default @@ -0,0 +1,6 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable +sata_mode=AHCI +gfx_uma_size=64M diff --git a/src/mainboard/intel/dq45ek/cmos.layout b/src/mainboard/intel/dq45ek/cmos.layout new file mode 100644 index 0000000..2174ecd --- /dev/null +++ b/src/mainboard/intel/dq45ek/cmos.layout @@ -0,0 +1,96 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 5 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: southbridge +408 1 e 10 sata_mode +409 2 e 7 power_on_after_fail +411 1 e 1 nmi + +# coreboot config options: cpu +#424 8 r 0 unused + +# coreboot config options: northbridge +432 4 e 11 gfx_uma_size +#435 549 r 0 unused + + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +10 0 AHCI +10 1 Compatible +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/intel/dq45ek/cstates.c b/src/mainboard/intel/dq45ek/cstates.c new file mode 100644 index 0000000..21b18b9 --- /dev/null +++ b/src/mainboard/intel/dq45ek/cstates.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} diff --git a/src/mainboard/intel/dq45ek/data.vbt b/src/mainboard/intel/dq45ek/data.vbt new file mode 100644 index 0000000..c4a94cb --- /dev/null +++ b/src/mainboard/intel/dq45ek/data.vbt Binary files differ diff --git a/src/mainboard/intel/dq45ek/devicetree.cb b/src/mainboard/intel/dq45ek/devicetree.cb new file mode 100644 index 0000000..d574498 --- /dev/null +++ b/src/mainboard/intel/dq45ek/devicetree.cb @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/x4x # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x # CPU + device lapic 0xacac off end + end + end + device domain 0 on # PCI domain + subsystemid 0x8086 0x1004 inherit + device pci 0.0 on end # Host Bridge + device pci 2.0 on end # Integrated graphics controller + device pci 2.1 on end # Integrated graphics controller 2 + chip southbridge/intel/i82801jx # Southbridge + register "gpe0_en" = "0x28000140" + + register "sata_port_map" = "0x1f" + + register "pcie_slot_implemented" = "0x8" + + register "gen1_dec" = "0x00fc0a01" + + device pci 19.0 on end # GBE + device pci 1a.0 on end # USB + device pci 1a.1 on end # USB + device pci 1a.2 on end # USB + device pci 1a.7 on end # USB + device pci 1b.0 on end # Audio + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 off end # PCIe 2 + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 on end # PCIe 4 + device pci 1c.4 off end # PCIe 5 + device pci 1c.5 off end # PCIe 6 + device pci 1d.0 on end # USB + device pci 1d.1 on end # USB + device pci 1d.2 on end # USB + device pci 1d.7 on end # USB + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/winbond/wpcd376i # Super I/O + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel port + device pnp 2e.3 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 0x4 + irq 0xf0 = 0x2 + end + device pnp 2e.4 on # SWC + io 0x60 = 0xa00 + io 0x62 = 0xa10 + irq 0x70 = 0x0 + end + device pnp 2e.5 off end # Mouse + device pnp 2e.6 off end # Keyboard + device pnp 2e.7 on # GPIO + io 0x60 = 0xa20 + irq 0x70 = 0x0 + irq 0xf0 = 0x17 + irq 0xf1 = 0x03 + irq 0xf2 = 0x00 + irq 0xf3 = 0x00 + irq 0xf8 = 0x01 + end + device pnp 2e.15 off end # ECIR + device pnp 2e.16 off end # COM3 / IR + end + end + device pci 1f.2 on end # SATA + device pci 1f.3 on # SMBus + chip drivers/i2c/ck505 # SLG8XP549T + register "mask" = "{ 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff }" + register "regs" = "{ 0x91, 0xd9, 0xff, 0xff, + 0xff, 0x00, 0x00, 0x06, + 0x03, 0x25, 0x01, 0x80, 0x0d }" + device i2c 69 on end + end + end + device pci 1f.5 off end # IDE + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/intel/dq45ek/dsdt.asl b/src/mainboard/intel/dq45ek/dsdt.asl new file mode 100644 index 0000000..de548d1 --- /dev/null +++ b/src/mainboard/intel/dq45ek/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20090419 // OEM revision +) +{ + // global NVS and variables + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/i82801jx/acpi/globalnvs.asl> + + Scope (_SB) { + Device (PCI0) + { + #include <northbridge/intel/x4x/acpi/x4x.asl> + #include <southbridge/intel/i82801jx/acpi/ich10.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/intel/dq45ek/early_init.c b/src/mainboard/intel/dq45ek/early_init.c new file mode 100644 index 0000000..dffde0a --- /dev/null +++ b/src/mainboard/intel/dq45ek/early_init.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootblock_common.h> +#include <northbridge/intel/x4x/x4x.h> +#include <southbridge/intel/i82801jx/i82801jx.h> +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/wpcd376i/wpcd376i.h> + +#define SERIAL_DEV PNP_DEV(0x2e, WPCD376I_SP1) + +void bootblock_mainboard_early_init(void) +{ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[2] = 0x52; +} diff --git a/src/mainboard/intel/dq45ek/gma-mainboard.ads b/src/mainboard/intel/dq45ek/gma-mainboard.ads new file mode 100644 index 0000000..8b07c07 --- /dev/null +++ b/src/mainboard/intel/dq45ek/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + HDMI2, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/intel/dq45ek/gpio.c b/src/mainboard/intel/dq45ek/gpio.c new file mode 100644 index 0000000..1c64b2f --- /dev/null +++ b/src/mainboard/intel/dq45ek/gpio.c @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio18 = GPIO_BLINK, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio72 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { }; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, + +}; diff --git a/src/mainboard/intel/dq45ek/hda_verb.c b/src/mainboard/intel/dq45ek/hda_verb.c new file mode 100644 index 0000000..6a29631 --- /dev/null +++ b/src/mainboard/intel/dq45ek/hda_verb.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x11d41882, // Vendor ID + 0x80861004, // Subsystem ID + 11, // Number of entries + + /* Pin Widget Verb Table */ + + AZALIA_PIN_CFG(0, 0x11, 0x02214030), + AZALIA_PIN_CFG(0, 0x12, 0x01014010), + AZALIA_PIN_CFG(0, 0x13, 0x511711f0), + AZALIA_PIN_CFG(0, 0x14, 0x02a19040), + AZALIA_PIN_CFG(0, 0x15, 0x0181302e), + AZALIA_PIN_CFG(0, 0x16, 0x41011012), + AZALIA_PIN_CFG(0, 0x17, 0x01a19020), + AZALIA_PIN_CFG(0, 0x18, 0x59331122), + AZALIA_PIN_CFG(0, 0x1a, 0x91f711f0), + AZALIA_PIN_CFG(0, 0x1b, 0x4145f1a0), + AZALIA_PIN_CFG(0, 0x24, 0x41016011), +}; + +const u32 pc_beep_verbs[0] = {}; + +const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs); +const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data);
Samuel Holland has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44696 )
Change subject: mb/intel/dq45ek: Add new mainboard ......................................................................
Patch Set 2:
(3 comments)
I had this change marked WIP, so I could finish the IRQ routing and look at the ACPI tables and maybe C-states. But apparently I can't respond to comments unless I remove the WIP flag.
https://review.coreboot.org/c/coreboot/+/44696/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44696/1//COMMIT_MSG@13 PS1, Line 13: GPIO33
Where is it?
On the back of the board, underneath the ICH10. I marked it, but I forgot to take a photo before putting the board in a rather cramped case. I was planning to write up a documentation page with a picture, so I only put the notes here temporarily.
https://review.coreboot.org/c/coreboot/+/44696/1//COMMIT_MSG@17 PS1, Line 17: fan control
This board uses Intel Quiet System Technology, which means the ME does fan control. It's expected. […]
Both fans are affected, as both are driven by the PCH. The SuperIO has no fan control.
https://review.coreboot.org/c/coreboot/+/44696/1/src/mainboard/intel/dq45ek/... File src/mainboard/intel/dq45ek/gpio.c:
https://review.coreboot.org/c/coreboot/+/44696/1/src/mainboard/intel/dq45ek/... PS1, Line 88: static const struct pch_gpio_set3 pch_gpio_set3_mode = { : .gpio72 = GPIO_MODE_GPIO, : }; : : static const struct pch_gpio_set3 pch_gpio_set3_direction = { : .gpio72 = GPIO_DIR_INPUT, : }; : : static const struct pch_gpio_set3 pch_gpio_set3_level = { };
Do these exist on ICH10?
GPIO72 is described in section 13.10.12 of the datasheet. The values are copied from inteltool output.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44696 )
Change subject: mb/intel/dq45ek: Add new mainboard ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44696/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44696/1//COMMIT_MSG@20 PS1, Line 20: * SeaBIOS, Tianocore
Please add the versions.
Done
https://review.coreboot.org/c/coreboot/+/44696/1//COMMIT_MSG@25 PS1, Line 25: * S3 suspend/resume
Please add the OS, you tested this with.
Done
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44696 )
Change subject: mb/intel/dq45ek: Add new mainboard ......................................................................
Patch Set 2: Code-Review+1
(2 comments)
Patch Set 2:
(3 comments)
I had this change marked WIP, so I could finish the IRQ routing and look at the ACPI tables and maybe C-states. But apparently I can't respond to comments unless I remove the WIP flag.
Only the PCI slots have fixed IRQ routing. You can optimize the routing of the other DEV/FN's (the ACPI code is generated automatically) via RCBA DxxIR.
https://review.coreboot.org/c/coreboot/+/44696/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44696/1//COMMIT_MSG@17 PS1, Line 17: fan control
Both fans are affected, as both are driven by the PCH. The SuperIO has no fan control.
I observed the same on my Intel DG43GT.
https://review.coreboot.org/c/coreboot/+/44696/2/src/mainboard/intel/dq45ek/... File src/mainboard/intel/dq45ek/early_init.c:
https://review.coreboot.org/c/coreboot/+/44696/2/src/mainboard/intel/dq45ek/... PS2, Line 5: #include <southbridge/intel/i82801jx/i82801jx.h> I think you can drop this?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44696 )
Change subject: mb/intel/dq45ek: Add new mainboard ......................................................................
Patch Set 2: Code-Review+1
(9 comments)
https://review.coreboot.org/c/coreboot/+/44696/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44696/1//COMMIT_MSG@13 PS1, Line 13: GPIO33
On the back of the board, underneath the ICH10. […]
Ack
https://review.coreboot.org/c/coreboot/+/44696/1//COMMIT_MSG@16 PS1, Line 16: At that point
Instead, I'd say: […]
Done
https://review.coreboot.org/c/coreboot/+/44696/1/src/mainboard/intel/dq45ek/... File src/mainboard/intel/dq45ek/cmos.layout:
https://review.coreboot.org/c/coreboot/+/44696/1/src/mainboard/intel/dq45ek/... PS1, Line 6: # ----------------------------------------------------------------- : # Status Register A : # ----------------------------------------------------------------- : # Status Register B : # ----------------------------------------------------------------- : # Status Register C : #96 4 r 0 status_c_rsvd : #100 1 r 0 uf_flag : #101 1 r 0 af_flag : #102 1 r 0 pf_flag : #103 1 r 0 irqf_flag : # ----------------------------------------------------------------- : # Status Register D : #104 7 r 0 status_d_rsvd : #111 1 r 0 valid_cmos_ram : # ----------------------------------------------------------------- : # Diagnostic Status Register : #112 8 r 0 diag_rsvd1
IMHO this isn't very useful, and I'd drop it
Done
https://review.coreboot.org/c/coreboot/+/44696/1/src/mainboard/intel/dq45ek/... PS1, Line 27: unused
All commented-out `unused` entries can go away
Done
https://review.coreboot.org/c/coreboot/+/44696/1/src/mainboard/intel/dq45ek/... PS1, Line 88: 11 9 96M : 11 10 160M : 11 11 224M : 11 12 352M
This seems to be misaligned
Done
https://review.coreboot.org/c/coreboot/+/44696/2/src/mainboard/intel/dq45ek/... File src/mainboard/intel/dq45ek/cmos.layout:
https://review.coreboot.org/c/coreboot/+/44696/2/src/mainboard/intel/dq45ek/... PS2, Line 8: #120 264 r 0 unused This one, too
https://review.coreboot.org/c/coreboot/+/44696/1/src/mainboard/intel/dq45ek/... File src/mainboard/intel/dq45ek/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/44696/1/src/mainboard/intel/dq45ek/... PS1, Line 84: IDE
Strictly speaking, this is SATA ports 4 and 5 when operating in IDE mode
Done
https://review.coreboot.org/c/coreboot/+/44696/1/src/mainboard/intel/dq45ek/... File src/mainboard/intel/dq45ek/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/44696/1/src/mainboard/intel/dq45ek/... PS1, Line 17: {
nit: move this brace to the next line for consistency
Done
https://review.coreboot.org/c/coreboot/+/44696/1/src/mainboard/intel/dq45ek/... File src/mainboard/intel/dq45ek/gpio.c:
https://review.coreboot.org/c/coreboot/+/44696/1/src/mainboard/intel/dq45ek/... PS1, Line 88: static const struct pch_gpio_set3 pch_gpio_set3_mode = { : .gpio72 = GPIO_MODE_GPIO, : }; : : static const struct pch_gpio_set3 pch_gpio_set3_direction = { : .gpio72 = GPIO_DIR_INPUT, : }; : : static const struct pch_gpio_set3 pch_gpio_set3_level = { };
GPIO72 is described in section 13.10.12 of the datasheet. […]
Ack
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44696 )
Change subject: mb/intel/dq45ek: Add new mainboard ......................................................................
Patch Set 2:
apparently I can't respond to comments unless I remove the WIP flag.
You can, but in "WIP mode", the Gerrit UI shuffles buttons a bit. There's a "Start review" button and another one ("Save", I think?) in the other corner that just stores the comments. I _think_ that will be fixed in upcoming versions of Gerrit, but right now there's some hunting involved.
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/44696?usp=email )
Change subject: mb/intel/dq45ek: Add new mainboard ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
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Angel Pons (Code Review) -
Arthur Heymans (Code Review)
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Martin L Roth (Code Review)
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Patrick Georgi (Code Review)
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Paul Menzel (Code Review)
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Samuel Holland (Code Review)