Thomas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48769 )
Change subject: mb/yanling: Add Yanling YL-KBR6L mainboard + doc ......................................................................
mb/yanling: Add Yanling YL-KBR6L mainboard + doc
The Yanling YL-KBR6L (aka Yanling N18) is a Protecli FW6 with a newer CPUs (i5-8250U), different SuperIO chip (ITE IT8613F), slightly different (newer?) flash memory chip (MX25L6436F) and support for a mPCIe modem.
Working: - USB 3.0 front ports (SeaBIOS, Linux and FreeBSD) - 6 Ethernet ports - HDMI port with libgfxinit and VGA Option ROM - flashrom - PCIe WiFi - SATA and mSATA - mPCIe Modem in mSATA slot (tested with Simcom SIM7100E mPCIe) - Super I/O serial port 0 (RS232 via front RJ45 connector) - SeaBIOS payload (version rel-1.14.0) - Booting Ubuntu 20.04, FreeBSD 12.2 - 64GB RAM (tested with Crucial CT2K32G4SFD8266)
Untested (same as Protectli FW6): - Internal USB 2.0 headers - Boot with cleaned ME
Misc: - Removed "ProbelessTrace" in devicetree as done for other boards by coreboot.
Change-Id: Icbc18914670f87f0943b371400c509ff0eeacf6a Signed-off-by: Thomas Kupper thomas.kupper@gmail.com --- M Documentation/mainboard/index.md A Documentation/mainboard/yanling/yl-kbr6l.md A Documentation/mainboard/yanling/yl-kbr6l_front.jpg A src/mainboard/yanling/Kconfig A src/mainboard/yanling/Kconfig.name A src/mainboard/yanling/yl_kbr6l/Kconfig A src/mainboard/yanling/yl_kbr6l/Kconfig.name A src/mainboard/yanling/yl_kbr6l/Makefile.inc A src/mainboard/yanling/yl_kbr6l/acpi/ec.asl A src/mainboard/yanling/yl_kbr6l/acpi/superio.asl A src/mainboard/yanling/yl_kbr6l/board_info.txt A src/mainboard/yanling/yl_kbr6l/bootblock.c A src/mainboard/yanling/yl_kbr6l/data.vbt A src/mainboard/yanling/yl_kbr6l/devicetree.cb A src/mainboard/yanling/yl_kbr6l/dsdt.asl A src/mainboard/yanling/yl_kbr6l/gma-mainboard.ads A src/mainboard/yanling/yl_kbr6l/gpio.h A src/mainboard/yanling/yl_kbr6l/ramstage.c A src/mainboard/yanling/yl_kbr6l/romstage.c 19 files changed, 820 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/48769/1
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 95efe55..2480069 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -179,3 +179,7 @@ ## UP
- [Squared](up/squared/index.md) + +## Yanling + +- [YL-KBR6L](yanling/yl-kbr6l.md) \ No newline at end of file diff --git a/Documentation/mainboard/yanling/yl-kbr6l.md b/Documentation/mainboard/yanling/yl-kbr6l.md new file mode 100644 index 0000000..28d1d56 --- /dev/null +++ b/Documentation/mainboard/yanling/yl-kbr6l.md @@ -0,0 +1,133 @@ +# Yanling YL-KBR6L + +This board and therefore its documentation is very, very similar to the Protectli FW6. This document is based on theirs, all praise to 3mdeb/Protectli. + +This page describes how to run coreboot on the [Yanling YL-KBR6L], or [Yanling N18] as it seems to be called officially (and its three CPU variants). + + + +## Required proprietary blobs + +To build a minimal working coreboot image some blobs are required (assuming +only the BIOS region is being modified). + +```eval_rst ++-----------------+---------------------------------+---------------------+ +| Binary file | Apply | Required / Optional | ++=================+=================================+=====================+ +| FSP-M, FSP-S | Intel Firmware Support Package | Required | ++-----------------+---------------------------------+---------------------+ +| microcode | CPU microcode | Required | ++-----------------+---------------------------------+---------------------+ +| vgabios | VGA Option ROM | Optional | ++-----------------+---------------------------------+---------------------+ +``` + +FSP-M and FSP-S are obtained after splitting the Kaby Lake FSP binary (done +automatically by the coreboot build system and included into the image) from +the `3rdparty/fsp` submodule. + +Microcode updates are automatically included into the coreboot image by build +system from the `3rdparty/intel-microcode` submodule. + +VGA Option ROM is not required to boot, but if one needs graphics in pre-OS +stage, it should be included (if not using libgfxinit). + +## Flashing coreboot + +### Internal programming + +The main SPI flash can be accessed using [flashrom]. The first version +supporting the chipset is flashrom v1.1. Firmware an be easily flashed +with internal programmer (either BIOS region or full image). + +### External programming + +The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip. +This chip is located on the bottom side of the case (the radiator side). One +has to remove all screws (in order): 4 top cover screws, 4 side cover screws +(one side is enough), 4 mainboard screws, 4 CPU screws (under DIMMs). Lift up +the mainboard and turn around it. The flash chip is near the SoC on the DIMM +slots side. Use a clip (or solder the wires) to program the chip. Specifically, +it's a Macronix MX25L6436F M2I-08Q (3V) - [datasheet][MX25L6436F]. + +## Known issues + +- assume the same as for Protectli FW6: + +- After flashing with external programmer it is always required to reset RTC + with jumper or disconnect coin cell temporarily. Only then the platform will + boot after flashing. +- FW6A does not always work reliably with all DIMMs. Linux happens to hang or + gives many panics. This issue was present also with vendor BIOS. +- Sometimes FSPMemoryInit return errors or hangs (especially with 2 DIMMs + connected). A workaround is to power cycle the board (even a few times) or + temporarily disconnect DIMM when platform is powered off. +- When using libgfxinit and SeaBIOS bootsplash, the red color is dim + +## Untested + +- assume the same as for Protectli FW6: + +Not all mainboard's peripherals and functions were tested because of lack of +the cables or not being populated on the board case. + +- Internal USB 2.0 headers +- Boot with cleaned ME + +## Working + +- USB 3.0 front ports (SeaBIOS and Linux) +- 6 Ethernet ports +- HDMI port with libgfxinit and VGA Option ROM +- flashrom +- PCIe WiFi +- SATA and mSATA +- mPCIe Modem in mSATA slot (tested with Simcom SIM7100E mPCIe) +- Super I/O serial port 0 (RS232 via front RJ45 connector) +- SeaBIOS payload (version rel-1.14) +- Booting Ubuntu 20.04, FreeBSD 12.2 +- 64GB RAM (tested with Crucial CT2K32G4SFD8266) + +## Technology + +```eval_rst ++---------------------+-----------------------------------------------+ +| CPU | [Intel Core i5-8250U] | ++---------------------+-----------------------------------------------+ +| PCH | Kaby Lake U w/ iHDCP2.2 Premium | ++---------------------+-----------------------------------------------+ +| Super I/O, EC | ITE IT8613F | ++---------------------+-----------------------------------------------+ +| Coprocessor | Intel Management Engine | ++---------------------+-----------------------------------------------+ +| Ethernet Controller | 6x Intel I211AT | ++---------------------+-----------------------------------------------+ +``` +Information about the PCH can be found in [Intel 7th and 8th gen datasheet vol 1] and [Intel 7th and 8th gen datasheet vol 2]. + +## Ports + +```eval_rst ++---------------------+-----------------------------------------------+ +| Ethernet | 6x 1GbE | ++---------------------+-----------------------------------------------+ +| USB | 4x USB 3.0 | ++---------------------+-----------------------------------------------+ +| Serial/COM | 1x RJ-45 serial port | ++---------------------+-----------------------------------------------+ +| SATA | 1x mSATA (port 0) + 1x SATA 3.0 (port 1) | ++---------------------+-----------------------------------------------+ +| Cellular Modem | 1x mPCIe, shared with mSATA slot, nano-SIM | ++---------------------+-----------------------------------------------+ +| Wifi/Bluetooth | 1x mPCIe slot, under mSATA/Modem, | +| | supports half-size cards only | ++---------------------+-----------------------------------------------+ +``` + +[flashrom]: https://flashrom.org/Flashrom +[Intel 7th and 8th gen datasheet vol 1]: https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/7th-... +[Intel 7th and 8th gen datasheet vol 2]: https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/7th-... +[MX25L6436F]: https://www.mxic.com.tw/Lists/Datasheet/Attachments/7405/MX25L6436F,%203V,%2... +[Yanling YL-KBR6L]: https://www.aliexpress.com/item/1005001813291053.html +[Yanling N18]:https://www.ylipc.com/product/network_server_network_server/N18_Firewall_Min... diff --git a/Documentation/mainboard/yanling/yl-kbr6l_front.jpg b/Documentation/mainboard/yanling/yl-kbr6l_front.jpg new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/Documentation/mainboard/yanling/yl-kbr6l_front.jpg diff --git a/src/mainboard/yanling/Kconfig b/src/mainboard/yanling/Kconfig new file mode 100644 index 0000000..2972a38 --- /dev/null +++ b/src/mainboard/yanling/Kconfig @@ -0,0 +1,15 @@ +if VENDOR_YANLING + +choice + prompt "Mainboard model" + +source "src/mainboard/yanling/*/Kconfig.name" + +endchoice + +source "src/mainboard/yanling/*/Kconfig" + +config MAINBOARD_VENDOR + default "Yanling" + +endif # VENDOR_YANLING diff --git a/src/mainboard/yanling/Kconfig.name b/src/mainboard/yanling/Kconfig.name new file mode 100644 index 0000000..6cc7ef1 --- /dev/null +++ b/src/mainboard/yanling/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_YANLING + bool "Yanling" diff --git a/src/mainboard/yanling/yl_kbr6l/Kconfig b/src/mainboard/yanling/yl_kbr6l/Kconfig new file mode 100644 index 0000000..838bc44 --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/Kconfig @@ -0,0 +1,57 @@ +if BOARD_YANLING_YLKBR6L + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS + select SOC_INTEL_KABYLAKE + select SPI_FLASH_MACRONIX + select SUPERIO_ITE_IT8613E + select MAINBOARD_HAS_CRB_TPM + select HAVE_INTEL_PTT + select TPM2 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_DIR + string + default "yanling/yl_kbr6l" + +config MAINBOARD_PART_NUMBER + string + default "YLKBR6L" + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config MAX_CPUS + int + default 8 + +config VGA_BIOS_ID + string + default "8086,5917" + +config PXE_ROM_ID + string + default "8086,1539" + +config CBFS_SIZE + hex + default 0x600000 + +config USE_PM_ACPI_TIMER + default n + +endif diff --git a/src/mainboard/yanling/yl_kbr6l/Kconfig.name b/src/mainboard/yanling/yl_kbr6l/Kconfig.name new file mode 100644 index 0000000..8b039de --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_YANLING_YLKBR6L + bool "YLKBR6L" diff --git a/src/mainboard/yanling/yl_kbr6l/Makefile.inc b/src/mainboard/yanling/yl_kbr6l/Makefile.inc new file mode 100644 index 0000000..4cd7aac --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += bootblock.c + +ramstage-y += ramstage.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/yanling/yl_kbr6l/acpi/ec.asl b/src/mainboard/yanling/yl_kbr6l/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/acpi/ec.asl diff --git a/src/mainboard/yanling/yl_kbr6l/acpi/superio.asl b/src/mainboard/yanling/yl_kbr6l/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/acpi/superio.asl diff --git a/src/mainboard/yanling/yl_kbr6l/board_info.txt b/src/mainboard/yanling/yl_kbr6l/board_info.txt new file mode 100644 index 0000000..c12e388 --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Yanling +Board name: YL-KBR6L +Category: sbc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/yanling/yl_kbr6l/bootblock.c b/src/mainboard/yanling/yl_kbr6l/bootblock.c new file mode 100644 index 0000000..e35a7cc --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/bootblock.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootblock_common.h> +#include <superio/ite/it8613e/it8613e.h> +#include <superio/ite/common/ite.h> + +#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO) +#define UART_DEV PNP_DEV(0x2e, IT8613E_SP1) + +void bootblock_mainboard_early_init(void) +{ + ite_reg_write(GPIO_DEV, 0x2c, 0x41); /* disable K8 power seq */ + ite_reg_write(GPIO_DEV, 0x2d, 0x02); /* PCICLK 25MHz */ + ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/yanling/yl_kbr6l/data.vbt b/src/mainboard/yanling/yl_kbr6l/data.vbt new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/data.vbt diff --git a/src/mainboard/yanling/yl_kbr6l/devicetree.cb b/src/mainboard/yanling/yl_kbr6l/devicetree.cb new file mode 100644 index 0000000..b57ab96 --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/devicetree.cb @@ -0,0 +1,278 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "1" + register "deep_s5_enable_dc" = "1" + register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" + register "s0ix_enable" = "1" + + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x007c0a01" + register "gen3_dec" = "0x000c03e1" + register "gen4_dec" = "0x001c02e1" + + register "eist_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # Enable VT-d + register "ignore_vtd" = "0" + + # Enable SERIRQ continuous + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + register "tcc_offset" = "5" # TCC of 95C + + # FSP Configuration + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "DspEnable" = "0" + register "IoBufferOwnership" = "0" + register "SsicPortEnable" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "SkipExtGfxScan" = "1" + register "HeciEnabled" = "1" + register "SaGv" = "SaGv_Enabled" + register "IslVrCmd" = "2" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "4" # 4s + register "PmConfigSlpSusMinAssert" = "1" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m | + #| DcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m | + #+----------------+-------+-------+-------+-------+ + #Note: IccMax settings are moved to SoC code + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Enable SATA ports 1,2 + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "0" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "0" + + # Enable Root ports. 1-6 for LAN and Root Port 9 + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[8]" = "1" # mPCIe WiFi + + # Enable Advanced Error Reporting for RP 1-6, 9 + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpAdvancedErrorReporting[1]" = "1" + register "PcieRpAdvancedErrorReporting[2]" = "1" + register "PcieRpAdvancedErrorReporting[3]" = "1" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpAdvancedErrorReporting[5]" = "1" + register "PcieRpAdvancedErrorReporting[8]" = "1" + + # Enable Latency Tolerance Reporting Mechanism RP 1-6, 9 + register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[1]" = "1" + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[8]" = "1" + + # TODO: Check why protectli used them and WiFi won't work + # for me if I set them -> err: lost pci device + # Enable RP 9 CLKREQ# support + #register "PcieRpClkReqSupport[8]" = "1" + # RP 9 uses CLKREQ0# + #register "PcieRpClkReqNumber[8]" = "0" + + # Clocks 0-5 for RP 1-6 + register "PcieRpClkSrcNumber[0]" = "0" + register "PcieRpClkSrcNumber[1]" = "1" + register "PcieRpClkSrcNumber[2]" = "2" + register "PcieRpClkSrcNumber[3]" = "3" + register "PcieRpClkSrcNumber[4]" = "4" + register "PcieRpClkSrcNumber[5]" = "5" + # RP 9 shares CLKSRC5# with RP 6 + register "PcieRpClkSrcNumber[8]" = "5" + + + # USB 2.0 enable ports 1-8, disable ports 9-12 + register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # Type-A Port + register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # mPCIe slot + + # USB 3.0 enable ports 1-4, disable ports 5-6 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ + }" + + # Lock Down CHIPSET_LOCKDOWN_COREBOOT + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # 8086 5914 - Host Bridge + device pci 02.0 on end # 8086 5917 - Integrated Graphics Device + device pci 04.0 off end # 8086 ???? - SA thermal subsystem + device pci 05.0 off end # 8086 ???? - SA IMGU + device pci 08.0 off end # 8086 ???? - Gaussian Mixture Model + device pci 13.0 off end # 8086 9d35 - Integrated Sensor Hub + device pci 14.0 on end # 8086 9d2f - USB xHCI + device pci 14.1 off end # 8086 9d30 - USB xDCI (OTG) + device pci 14.2 off end # 8086 9d31 - Thermal Subsystem + device pci 14.3 off end # 8086 9d32 - Camera I/O Host Controller + device pci 15.0 off end # 8086 9d60 - I2C #0 + device pci 15.1 off end # 8086 9d61 - I2C #1 + device pci 15.2 off end # 8086 9d62 - I2C #2 + device pci 15.3 off end # 8086 9d63 - I2C #3 + device pci 16.0 on end # 8086 9d3a - Management Engine Interface 1 + device pci 16.1 off end # 8086 9d3b - Management Engine Interface 2 + device pci 16.2 off end # 8086 9d3c - Management Engine IDE-Redirection + device pci 16.3 off end # 8086 9d3d - Management Engine KT Redirection + device pci 16.4 off end # 8086 9d3e - Management Engine Interface 3 + device pci 17.0 on end # 8086 9d03 - SATA + device pci 19.0 off end # 8086 9d66 - UART #2 + device pci 19.1 off end # 8086 9d65 - I2C #5 + device pci 19.2 off end # 8086 9d64 - I2C #4 + device pci 1c.0 on end # 8086 9d10 - PCI Express Port 1 + device pci 1c.1 on end # 8086 9d11 - PCI Express Port 2 + device pci 1c.2 on end # 8086 9d12 - PCI Express Port 3 + device pci 1c.3 on end # 8086 9d13 - PCI Express Port 4 + device pci 1c.4 on end # 8086 9d14 - PCI Express Port 5 + device pci 1c.5 on end # 8086 9d15 - PCI Express Port 6 + device pci 1c.6 off end # 8086 9d16 - PCI Express Port 7 + device pci 1c.7 off end # 8086 9d17 - PCI Express Port 8 + device pci 1d.0 on # 8086 9d18 - PCI Express Port 9 - WiFi + smbios_slot_desc + "SlotTypePciExpressMini52pinWithoutBSKO" + "SlotLengthShort" "WIFI1" "SlotDataBusWidth1X" + end + device pci 1d.1 off end # 8086 9d19 - PCI Express Port 10 + device pci 1d.2 off end # 8086 9d1a - PCI Express Port 11 + device pci 1d.3 off end # 8086 9d1b - PCI Express Port 12 + device pci 1e.0 off end # 8086 9d27 - UART #0 + device pci 1e.1 off end # 8086 9d28 - UART #1 + device pci 1e.2 off end # 8086 9d29 - GSPI #0 + device pci 1e.3 off end # 8086 9d2a - GSPI #1 + device pci 1e.4 off end # 8086 9d2b - eMMC + device pci 1e.5 off end # 8086 ???? - SDIO + device pci 1e.6 off end # 8086 9d2d = SDXC + device pci 1f.0 on # 8086 9d4e - LPC Controller + chip superio/ite/it8613e + device pnp 2e.0 off end + device pnp 2e.1 on # COM 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off end # Environment Controller + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # CIR + end + end # LPC Interface + device pci 1f.1 on end # 8086 9d20 - P2SB + device pci 1f.2 on end # 8086 9d21 - Power Management Controller + device pci 1f.3 off end # 8086 9d71 - Intel HDA + device pci 1f.4 on end # 8086 9d23 - SMBus + device pci 1f.5 off end # 8086 9d24 - PCH SPI + device pci 1f.6 off end # 8086 9d25 - GbE + end + chip drivers/crb + device mmio 0xfed40000 on end + end +end diff --git a/src/mainboard/yanling/yl_kbr6l/dsdt.asl b/src/mainboard/yanling/yl_kbr6l/dsdt.asl new file mode 100644 index 0000000..3de4e26 --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/dsdt.asl @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/skylake/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (_SB.PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/yanling/yl_kbr6l/gma-mainboard.ads b/src/mainboard/yanling/yl_kbr6l/gma-mainboard.ads new file mode 100644 index 0000000..0e0f4f8 --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/gma-mainboard.ads @@ -0,0 +1,15 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/yanling/yl_kbr6l/gpio.h b/src/mainboard/yanling/yl_kbr6l/gpio.h new file mode 100644 index 0000000..7ec5a8a --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/gpio.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _GPIOFW6B_H +#define _GPIOFW6B_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), +/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), +/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), +/* PIRQA_N*/ PAD_CFG_TERM_GPO(GPP_A7, 1, NONE, DEEP), +/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* PCH_LPC_CLK0 */ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), +/* PCH_LPC_CLK1 */ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), +/* PME# */ PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1), +/* ISH_GP6 */ PAD_NC(GPP_A12, NONE), +/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* PCH_SUSSTAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), +/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN */ PAD_NC(GPP_A17, NONE), +/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), +/* VRALERT_N */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), +/* CPU_GP2 */ PAD_NC(GPP_B3, NONE), +/* CPU_GP3 */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0_N */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), +/* SRCCLKREQ1_N*/ PAD_NC(GPP_B6, NONE), +/* SRCCLKREQ2_N*/ PAD_NC(GPP_B7, NONE), +/* SRCCLKREQ3_N*/ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4_N*/ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5_N*/ PAD_NC(GPP_B10, NONE), +/* EXT_PWR_GATE_N */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* SPKR */ PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), +/* GSPI0_CS_N */ PAD_NC(GPP_B15, NONE), +/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE), +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* GSPI1_CS_N */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE), +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), +/* SM1ALERT# */ PAD_NC(GPP_B23, NONE), +/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1), +/* SML0_CLK */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, NONE), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_CTS_N */ PAD_NC(GPP_C10, NONE), +/* UART0_RTS_N */ PAD_NC(GPP_C11, NONE), +/* UART1_RXD */ PAD_NC(GPP_C12, NONE), +/* UART1_TXD */ PAD_NC(GPP_C13, NONE), +/* UART1_CTS_N */ PAD_NC(GPP_C14, NONE), +/* UART1_RTS_N */ PAD_NC(GPP_C15, NONE), +/* I2C0_SDA */ PAD_NC(GPP_C16, NONE), +/* I2C0_SCL */ PAD_NC(GPP_C17, NONE), +/* I2C1_SDA */ PAD_NC(GPP_C18, NONE), +/* I2C1_SCL */ PAD_NC(GPP_C19, NONE), +/* UART2_RXD */ PAD_NC(GPP_C20, NONE), +/* UART2_TXD */ PAD_NC(GPP_C21, NONE), +/* UART2_CTS_N */ PAD_NC(GPP_C22, NONE), +/* UART2_RTS_N */ PAD_NC(GPP_C23, NONE), +/* ITCH_SPI_CS */ PAD_NC(GPP_D0, NONE), +/* ITCH_SPI_CLK */ PAD_NC(GPP_D1, NONE), +/* ITCH_SPI_MISO_1 */ PAD_NC(GPP_D2, NONE), +/* ITCH_SPI_MISO_0 */ PAD_NC(GPP_D3, NONE), +/* FLASHTRIG */ PAD_NC(GPP_D4, NONE), +/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE), +/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* GPP_D9 */ PAD_NC(GPP_D9, NONE), +/* GPP_D10 */ PAD_NC(GPP_D10, NONE), +/* GPP_D11 */ PAD_NC(GPP_D11, NONE), +/* GPP_D12 */ PAD_NC(GPP_D12, NONE), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK_1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA_1 */ PAD_NC(GPP_D18, NONE), +/* DMIC_CLK_0 */ PAD_NC(GPP_D19, NONE), +/* DMIC_DATA_0 */ PAD_NC(GPP_D20, NONE), +/* ITCH_SPI_D2 */ PAD_NC(GPP_D21, NONE), +/* ITCH_SPI_D3 */ PAD_NC(GPP_D22, NONE), +/* I2S_MCLK */ PAD_NC(GPP_D23, NONE), +/* SATAXPCIE0 (TP8) */ PAD_NC(GPP_E0, NONE), +/* SATAXPCIE1 (TP9)*/ PAD_NC(GPP_E1, NONE), +/* SATAXPCIE2 (TP10) */ PAD_NC(GPP_E2, NONE), +/* CPU_GP0 */ PAD_NC(GPP_E3, NONE), +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* CPU_GP1 */ PAD_NC(GPP_E7, NONE), +/* SATA_LED */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* USB2_OC_0 */ PAD_NC(GPP_E9, NONE), +/* USB2_OC_1 */ PAD_NC(GPP_E10, NONE), +/* USB2_OC_2 */ PAD_NC(GPP_E11, NONE), +/* USB2_OC_3 */ PAD_NC(GPP_E12, NONE), +/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), +/* DDI2_HPD */ PAD_NC(GPP_E14, NONE), +/* DDI3_HPD */ PAD_NC(GPP_E15, NONE), +/* DDI4_HPD */ PAD_NC(GPP_E16, NONE), +/* EDP_HPD */ PAD_NC(GPP_E17, NONE), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), +/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), +/* I2S2_SCLK */ PAD_NC(GPP_F0, NONE), +/* I2S2_SFRM */ PAD_NC(GPP_F1, NONE), +/* I2S2_TXD */ PAD_NC(GPP_F2, NONE), +/* I2S2_RXD */ PAD_NC(GPP_F3, NONE), +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), +/* I2C4_SDA */ PAD_NC(GPP_F8, NONE), +/* I2C4_SDA */ PAD_NC(GPP_F9, NONE), +/* I2C5_SDA */ PAD_NC(GPP_F10, NONE), +/* I2C5_SCL */ PAD_NC(GPP_F11, NONE), +/* EMMC_CMD */ PAD_NC(GPP_F12, NONE), +/* EMMC_DATA0 */ PAD_NC(GPP_F13, NONE), +/* EMMC_DATA1 */ PAD_NC(GPP_F14, NONE), +/* EMMC_DATA2 */ PAD_NC(GPP_F15, NONE), +/* EMMC_DATA3 */ PAD_NC(GPP_F16, NONE), +/* EMMC_DATA4 */ PAD_NC(GPP_F17, NONE), +/* EMMC_DATA5 */ PAD_NC(GPP_F18, NONE), +/* EMMC_DATA6 */ PAD_NC(GPP_F19, NONE), +/* EMMC_DATA7 */ PAD_NC(GPP_F20, NONE), +/* EMMC_RCLK */ PAD_NC(GPP_F21, NONE), +/* EMMC_CLK */ PAD_NC(GPP_F22, NONE), +/* GPP_F23 */ PAD_NC(GPP_F23, NONE), +/* SD_CMD */ PAD_NC(GPP_G0, NONE), +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), +/* SD_CD# */ PAD_NC(GPP_G5, NONE), +/* SD_CLK */ PAD_NC(GPP_G6, NONE), +/* SD_WP */ PAD_NC(GPP_G7, NONE), +/* PCH_BATLOW */ PAD_NC(GPD0, NONE), +/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), +/* LAN_WAKE_N */ PAD_NC(GPD2, NONE), +/* PWRBTN */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), +/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* PM_SLP_SA# (TP7) */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), +/* GPD7_RSVD */ PAD_CFG_TERM_GPO(GPD7, 1, NONE, DEEP), +/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* SLP_WLAN# (TP6) */ PAD_NC(GPD9, NONE), +/* SLP_S5# (TP3) */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), +/* LANPHYC */ PAD_NC(GPD11, NONE), +}; + +#endif + +#endif diff --git a/src/mainboard/yanling/yl_kbr6l/ramstage.c b/src/mainboard/yanling/yl_kbr6l/ramstage.c new file mode 100644 index 0000000..9518b1d --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/ramstage.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/ramstage.h> + +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* + * Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. + */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + params->TurboMode = 1; + params->PchPort61hEnable = 1; + params->CdClock = 3; +} diff --git a/src/mainboard/yanling/yl_kbr6l/romstage.c b/src/mainboard/yanling/yl_kbr6l/romstage.c new file mode 100644 index 0000000..2b68e1a --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/romstage.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <fsp/api.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <string.h> + +static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1) +{ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); + memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); +} + +static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1) +{ + const u8 dqs_map[2][8] = { + { 0, 1, 2, 3, 4, 5, 6, 7 }, + { 1, 0, 2, 3, 4, 5, 6, 7 } }; + memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); + memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); +} + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + static const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, + &mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, + &mem_cfg->DqsMapCpu2DramCh1); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + struct spd_block blk = { + .addr_map = { 0x50, 0x52, }, + }; + + mem_cfg->DqPinsInterleaved = 1; + mem_cfg->CaVrefConfig = 2; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; +}
Thomas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48769 )
Change subject: mb/yanling: Add Yanling YL-KBR6L mainboard + doc ......................................................................
Patch Set 1:
Hi,
First time patch contributor, longer time user as I got an PC Engines APU2.
I was in contact with Michal Zygowski after I bought this Yanling N18/YL-KBR6L since I assumed that it's very, very close to the Protectli FW6. Looked like it was indeed the case and not too many modifications were necessary.
I have to add that I'm neither a firmware nor an embedded developer but a Linux Admin.
The code for the SuperIO is from Protectli vault_bsw and the rest from Protectli vaul_kbl. With changed device ids for video and LAN, of course.
I'm not sure if I have credited 3mdeb/Protectli enough and if not what should be added?
Cheers Thomas
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48769 )
Change subject: mb/yanling: Add Yanling YL-KBR6L mainboard + doc ......................................................................
Patch Set 1:
(15 comments)
https://review.coreboot.org/c/coreboot/+/48769/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48769/1//COMMIT_MSG@9 PS1, Line 9: Yanling YL-KBR6L Do you have an URL for that? (I know, some folks do not like URLs in commit messages.)
https://review.coreboot.org/c/coreboot/+/48769/1//COMMIT_MSG@15 PS1, Line 15: SeaBIOS, Linux and FreeBSD For the record, can you please also note down the used version of these?
https://review.coreboot.org/c/coreboot/+/48769/1//COMMIT_MSG@17 PS1, Line 17: VGA Option ROM Extracted how?
https://review.coreboot.org/c/coreboot/+/48769/1//COMMIT_MSG@18 PS1, Line 18: flashrom What version?
https://review.coreboot.org/c/coreboot/+/48769/1//COMMIT_MSG@25 PS1, Line 25: Crucial CT2K32G4SFD8266 Is that one DIMM with 64 GB?
https://review.coreboot.org/c/coreboot/+/48769/1//COMMIT_MSG@32 PS1, Line 32: Removed Present tense: Remove
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... File Documentation/mainboard/yanling/yl-kbr6l.md:
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... PS1, Line 3: Protectli FW6 Please link to the page.
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... PS1, Line 33: VGA Option ROM is not required to boot, but if one needs graphics in pre-OS : stage, it should be included (if not using libgfxinit). Maybe:
Graphics initialization is not required in firmware for graphics in the OS. But for graphics in pre-OS stage (payload), libgfxinit or the VGA Option ROM are required.
Is the GOP driver also supported (by FSP)?
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... PS1, Line 40: The main SPI flash can be accessed using [flashrom]. Maybe clarify, that this also applies to the vendor firmware.
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... PS1, Line 56: - assume the same as for Protectli FW6: Remove the “bullet point”?
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... PS1, Line 63: return returns
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... PS1, Line 64: or : temporarily disconnect or *to* temporarily disconnect
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... PS1, Line 66: dim What does that mean?
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... PS1, Line 70: - assume the same as for Protectli FW6: Remove the “bullet point”?
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... PS1, Line 133: [Yanling N18]:https://www.ylipc.com/product/network_server_network_server/N18_Firewall_Min... Please add a space after the colon.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48769 )
Change subject: mb/yanling: Add Yanling YL-KBR6L mainboard + doc ......................................................................
Patch Set 1:
Is it close enough to the Protectli FW6, so it could be added as a variant?
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48769 )
Change subject: mb/yanling: Add Yanling YL-KBR6L mainboard + doc ......................................................................
Patch Set 1:
(10 comments)
https://review.coreboot.org/c/coreboot/+/48769/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48769/1//COMMIT_MSG@17 PS1, Line 17: VGA Option ROM
Extracted how?
Extracting and adding vbt to the commit is also an option.
https://review.coreboot.org/c/coreboot/+/48769/1//COMMIT_MSG@25 PS1, Line 25: Crucial CT2K32G4SFD8266
Is that one DIMM with 64 GB?
It is rather 2x 32GB by searching for it on google.com
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... File Documentation/mainboard/yanling/yl-kbr6l.md:
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... PS1, Line 26: Kaby Lake FSP According to Intel FSP repository the Kaby Lake Refresh should use AmberlakeFspBinPkg https://github.com/intel/FSP#fsp-project-information. i5-8250 is Kaby Lake Refresh.
Does the platform boot with Kaby Lake FSP?
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... PS1, Line 33: VGA Option ROM is not required to boot, but if one needs graphics in pre-OS : stage, it should be included (if not using libgfxinit).
Maybe: […]
It should be with correct VBT. I don't actually remember why I have not written about VBT and GOP here.
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... PS1, Line 56: assume the same as for Protectli FW6 Does have to be the same
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... PS1, Line 61: FW6A There wouldn't be FW6A since it is Protectli platform variant, not Yanling.
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... PS1, Line 98: | PCH | Kaby Lake U w/ iHDCP2.2 Premium | Have you checked that the chipset is the same? Flashrom can detect the chipset and it's name may be different.
https://review.coreboot.org/c/coreboot/+/48769/1/src/mainboard/yanling/yl_kb... File src/mainboard/yanling/yl_kbr6l/bootblock.c:
https://review.coreboot.org/c/coreboot/+/48769/1/src/mainboard/yanling/yl_kb... PS1, Line 13: ite_reg_write(GPIO_DEV, 0x2d, 0x02); /* PCICLK 25MHz */ That will need a revisit of the Super I/O configuration for this platform. Although FW2B/FW4B had the same chip, the configuration may not be identical. Have you tried using superiotool on the original firmware?
https://review.coreboot.org/c/coreboot/+/48769/1/src/mainboard/yanling/yl_kb... File src/mainboard/yanling/yl_kbr6l/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48769/1/src/mainboard/yanling/yl_kb... PS1, Line 33: # FSP Configuration Some of the settings probably will change the names after Amberlake FSP integration
https://review.coreboot.org/c/coreboot/+/48769/1/src/mainboard/yanling/yl_kb... PS1, Line 151: # TODO: Check why protectli used them and WiFi won't work : # for me if I set them -> err: lost pci device Well, that depends on the routing of CLRREQ signals. If you can't get it working, then just remove the lines: ``` register "PcieRpClkReqSupport[8]" = "1" # RP 9 uses CLKREQ0# register "PcieRpClkReqNumber[8]" = "0" ``` And the clock will always be on in such case and the device shouldn't get lost.
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48769 )
Change subject: mb/yanling: Add Yanling YL-KBR6L mainboard + doc ......................................................................
Patch Set 1:
I'm not sure if I have credited 3mdeb/Protectli enough and if not what should be added?
Cheers Thomas
To me it is enough to be mentioned in board documentation. Anyway 3mdeb and Protectli is in the AUTHORS file, so there isn't any distinction about single files now.
First and foremost: does it boot well?
Thomas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48769 )
Change subject: mb/yanling: Add Yanling YL-KBR6L mainboard + doc ......................................................................
Patch Set 1:
(6 comments)
Patch Set 1:
Is it close enough to the Protectli FW6, so it could be added as a variant?
I assume it is close enough to be a variant of Protectli. My thinking was that if someone would have bought that Yanling computer she wouldn't look under Protectli for the mainboard source. And what name would we give that model?
Personally I think Protectli will get this and the faster model with i7-8550u cpu sooner or later.
While being in contact with Yanling because I couldn't get the 4G modem working with the stock firmware, they showed me screenshots of that it worked for them. The name of the Ubuntu workstation was 'ubuntu-FW6E' and the CPU was an i7-8550u. It certainly fits Protectlis naming. That would make this the FW6D model.
But adding it without the OK from Protectli or 3mdeb seems wrong to me.
https://review.coreboot.org/c/coreboot/+/48769/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48769/1//COMMIT_MSG@9 PS1, Line 9: Yanling YL-KBR6L
Do you have an URL for that? (I know, some folks do not like URLs in commit messages. […]
Hi Paul,
Thanks a lot for commenting.
Yes, I do have ULRs which are in the markdown document. I'm indeed not a big fan of URLs in commit messages, too. Since they are often longer then 75 chars.
Would it be enough to add a reference that the links can be found in the documentation?
https://review.coreboot.org/c/coreboot/+/48769/1//COMMIT_MSG@15 PS1, Line 15: SeaBIOS, Linux and FreeBSD
For the record, can you please also note down the used version of these?
I'll do that, yes.
https://review.coreboot.org/c/coreboot/+/48769/1//COMMIT_MSG@17 PS1, Line 17: VGA Option ROM
Extracting and adding vbt to the commit is also an option.
Most part of the commit message comes from the markdown document. And most of that is a one-to-one copy of the FW6 document.
That is one part of that. Maybe it's better if I remove all the parts which are already in the FW6 markdown and add only a reference to it?
To answer the question: I used 3mdebs VGA options rom, the download link which can be found in the excellent Protectli/3mdeb "coreboot-building-guide.pdf".
https://review.coreboot.org/c/coreboot/+/48769/1//COMMIT_MSG@18 PS1, Line 18: flashrom
What version?
I'll add the version.
https://review.coreboot.org/c/coreboot/+/48769/1//COMMIT_MSG@25 PS1, Line 25: Crucial CT2K32G4SFD8266
It is rather 2x 32GB by searching for it on google. […]
As Michal correctly said, it's 2x 32GB. I was avoiding to make the lines getting to long but I see it add confusion. I'll add the "2x32GB".
https://review.coreboot.org/c/coreboot/+/48769/1//COMMIT_MSG@32 PS1, Line 32: Removed
Present tense: Remove
Will be done.
Thomas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48769 )
Change subject: mb/yanling: Add Yanling YL-KBR6L mainboard + doc ......................................................................
Patch Set 1:
(15 comments)
Patch Set 1:
I'm not sure if I have credited 3mdeb/Protectli enough and if not what should be added?
Cheers Thomas
To me it is enough to be mentioned in board documentation. Anyway 3mdeb and Protectli is in the AUTHORS file, so there isn't any distinction about single files now.
First and foremost: does it boot well?
It does boot very well, a bit too fast so sometimes an USB stick won't be recognized but that's expected I guess.
And there is one error in the boot log regarding PCH_DEVFN_THERMAL device not found (line 7), which I haven't looked into it yet:
``` 1: ME: Error Code : No Error 2: ME: Progress Phase : Host Communication 3: ME: Power Management Event : Pseudo-global reset 4: ME: Progress Phase State : Host communication established 5: ME: Power Down Mitigation : NO 6: ME: FPF status : unfused 7: ERROR: PCH_DEVFN_THERMAL device not found! 8: Finalizing SMM. 9: APMC done. ```
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... File Documentation/mainboard/yanling/yl-kbr6l.md:
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... PS1, Line 3: Protectli FW6
Please link to the page.
Your right, I'll do that.
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... PS1, Line 26: Kaby Lake FSP
According to Intel FSP repository the Kaby Lake Refresh should use AmberlakeFspBinPkg https://github […]
It works very well, yes.
Looking at the "7th-and-8th-gen" document from Intel which you mentioned in an email, Kaby Lake and Kaby Lake Refresh where in the same category.
Nevertheless I'll have a look at the AmberlakeFspBinPkg and compare the settings.
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... PS1, Line 33: VGA Option ROM is not required to boot, but if one needs graphics in pre-OS : stage, it should be included (if not using libgfxinit).
It should be with correct VBT. […]
That is one of the parts which I took over one-to-one from the FW6 documenation.
I know nothing yet about GOP, had to look up what it means.
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... PS1, Line 40: The main SPI flash can be accessed using [flashrom].
Maybe clarify, that this also applies to the vendor firmware.
Again, part of the original FW6 documentation.
But yes I used to flash coreboot and the original firmware, although only the BIOS part.
So I should add that both coreboot and the vendor firmware can be flashed using internal programing?
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... PS1, Line 56: - assume the same as for Protectli FW6:
Remove the “bullet point”?
Will be done
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... PS1, Line 61: FW6A
There wouldn't be FW6A since it is Protectli platform variant, not Yanling.
You're right, as mentioned (way) earlier, it maybe better if I remove all the pure copy-paste from FW6 and only reference to the FW6 document.
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... PS1, Line 63: return
returns
Will be corrected.
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... PS1, Line 64: or : temporarily disconnect
or *to* temporarily disconnect
"or *to* temporarily disconnect *the* DIMS*s*"?
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... PS1, Line 66: dim
What does that mean?
Copy-paste from FW6 doc, no idea.
I created a bootsplash with my red Moto Guzzi Griso motorbike and the red colors look just right to me. Maybe Michal could elaborate?
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... PS1, Line 70: - assume the same as for Protectli FW6:
Remove the “bullet point”?
Will be done.
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... PS1, Line 98: | PCH | Kaby Lake U w/ iHDCP2.2 Premium |
Have you checked that the chipset is the same? Flashrom can detect the chipset and it's name may be […]
I ran the recommended tools before starting. And both the flashrom and "7th-and-8th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.pdf" let me to believe that it is indeed the same chipset.
--- flashrom.log --- DMI string chassis-type: "Desktop" DMI string system-manufacturer: "YANLING" DMI string system-product-name: "YL-KBR6L" DMI string system-version: "Ver:1.00" DMI string baseboard-manufacturer: "YANLING" DMI string baseboard-product-name: "YL-KBR6L" DMI string baseboard-version: "Ver:1.00" Found ITE Super I/O, ID 0x8613 on port 0x2e Found chipset "Intel Kaby Lake U w/ iHDCP2.2 Prem." with PCI ID 8086:9d4e. ---
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... PS1, Line 133: [Yanling N18]:https://www.ylipc.com/product/network_server_network_server/N18_Firewall_Min...
Please add a space after the colon.
I will do that.
https://review.coreboot.org/c/coreboot/+/48769/1/src/mainboard/yanling/yl_kb... File src/mainboard/yanling/yl_kbr6l/bootblock.c:
https://review.coreboot.org/c/coreboot/+/48769/1/src/mainboard/yanling/yl_kb... PS1, Line 13: ite_reg_write(GPIO_DEV, 0x2d, 0x02); /* PCICLK 25MHz */
That will need a revisit of the Super I/O configuration for this platform. […]
Yes I did use the superiotool on the original firmware but haven't look at anything else then the serial port. You are right I have to revisit that topic again.
Not sure if I'm allowed to dump some log in here:
--- superiotool.log Found ITE IT8613E (id=0x8613, rev=0x8) at 0x2e Register dump: idx 20 21 22 23 24 2b val 86 13 08 49 00 48 def 86 13 05 40 00 48 LDN 0x01 (COM1) idx 30 60 61 70 f0 val 01 03 f8 04 00 def 00 03 f8 04 00 LDN 0x04 (Environment controller) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 fa fb fc val 01 0a 30 0a 20 00 00 00 40 00 20 00 f0 00 00 00 def 00 02 90 02 30 09 00 00 00 00 00 NA NA 00 00 00 LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 71 f0 val 01 00 60 00 64 01 02 48 def 01 00 60 00 64 01 02 48 LDN 0x06 (Mouse) idx 30 70 71 f0 val 01 0c 02 00 def 00 0c 02 00 LDN 0x07 (GPIO) idx 25 26 27 28 29 2a 2c 2d 60 61 62 63 70 71 72 73 74 b0 b1 b2 b3 b4 b8 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc cd da db e0 e1 e2 e3 e4 ec f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb val 00 f3 00 00 00 01 41 02 0a 10 0a 00 00 08 10 00 00 00 00 00 00 00 00 00 00 c0 03 01 00 00 40 00 01 00 00 00 00 00 30 44 00 00 00 00 00 00 00 00 00 00 00 00 0e 00 00 00 00 00 def 00 f3 00 00 00 01 01 00 00 00 00 00 00 00 20 38 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA NA 00 00 0e 00 00 00 00 00 LDN 0x0a (Consumer IR) idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 06 Environment controller (0x0a35) Register dump: idx 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0e 0f 11 12 13 14 16 17 19 1a 1c 1d 1e 1f 20 21 22 24 25 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 38 39 3a 3b 40 41 42 43 44 45 46 47 50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f 68 69 6a 6b 6c 6d 6e 70 71 72 73 74 75 76 78 79 7a 7b 7c 7d 7e 80 81 82 83 84 85 86 87 88 89 8a 8b 8c 8d 8e 8f 90 91 98 99 9c 9d 9e 9f a0 a1 a2 a3 a4 a5 a6 b4 b5 b6 b7 b8 b9 val 19 90 df 09 00 00 00 00 00 c0 64 00 00 ff 00 ff ff a0 c0 80 00 ff 00 ff ff 00 00 32 60 98 5c 77 f0 8e 26 80 80 00 80 80 97 20 05 a8 e3 6c 9c 20 72 8a 6c ff 83 ff 64 ff 72 e7 1d 00 00 7f 7f 7f 40 63 00 90 00 00 12 e0 00 00 00 27 27 4f 64 18 00 0f 7f 7f 7f 80 00 00 0f 7f 7f 7f 80 00 00 0f 00 00 00 00 ff ff ff ff 02 30 01 02 01 78 e0 c6 00 00 40 00 00 d2 00 00 7f 7f 7f 80 00 00 0f 44 4c d7 82 3e 0d def 18 00 00 00 00 00 00 00 00 c0 44 00 00 MM MM NA NA 00 40 00 00 MM MM NA NA 00 00 MM MM MM MM MM MM MM MM MM MM MM MM MM MM NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 00 00 7f 7f 7f 40 00 00 90 00 00 12 60 00 00 00 7f 7f 7f 00 00 7f 0f 7f 7f 7f 00 00 7f 0f 7f 7f 7f 00 00 7f 0f MM MM MM MM NA NA NA NA 00 00 00 00 00 00 00 MM 00 00 00 00 00 NA 00 NA 7f 7f 7f 00 00 7f 0f NA NA NA NA NA NA BRAM (0x0000)
https://review.coreboot.org/c/coreboot/+/48769/1/src/mainboard/yanling/yl_kb... File src/mainboard/yanling/yl_kbr6l/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48769/1/src/mainboard/yanling/yl_kb... PS1, Line 33: # FSP Configuration
Some of the settings probably will change the names after Amberlake FSP integration
I'll look into the Amberlake FSB integration. The naming is confusing since it's not an Amberlake at all ... but that's just Intel I assume.
https://review.coreboot.org/c/coreboot/+/48769/1/src/mainboard/yanling/yl_kb... PS1, Line 151: # TODO: Check why protectli used them and WiFi won't work : # for me if I set them -> err: lost pci device
Well, that depends on the routing of CLRREQ signals. […]
I'll remove them.
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48769 )
Change subject: mb/yanling: Add Yanling YL-KBR6L mainboard + doc ......................................................................
Patch Set 1:
I have got some new information. Protectli is going to ship these platforms as their product. I got the hardware with 8550U CPU and will help to fix remaining things. We will have to change the platform name and vendor accordingly.
Thomas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48769 )
Change subject: mb/yanling: Add Yanling YL-KBR6L mainboard + doc ......................................................................
Patch Set 1:
(1 comment)
Patch Set 1:
I have got some new information. Protectli is going to ship these platforms as their product. I got the hardware with 8550U CPU and will help to fix remaining things. We will have to change the platform name and vendor accordingly.
Hey Michal,
That is good news. How are we going to proceed? Are you taking over? Should I change the platform name and vendor? The new models as variants in vault_kbl or create a new one, e.g. vault_kbr?
Or abandon this patch and you provide your fixed one?
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... File Documentation/mainboard/yanling/yl-kbr6l.md:
https://review.coreboot.org/c/coreboot/+/48769/1/Documentation/mainboard/yan... PS1, Line 3: Protectli FW6
Your right, I'll do that.
Maybe to clarify: link to the coreboot doc page or to their homepage? And if to their coreboot doc page: I don't know if relative links work so I would have to add an absolute link... which will break if the directory structure changes.
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/48769?usp=email )
Change subject: mb/yanling: Add Yanling YL-KBR6L mainboard + doc ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
-
Martin L Roth (Code Review) -
Michał Żygowski (Code Review)
-
Paul Menzel (Code Review)
-
Thomas (Code Review)