Mac Mini has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49074 )
Change subject: Apple Mac Mini (mid 2011) ......................................................................
Apple Mac Mini (mid 2011)
Autoported and tested on real device
Signed-off-by: Mac Mini mac-mini-2011@outlook.com Change-Id: Ied578e8a9c7ff2c041b5495491acb256019f1c6d --- A src/mainboard/apple/macmini5_1/Kconfig A src/mainboard/apple/macmini5_1/Kconfig.name A src/mainboard/apple/macmini5_1/Makefile.inc A src/mainboard/apple/macmini5_1/acpi/ec.asl A src/mainboard/apple/macmini5_1/acpi/platform.asl A src/mainboard/apple/macmini5_1/acpi/superio.asl A src/mainboard/apple/macmini5_1/acpi_tables.c A src/mainboard/apple/macmini5_1/board_info.txt A src/mainboard/apple/macmini5_1/devicetree.cb A src/mainboard/apple/macmini5_1/dsdt.asl A src/mainboard/apple/macmini5_1/early_init.c A src/mainboard/apple/macmini5_1/gma-mainboard.ads A src/mainboard/apple/macmini5_1/gpio.c A src/mainboard/apple/macmini5_1/hda_verb.c A src/mainboard/apple/macmini5_1/mainboard.c 15 files changed, 494 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/49074/1
diff --git a/src/mainboard/apple/macmini5_1/Kconfig b/src/mainboard/apple/macmini5_1/Kconfig new file mode 100644 index 0000000..edc994e --- /dev/null +++ b/src/mainboard/apple/macmini5_1/Kconfig @@ -0,0 +1,36 @@ +if BOARD_APPLE_MACMINI5_1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select USE_NATIVE_RAMINIT + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select MAINBOARD_HAS_LIBGFXINIT + # select HAVE_CMOS_DEFAULT + # select HAVE_OPTION_TABLE + +config MAINBOARD_DIR + string + default "apple/macmini5_1" + +config MAINBOARD_PART_NUMBER + string + default "Macmini5,1" + +config VGA_BIOS_FILE + string + default "pci8086,0126.rom" + +config VGA_BIOS_ID + string + default "8086,0126" + +config DRAM_RESET_GATE_GPIO + int + default 30 +endif diff --git a/src/mainboard/apple/macmini5_1/Kconfig.name b/src/mainboard/apple/macmini5_1/Kconfig.name new file mode 100644 index 0000000..bca6a27 --- /dev/null +++ b/src/mainboard/apple/macmini5_1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_APPLE_MACMINI5_1 + bool "Macmini5,1" diff --git a/src/mainboard/apple/macmini5_1/Makefile.inc b/src/mainboard/apple/macmini5_1/Makefile.inc new file mode 100644 index 0000000..e402ffa --- /dev/null +++ b/src/mainboard/apple/macmini5_1/Makefile.inc @@ -0,0 +1,6 @@ +bootblock-y += gpio.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/apple/macmini5_1/acpi/ec.asl b/src/mainboard/apple/macmini5_1/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/apple/macmini5_1/acpi/ec.asl diff --git a/src/mainboard/apple/macmini5_1/acpi/platform.asl b/src/mainboard/apple/macmini5_1/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/apple/macmini5_1/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/apple/macmini5_1/acpi/superio.asl b/src/mainboard/apple/macmini5_1/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/apple/macmini5_1/acpi/superio.asl diff --git a/src/mainboard/apple/macmini5_1/acpi_tables.c b/src/mainboard/apple/macmini5_1/acpi_tables.c new file mode 100644 index 0000000..161689d --- /dev/null +++ b/src/mainboard/apple/macmini5_1/acpi_tables.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/apple/macmini5_1/board_info.txt b/src/mainboard/apple/macmini5_1/board_info.txt new file mode 100644 index 0000000..85a3d5d --- /dev/null +++ b/src/mainboard/apple/macmini5_1/board_info.txt @@ -0,0 +1,6 @@ +Category: mini +ROM protocol: SPI +Flashrom support: y +ROM package: SOIC-8 +ROM socketed: n +Release year: 2011 diff --git a/src/mainboard/apple/macmini5_1/devicetree.cb b/src/mainboard/apple/macmini5_1/devicetree.cb new file mode 100644 index 0000000..820bba9 --- /dev/null +++ b/src/mainboard/apple/macmini5_1/devicetree.cb @@ -0,0 +1,77 @@ +chip northbridge/intel/sandybridge + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0 on + subsystemid 0x8086 0x7270 inherit + + device pci 00.0 on # Host bridge + subsystemid 0x106b 0x00e6 + end + device pci 01.0 on # PCI Express Graphics + subsystemid 0x106b 0x00e6 + end + device pci 01.1 on # Thunderbolt + subsystemid 0x106b 0x00e6 + end + device pci 02.0 on # iGPU + subsystemid 0x106b 0x00e6 + end + device pci 04.0 off end # Signal Processing Controller ?? + + chip southbridge/intel/bd82x6x # Intel Series 6 Chipset + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x001c0301" + register "gen4_dec" = "0x00fc0701" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x2005" + + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1a.7 on end + + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # Ethernet Controller + device pci 1c.1 on end # Broadcom WiFi + device pci 1c.2 on end # FireWire + + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1d.7 on end + + device pci 1e.0 off end # PCI bridge + + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/apple/macmini5_1/dsdt.asl b/src/mainboard/apple/macmini5_1/dsdt.asl new file mode 100644 index 0000000..27d14ae --- /dev/null +++ b/src/mainboard/apple/macmini5_1/dsdt.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define BRIGHTNESS_UP _SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN _SB.PCI0.GFX0.DECB + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } +} diff --git a/src/mainboard/apple/macmini5_1/early_init.c b/src/mainboard/apple/macmini5_1/early_init.c new file mode 100644 index 0000000..c02d482 --- /dev/null +++ b/src/mainboard/apple/macmini5_1/early_init.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci_ops.h> +#include <device/pci_def.h> +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/apple/macmini5_1/gma-mainboard.ads b/src/mainboard/apple/macmini5_1/gma-mainboard.ads new file mode 100644 index 0000000..e07e1e9 --- /dev/null +++ b/src/mainboard/apple/macmini5_1/gma-mainboard.ads @@ -0,0 +1,13 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := (DP1, HDMI1, DP3, HDMI3, others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/apple/macmini5_1/gpio.c b/src/mainboard/apple/macmini5_1/gpio.c new file mode 100644 index 0000000..e69fd26 --- /dev/null +++ b/src/mainboard/apple/macmini5_1/gpio.c @@ -0,0 +1,216 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio16 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio9 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_OUTPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_LOW, + .gpio45 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/apple/macmini5_1/hda_verb.c b/src/mainboard/apple/macmini5_1/hda_verb.c new file mode 100644 index 0000000..e622098 --- /dev/null +++ b/src/mainboard/apple/macmini5_1/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10134206, /* Codec Vendor / Device ID: Cirrus */ + 0x106b2100, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x106b2100), + AZALIA_PIN_CFG(0, 0x09, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0a, 0x002b4040), + AZALIA_PIN_CFG(0, 0x0b, 0x90100130), + AZALIA_PIN_CFG(0, 0x0c, 0x008b3010), + AZALIA_PIN_CFG(0, 0x0d, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0e, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0f, 0x00cbe020), + AZALIA_PIN_CFG(0, 0x10, 0x004be050), + AZALIA_PIN_CFG(0, 0x12, 0x400000f0), + AZALIA_PIN_CFG(0, 0x15, 0x400000f0), + + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560010), + AZALIA_PIN_CFG(3, 0x07, 0x18560010), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/apple/macmini5_1/mainboard.c b/src/mainboard/apple/macmini5_1/mainboard.c new file mode 100644 index 0000000..e90d85e --- /dev/null +++ b/src/mainboard/apple/macmini5_1/mainboard.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler( + GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, + 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +};
Evgeny Zinoviev has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49074 )
Change subject: Apple Mac Mini (mid 2011) ......................................................................
Patch Set 1:
(10 comments)
https://review.coreboot.org/c/coreboot/+/49074/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/49074/1//COMMIT_MSG@7 PS1, Line 7: Apple Mac Mini (mid 2011) Rewrite like this: mb/apple: Add Mac Mini 5,1 support
Also add a board number, it looks like 820-????.
https://review.coreboot.org/c/coreboot/+/49074/1//COMMIT_MSG@9 PS1, Line 9: tested Please add a list of what's been tested, what works and what doesn't.
Please also add at least a short description of the flashing process, ideally add a page to the documentation.
https://review.coreboot.org/c/coreboot/+/49074/1//COMMIT_MSG@11 PS1, Line 11: Mac Mini Please use a real name here, patches without a real name cannot be merged.
https://review.coreboot.org/c/coreboot/+/49074/1/src/mainboard/apple/macmini... File src/mainboard/apple/macmini5_1/Kconfig:
https://review.coreboot.org/c/coreboot/+/49074/1/src/mainboard/apple/macmini... PS1, Line 14: # select HAVE_CMOS_DEFAULT : # select HAVE_OPTION_TABLE Should be removed
https://review.coreboot.org/c/coreboot/+/49074/1/src/mainboard/apple/macmini... File src/mainboard/apple/macmini5_1/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49074/1/src/mainboard/apple/macmini... PS1, Line 29: ?? ?
https://review.coreboot.org/c/coreboot/+/49074/1/src/mainboard/apple/macmini... PS1, Line 33: register "docking_supported" = "0" this is zero, can be dropped
https://review.coreboot.org/c/coreboot/+/49074/1/src/mainboard/apple/macmini... PS1, Line 38: register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" can be dropped
https://review.coreboot.org/c/coreboot/+/49074/1/src/mainboard/apple/macmini... PS1, Line 52: device pci 1a.7 on end What's this?
https://review.coreboot.org/c/coreboot/+/49074/1/src/mainboard/apple/macmini... PS1, Line 52: device pci 1a.7 on end What's this?
https://review.coreboot.org/c/coreboot/+/49074/1/src/mainboard/apple/macmini... File src/mainboard/apple/macmini5_1/early_init.c:
https://review.coreboot.org/c/coreboot/+/49074/1/src/mainboard/apple/macmini... PS1, Line 10: { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, Looks like these are default autoported values? Please fill with correct values if possible. Do you have the schematics for this macmini?
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49074 )
Change subject: Apple Mac Mini (mid 2011) ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/49074/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/49074/1//COMMIT_MSG@11 PS1, Line 11: Mac Mini
Please use a real name here, patches without a real name cannot be merged.
Do you know, where this is documented? For me, pseudonyms are good enough, as we have no way to check it anyway.
Evgeny Zinoviev has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49074 )
Change subject: Apple Mac Mini (mid 2011) ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/49074/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/49074/1//COMMIT_MSG@11 PS1, Line 11: Mac Mini
Do you know, where this is documented? For me, pseudonyms are good enough, as we have no way to chec […]
I agree, but at least something that looks like a name ;)
It was documented in old development guidelines: https://www.coreboot.org/Development_Guidelines#Sign-off_Procedure
Can't find it in the new docs though.
Attention is currently required from: Mac Mini, Evgeny Zinoviev. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49074 )
Change subject: Apple Mac Mini (mid 2011) ......................................................................
Patch Set 1:
(11 comments)
File src/mainboard/apple/macmini5_1/Kconfig:
https://review.coreboot.org/c/coreboot/+/49074/comment/030c14fc_4857c5cf PS1, Line 25: config VGA_BIOS_FILE : string : default "pci8086,0126.rom" : : config VGA_BIOS_ID : string : default "8086,0126" Please remove, not all CPUs will use the same IDs
https://review.coreboot.org/c/coreboot/+/49074/comment/c92a3fa2_cf2fe47a PS1, Line 33: config DRAM_RESET_GATE_GPIO : int : default 30 Impossible. GPIO is configured as input. Does S3 suspend/resume work?
File src/mainboard/apple/macmini5_1/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/49074/comment/e2bed419_4f291b15 PS1, Line 2: bool "Macmini5,1" I would also add the mainboard model between parentheses: `(820-3017-A)`
File src/mainboard/apple/macmini5_1/acpi_tables.c:
https://review.coreboot.org/c/coreboot/+/49074/comment/23495ca5_f9565ecf PS1, Line 6: void acpi_create_gnvs(struct global_nvs *gnvs) : { : /* Temperature at which OS will shutdown */ : gnvs->tcrt = 100; : /* Temperature at which OS will throttle CPU */ : gnvs->tpsv = 90; : } Isn't used anywhere
File src/mainboard/apple/macmini5_1/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49074/comment/70e283d0_aeb5a612 PS1, Line 15: 0x8086 0x7270 Replace with `0x106b 0x0e6` and drop all other subsystem ID entries
https://review.coreboot.org/c/coreboot/+/49074/comment/161bd3d3_2a8033ba PS1, Line 29: ??
?
Interesting... This device shouldn't appear. Keeping it off should be fine.
https://review.coreboot.org/c/coreboot/+/49074/comment/fc482ceb_d92678b4 PS1, Line 52: device pci 1a.7 on end
What's this?
It could only appear if Apple firmware didn't enable the RMH (Rate-Matching Hub), if that's even possible on bd82x6x. coreboot always enables the RMH, so this can be dropped.
https://review.coreboot.org/c/coreboot/+/49074/comment/786e8761_a6928e4d PS1, Line 66: device pci 1d.7 on end Drop this too
File src/mainboard/apple/macmini5_1/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/49074/comment/395d796a_a82c9a86 PS1, Line 3: #define BRIGHTNESS_UP _SB.PCI0.GFX0.INCB : #define BRIGHTNESS_DOWN _SB.PCI0.GFX0.DECB No brightness to control
https://review.coreboot.org/c/coreboot/+/49074/comment/be8f61c4_2a1225ee PS1, Line 27: #include <drivers/intel/gma/acpi/default_brightness_levels.asl> No brightness to control.
File src/mainboard/apple/macmini5_1/early_init.c:
https://review.coreboot.org/c/coreboot/+/49074/comment/b3c02451_cdfea1c3 PS1, Line 28: pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); : pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070); These register writes can be dropped (the function can be dropped too)
Attention is currently required from: Mac Mini, Evgeny Zinoviev. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49074 )
Change subject: Apple Mac Mini (mid 2011) ......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/apple/macmini5_1/early_init.c:
https://review.coreboot.org/c/coreboot/+/49074/comment/4962202d_227324f8 PS1, Line 10: { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 },
Looks like these are default autoported values? Please fill with correct values if possible. […]
I couldn't find them.
Attention is currently required from: Angel Pons, Mac Mini. Evgeny Zinoviev has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49074 )
Change subject: Apple Mac Mini (mid 2011) ......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/apple/macmini5_1/early_init.c:
https://review.coreboot.org/c/coreboot/+/49074/comment/7d72bacd_a77e88b5 PS1, Line 10: { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 },
I couldn't find them.
Yeah, swiftgeek told me they're not available in public and nobody have them.
I didn't try it but I think it should be possible to get the values by dumping corresponding registers? Maybe inteltool even dumps them.
Attention is currently required from: Mac Mini, Evgeny Zinoviev. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49074 )
Change subject: Apple Mac Mini (mid 2011) ......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/apple/macmini5_1/early_init.c:
https://review.coreboot.org/c/coreboot/+/49074/comment/82b2946b_245a2af7 PS1, Line 10: { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 }, : { 1, 0, -1 },
Yeah, swiftgeek told me they're not available in public and nobody have them. […]
IIRC autoport already dumps the register values. It may be that Apple doesn't use the PCH's OC pins. You can also check the mode of the corresponding PCH GPIOs: if they are used as GPIOs, they are not used as OC pins.
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/49074?usp=email )
Change subject: Apple Mac Mini (mid 2011) ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
-
Angel Pons (Code Review) -
Evgeny Zinoviev (Code Review)
-
Mac Mini (Code Review)
-
Martin L Roth (Code Review)
-
Paul Menzel (Code Review)