Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45827 )
Change subject: soc/intel/braswell: Increase dcache size ......................................................................
soc/intel/braswell: Increase dcache size
Need to increase the DRAM cache size for braswell as the was getting the compilation error "Cache as RAM area is too full" when moving the mrc_cache writeback to romstage. We need to increase this first before landing the CL moving mrc_cache writeback to romstage.
BUG=b:150502246 BRANCH=None TEST=Able to successfully compile braswell boards
Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c Signed-off-by: Shelley Chen shchen@google.com --- M src/soc/intel/braswell/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/45827/1
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 5c9988c..077b5a1 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -96,7 +96,7 @@
config DCACHE_RAM_SIZE hex - default 0x4000 + default 0x5000 help The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45827 )
Change subject: soc/intel/braswell: Increase dcache size ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45827/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45827/1//COMMIT_MSG@9 PS1, Line 9: the it?
https://review.coreboot.org/c/coreboot/+/45827/1/src/soc/intel/braswell/Kcon... File src/soc/intel/braswell/Kconfig:
https://review.coreboot.org/c/coreboot/+/45827/1/src/soc/intel/braswell/Kcon... PS1, Line 103: must add up to a power of 2 Given this comment, I believe you will have to bump it up to 0x8000.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45827 )
Change subject: soc/intel/braswell: Increase dcache size ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45827/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45827/1//COMMIT_MSG@9 PS1, Line 9: Need to increase the DRAM cache size for braswell as the was getting : the compilation error "Cache as RAM area is too full" when moving the : mrc_cache writeback to romstage.
Increase the DRAM cache size for Braswell to address the compilation error
Cache as RAM area too fullwhen moving the mrc_cache writeback to romstage.
Hello build bot (Jenkins), Furquan Shaikh, Duncan Laurie, Julius Werner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45827
to look at the new patch set (#2).
Change subject: soc/intel/braswell: Increase dcache size ......................................................................
soc/intel/braswell: Increase dcache size
Increase the DRAM cache size for Braswell to address the compilation error
Cache as RAM area too full
when moving the mrc_cache writeback to romstage. We need to increase this first before landing the CL moving mrc_cache writeback to romstage.
BUG=b:150502246 BRANCH=None TEST=Able to successfully compile braswell boards
Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c Signed-off-by: Shelley Chen shchen@google.com --- M src/soc/intel/braswell/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/45827/2
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45827 )
Change subject: soc/intel/braswell: Increase dcache size ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45827/1/src/soc/intel/braswell/Kcon... File src/soc/intel/braswell/Kconfig:
https://review.coreboot.org/c/coreboot/+/45827/1/src/soc/intel/braswell/Kcon... PS1, Line 103: must add up to a power of 2
Given this comment, I believe you will have to bump it up to 0x8000.
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45827 )
Change subject: soc/intel/braswell: Increase dcache size ......................................................................
Patch Set 2: Code-Review+2
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45827 )
Change subject: soc/intel/braswell: Increase dcache size ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45827/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45827/1//COMMIT_MSG@9 PS1, Line 9: the
it?
Done
https://review.coreboot.org/c/coreboot/+/45827/1//COMMIT_MSG@9 PS1, Line 9: Need to increase the DRAM cache size for braswell as the was getting : the compilation error "Cache as RAM area is too full" when moving the : mrc_cache writeback to romstage.
Increase the DRAM cache size for Braswell to address the […]
Done
Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45827 )
Change subject: soc/intel/braswell: Increase dcache size ......................................................................
soc/intel/braswell: Increase dcache size
Increase the DRAM cache size for Braswell to address the compilation error
Cache as RAM area too full
when moving the mrc_cache writeback to romstage. We need to increase this first before landing the CL moving mrc_cache writeback to romstage.
BUG=b:150502246 BRANCH=None TEST=Able to successfully compile braswell boards
Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c Signed-off-by: Shelley Chen shchen@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45827 Reviewed-by: Furquan Shaikh furquan@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/braswell/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index ae4fc21..4eb810e 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -93,7 +93,7 @@
config DCACHE_RAM_SIZE hex - default 0x4000 + default 0x8000 help The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45827 )
Change subject: soc/intel/braswell: Increase dcache size ......................................................................
Patch Set 4:
Automatic boot test returned (PASS/FAIL/TOTAL): 5/1/6 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/21963 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/21962 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : FAIL : https://lava.9esec.io/r/21961 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/21960 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/21958 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/21957
Please note: This test is under development and might not be accurate at all!
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45827?usp=email )
Change subject: soc/intel/braswell: Increase dcache size ......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4: For the record, this seems to have caused a regression: CB:82256
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9elements QA (Code Review) -
Angel Pons (Code Review)
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Furquan Shaikh (Code Review)
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Paul Menzel (Code Review)
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Shelley Chen (Code Review)