[coreboot-gerrit] Change in coreboot[master]: soc/intel/braswell: Increase dcache size

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45827 )

Change subject: soc/intel/braswell: Increase dcache size
......................................................................


Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45827/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/45827/1//COMMIT_MSG@9 
PS1, Line 9: Need to increase the DRAM cache size for braswell as the was getting
           : the compilation error "Cache as RAM area is too full" when moving the
           : mrc_cache writeback to romstage.
> Increase the DRAM cache size for Braswell to address the
> compilation error
>
> Cache as RAM area too full
>
> when moving the mrc_cache writeback to romstage.