Shelley Chen uploaded patch set #2 to this change.

View Change

soc/intel/braswell: Increase dcache size

Increase the DRAM cache size for Braswell to address the
compilation error

    Cache as RAM area too full

when moving the mrc_cache writeback to romstage.  We need to increase
this first before landing the CL moving mrc_cache writeback to
romstage.

BUG=b:150502246
BRANCH=None
TEST=Able to successfully compile braswell boards

Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c
Signed-off-by: Shelley Chen <shchen@google.com>
---
M src/soc/intel/braswell/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/45827/2

To view, visit change 45827. To unsubscribe, or for help writing mail filters, visit settings.