Shelley Chen uploaded patch set #2 to this change.

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soc/intel/braswell: Increase dcache size

Increase the DRAM cache size for Braswell to address the
compilation error

Cache as RAM area too full

when moving the mrc_cache writeback to romstage. We need to increase
this first before landing the CL moving mrc_cache writeback to

TEST=Able to successfully compile braswell boards

Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c
Signed-off-by: Shelley Chen <>
M src/soc/intel/braswell/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh:// refs/changes/27/45827/2

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c
Gerrit-Change-Number: 45827
Gerrit-PatchSet: 2
Gerrit-Owner: Shelley Chen <>
Gerrit-Reviewer: Duncan Laurie <>
Gerrit-Reviewer: Furquan Shaikh <>
Gerrit-Reviewer: Julius Werner <>
Gerrit-Reviewer: Patrick Rudolph <>
Gerrit-Reviewer: build bot (Jenkins) <>
Gerrit-CC: Paul Menzel <>
Gerrit-MessageType: newpatchset