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[XS] Change in coreboot[main]: vc/amd/opensil/genoa_poc/mpio: simplify per_device_config arguments
by Felix Held (Code Review) 18 Mar '24

18 Mar '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81341?usp=email ) Change subject: vc/amd/opensil/genoa_poc/mpio: simplify per_device_config arguments ...................................................................... vc/amd/opensil/genoa_poc/mpio: simplify per_device_config arguments Since we're already passing a pointer to the corresponding device to per_device_config, we don't need to pass the chip_info as separate parameter. Before moving the PCIe port function device below the MPIO chip, the chip_info struct was from a different device, so that change allows this simplification. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I0466f7ad2f5c9874d45712fa9f89b978bd2a09bc --- M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/81341/1 diff --git a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c index 47bfdf1..d279555 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c +++ b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c @@ -125,12 +125,12 @@ mpio_data->EarlyBmcLinkDie = 0; } -static void per_device_config(MPIOCLASS_INPUT_BLK *mpio_data, struct device *dev, - struct vendorcode_amd_opensil_genoa_poc_mpio_config *const config) +static void per_device_config(MPIOCLASS_INPUT_BLK *mpio_data, struct device *dev) { static uint32_t slot_num; const uint32_t domain = dev->upstream->dev->path.domain.domain; const uint32_t devfn = dev->path.pci.devfn; + const struct vendorcode_amd_opensil_genoa_poc_mpio_config *const config = dev->chip_info; printk(BIOS_DEBUG, "Setting MPIO port for domain 0x%x, PCI %d:%d\n", domain, PCI_SLOT(devfn), PCI_FUNC(devfn)); @@ -198,5 +198,5 @@ for (struct device *dev = &dev_root; dev; dev = dev->next) if (dev->chip_ops == &vendorcode_amd_opensil_genoa_poc_mpio_ops && dev->chip_info != dev->upstream->dev->chip_info) - per_device_config(mpio_data, dev, dev->chip_info); + per_device_config(mpio_data, dev); } -- To view, visit https://review.coreboot.org/c/coreboot/+/81341?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0466f7ad2f5c9874d45712fa9f89b978bd2a09bc Gerrit-Change-Number: 81341 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: vc/amd/opensil/genoa_poc/mpio: move PCIe port function below mpio chip
by Felix Held (Code Review) 18 Mar '24

18 Mar '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81340?usp=email ) Change subject: vc/amd/opensil/genoa_poc/mpio: move PCIe port function below mpio chip ...................................................................... vc/amd/opensil/genoa_poc/mpio: move PCIe port function below mpio chip Move the gpp_bridge_* device functions that are bridges to the external PCIe ports below the corresponding mpio chip. This avoids the need for dummy devices and does things in a slightly more coreboot-native way. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7e39bf68d30d7d00b16f943953e8207d6fe9ef41 --- M src/mainboard/amd/onyx_poc/devicetree.cb M src/soc/amd/genoa_poc/chipset.cb M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c 3 files changed, 328 insertions(+), 192 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/81340/1 diff --git a/src/mainboard/amd/onyx_poc/devicetree.cb b/src/mainboard/amd/onyx_poc/devicetree.cb index 9cdbe05..059c26f 100644 --- a/src/mainboard/amd/onyx_poc/devicetree.cb +++ b/src/mainboard/amd/onyx_poc/devicetree.cb @@ -55,36 +55,30 @@ device domain 0 on device ref iommu_0 on end device ref rcec_0 on end - device ref gpp_bridge_0_0_a on - chip vendorcode/amd/opensil/genoa_poc/mpio # P2 - register "type" = "ENGINE_PCIE" - register "start_lane" = "48" - register "end_lane" = "63" - register "gpio_group" = "1" - register "aspm" = "L1" - device generic 0 on end # dummy for configuring mpio - end + chip vendorcode/amd/opensil/genoa_poc/mpio # P2 + register "type" = "ENGINE_PCIE" + register "start_lane" = "48" + register "end_lane" = "63" + register "gpio_group" = "1" + register "aspm" = "L1" + device ref gpp_bridge_0_0_a on end end - device ref gpp_bridge_0_0_b on - chip vendorcode/amd/opensil/genoa_poc/mpio # G2 - register "type" = "ENGINE_PCIE" - register "start_lane" = "112" - register "end_lane" = "127" - register "gpio_group" = "1" - register "aspm" = "L1" - register "hotplug" = "ServerExpress" - device generic 0 on end - end + chip vendorcode/amd/opensil/genoa_poc/mpio # G2 + register "type" = "ENGINE_PCIE" + register "start_lane" = "112" + register "end_lane" = "127" + register "gpio_group" = "1" + register "aspm" = "L1" + register "hotplug" = "ServerExpress" + device ref gpp_bridge_0_0_b on end end - device ref gpp_bridge_0_0_c on - chip vendorcode/amd/opensil/genoa_poc/mpio - register "type" = "ENGINE_PCIE" - register "start_lane" = "128" - register "end_lane" = "131" - register "gpio_group" = "1" - register "aspm" = "L1" - device generic 0 on end - end + chip vendorcode/amd/opensil/genoa_poc/mpio + register "type" = "ENGINE_PCIE" + register "start_lane" = "128" + register "end_lane" = "131" + register "gpio_group" = "1" + register "aspm" = "L1" + device ref gpp_bridge_0_0_c on end end device ref gpp_bridge_0_a on device ref xhci_0 on end @@ -99,51 +93,43 @@ device domain 1 on device ref iommu_1 on end device ref rcec_1 on end - device ref gpp_bridge_1_0_a on - chip vendorcode/amd/opensil/genoa_poc/mpio # P3 - register "type" = "ENGINE_PCIE" - register "start_lane" = "16" - register "end_lane" = "31" - register "gpio_group" = "1" - register "aspm" = "L1" - device generic 0 on end - end + chip vendorcode/amd/opensil/genoa_poc/mpio # P3 + register "type" = "ENGINE_PCIE" + register "start_lane" = "16" + register "end_lane" = "31" + register "gpio_group" = "1" + register "aspm" = "L1" + device ref gpp_bridge_1_0_a on end end - device ref gpp_bridge_1_0_b on - chip vendorcode/amd/opensil/genoa_poc/mpio # G3 - register "type" = "ENGINE_PCIE" - register "start_lane" = "80" - register "end_lane" = "95" - register "gpio_group" = "1" - register "aspm" = "L1" - device generic 0 on end - end + chip vendorcode/amd/opensil/genoa_poc/mpio # G3 + register "type" = "ENGINE_PCIE" + register "start_lane" = "80" + register "end_lane" = "95" + register "gpio_group" = "1" + register "aspm" = "L1" + device ref gpp_bridge_1_0_b on end end end device domain 2 on device ref iommu_2 on end device ref rcec_2 on end - device ref gpp_bridge_2_0_a on - chip vendorcode/amd/opensil/genoa_poc/mpio # P1 - register "type" = "ENGINE_PCIE" - register "start_lane" = "32" - register "end_lane" = "47" - register "gpio_group" = "1" - register "aspm" = "L1" - register "hotplug" = "ServerExpress" - device generic 0 on end - end + chip vendorcode/amd/opensil/genoa_poc/mpio # P1 + register "type" = "ENGINE_PCIE" + register "start_lane" = "32" + register "end_lane" = "47" + register "gpio_group" = "1" + register "aspm" = "L1" + register "hotplug" = "ServerExpress" + device ref gpp_bridge_2_0_a on end end - device ref gpp_bridge_2_0_b on - chip vendorcode/amd/opensil/genoa_poc/mpio # G1 - register "type" = "ENGINE_PCIE" - register "start_lane" = "64" - register "end_lane" = "79" - register "gpio_group" = "1" - register "aspm" = "L1" - device generic 0 on end - end + chip vendorcode/amd/opensil/genoa_poc/mpio # G1 + register "type" = "ENGINE_PCIE" + register "start_lane" = "64" + register "end_lane" = "79" + register "gpio_group" = "1" + register "aspm" = "L1" + device ref gpp_bridge_2_0_b on end end end @@ -151,56 +137,46 @@ device domain 3 on device ref iommu_3 on end device ref rcec_3 on end - device ref gpp_bridge_3_0_a on - chip vendorcode/amd/opensil/genoa_poc/mpio # P0 - register "type" = "ENGINE_PCIE" - register "start_lane" = "0" - register "end_lane" = "15" - register "gpio_group" = "1" - register "aspm" = "L1" - device generic 0 on end - end + chip vendorcode/amd/opensil/genoa_poc/mpio # P0 + register "type" = "ENGINE_PCIE" + register "start_lane" = "0" + register "end_lane" = "15" + register "gpio_group" = "1" + register "aspm" = "L1" + device ref gpp_bridge_3_0_a on end end - device ref gpp_bridge_3_0_b on - chip vendorcode/amd/opensil/genoa_poc/mpio # G0 - register "type" = "ENGINE_PCIE" - register "start_lane" = "96" - register "end_lane" = "111" - register "gpio_group" = "1" - register "aspm" = "L1" - device generic 0 on end - end + chip vendorcode/amd/opensil/genoa_poc/mpio # G0 + register "type" = "ENGINE_PCIE" + register "start_lane" = "96" + register "end_lane" = "111" + register "gpio_group" = "1" + register "aspm" = "L1" + device ref gpp_bridge_3_0_b on end end - device ref gpp_bridge_3_0_c on # WAFL - chip vendorcode/amd/opensil/genoa_poc/mpio - register "type" = "ENGINE_PCIE" - register "start_lane" = "132" - register "end_lane" = "133" - register "gpio_group" = "1" - register "aspm" = "L1" - device generic 0 on end - end + chip vendorcode/amd/opensil/genoa_poc/mpio + register "type" = "ENGINE_PCIE" + register "start_lane" = "132" + register "end_lane" = "133" + register "gpio_group" = "1" + register "aspm" = "L1" + device ref gpp_bridge_3_0_c on end # WAFL end - device ref gpp_bridge_3_1_c on # BMC - chip vendorcode/amd/opensil/genoa_poc/mpio - register "type" = "ENGINE_PCIE" - register "start_lane" = "134" - register "end_lane" = "134" - register "gpio_group" = "1" - register "aspm" = "L1" - register "bmc" = "1" - device generic 0 on end - end + chip vendorcode/amd/opensil/genoa_poc/mpio + register "type" = "ENGINE_PCIE" + register "start_lane" = "134" + register "end_lane" = "134" + register "gpio_group" = "1" + register "aspm" = "L1" + register "bmc" = "1" + device ref gpp_bridge_3_1_c on end # BMC end - device ref gpp_bridge_3_2_c on # BMC - chip vendorcode/amd/opensil/genoa_poc/mpio - register "type" = "ENGINE_PCIE" - register "start_lane" = "135" - register "end_lane" = "135" - register "gpio_group" = "1" - register "aspm" = "L1" - device generic 0 on end - end + chip vendorcode/amd/opensil/genoa_poc/mpio + register "type" = "ENGINE_PCIE" + register "start_lane" = "135" + register "end_lane" = "135" + register "gpio_group" = "1" + register "aspm" = "L1" + device ref gpp_bridge_3_2_c on end # BMC end device ref gpp_bridge_3_a on device ref xhci_3 on end diff --git a/src/soc/amd/genoa_poc/chipset.cb b/src/soc/amd/genoa_poc/chipset.cb index dccffde..92dcb5d 100644 --- a/src/soc/amd/genoa_poc/chipset.cb +++ b/src/soc/amd/genoa_poc/chipset.cb @@ -16,36 +16,80 @@ device pci 00.3 alias rcec_0 off end device pci 01.0 on end # Dummy device function, do not disable - device pci 01.1 alias gpp_bridge_0_0_a off end - device pci 01.2 alias gpp_bridge_0_1_a off end - device pci 01.3 alias gpp_bridge_0_2_a off end - device pci 01.4 alias gpp_bridge_0_3_a off end - device pci 01.5 alias gpp_bridge_0_4_a off end - device pci 01.6 alias gpp_bridge_0_5_a off end - device pci 01.7 alias gpp_bridge_0_6_a off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.1 alias gpp_bridge_0_0_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.2 alias gpp_bridge_0_1_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.3 alias gpp_bridge_0_2_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.4 alias gpp_bridge_0_3_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.5 alias gpp_bridge_0_4_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.6 alias gpp_bridge_0_5_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.7 alias gpp_bridge_0_6_a off end + end device pci 02.0 on end # Dummy device function, do not disable - device pci 02.1 alias gpp_bridge_0_7_a off end - device pci 02.2 alias gpp_bridge_0_8_a off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 02.1 alias gpp_bridge_0_7_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 02.2 alias gpp_bridge_0_8_a off end + end device pci 03.0 on end # Dummy device function, do not disable - device pci 03.1 alias gpp_bridge_0_0_b off end - device pci 03.2 alias gpp_bridge_0_1_b off end - device pci 03.3 alias gpp_bridge_0_2_b off end - device pci 03.4 alias gpp_bridge_0_3_b off end - device pci 03.5 alias gpp_bridge_0_4_b off end - device pci 03.6 alias gpp_bridge_0_5_b off end - device pci 03.7 alias gpp_bridge_0_6_b off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.1 alias gpp_bridge_0_0_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.2 alias gpp_bridge_0_1_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.3 alias gpp_bridge_0_2_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.4 alias gpp_bridge_0_3_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.5 alias gpp_bridge_0_4_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.6 alias gpp_bridge_0_5_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.7 alias gpp_bridge_0_6_b off end + end device pci 04.0 on end # Dummy device function, do not disable - device pci 04.1 alias gpp_bridge_0_7_b off end - device pci 04.2 alias gpp_bridge_0_8_b off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 04.1 alias gpp_bridge_0_7_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 04.2 alias gpp_bridge_0_8_b off end + end device pci 05.0 on end # Dummy device function, do not disable - device pci 05.1 alias gpp_bridge_0_0_c off end - device pci 05.2 alias gpp_bridge_0_1_c off end - device pci 05.3 alias gpp_bridge_0_2_c off end - device pci 05.4 alias gpp_bridge_0_3_c off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 05.1 alias gpp_bridge_0_0_c off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 05.2 alias gpp_bridge_0_1_c off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 05.3 alias gpp_bridge_0_2_c off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 05.4 alias gpp_bridge_0_3_c off end + end device pci 07.0 on end # Dummy device function, do not disable device pci 07.1 alias gpp_bridge_0_a off # Internal GPP Bridge 0 to Bus B0 @@ -84,30 +128,66 @@ device pci 00.3 alias rcec_1 off end device pci 01.0 on end # Dummy device function, do not disable - device pci 01.1 alias gpp_bridge_1_0_a off end - device pci 01.2 alias gpp_bridge_1_1_a off end - device pci 01.3 alias gpp_bridge_1_2_a off end - device pci 01.4 alias gpp_bridge_1_3_a off end - device pci 01.5 alias gpp_bridge_1_4_a off end - device pci 01.6 alias gpp_bridge_1_5_a off end - device pci 01.7 alias gpp_bridge_1_6_a off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.1 alias gpp_bridge_1_0_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.2 alias gpp_bridge_1_1_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.3 alias gpp_bridge_1_2_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.4 alias gpp_bridge_1_3_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.5 alias gpp_bridge_1_4_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.6 alias gpp_bridge_1_5_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.7 alias gpp_bridge_1_6_a off end + end device pci 02.0 on end # Dummy device function, do not disable - device pci 02.1 alias gpp_bridge_1_7_a off end - device pci 02.2 alias gpp_bridge_1_8_a off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 02.1 alias gpp_bridge_1_7_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 02.2 alias gpp_bridge_1_8_a off end + end device pci 03.0 on end # Dummy device function, do not disable - device pci 03.1 alias gpp_bridge_1_0_b off end - device pci 03.2 alias gpp_bridge_1_1_b off end - device pci 03.3 alias gpp_bridge_1_2_b off end - device pci 03.4 alias gpp_bridge_1_3_b off end - device pci 03.5 alias gpp_bridge_1_4_b off end - device pci 03.6 alias gpp_bridge_1_5_b off end - device pci 03.7 alias gpp_bridge_1_6_b off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.1 alias gpp_bridge_1_0_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.2 alias gpp_bridge_1_1_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.3 alias gpp_bridge_1_2_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.4 alias gpp_bridge_1_3_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.5 alias gpp_bridge_1_4_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.6 alias gpp_bridge_1_5_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.7 alias gpp_bridge_1_6_b off end + end device pci 04.0 on end # Dummy device function, do not disable - device pci 04.1 alias gpp_bridge_1_7_b off end - device pci 04.2 alias gpp_bridge_1_8_b off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 04.1 alias gpp_bridge_1_7_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 04.2 alias gpp_bridge_1_8_b off end + end device pci 05.0 on end # Dummy device function, do not disable @@ -127,30 +207,66 @@ device pci 00.3 alias rcec_2 off end device pci 01.0 on end # Dummy device function, do not disable - device pci 01.1 alias gpp_bridge_2_0_a off end - device pci 01.2 alias gpp_bridge_2_1_a off end - device pci 01.3 alias gpp_bridge_2_2_a off end - device pci 01.4 alias gpp_bridge_2_3_a off end - device pci 01.5 alias gpp_bridge_2_4_a off end - device pci 01.6 alias gpp_bridge_2_5_a off end - device pci 01.7 alias gpp_bridge_2_6_a off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.1 alias gpp_bridge_2_0_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.2 alias gpp_bridge_2_1_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.3 alias gpp_bridge_2_2_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.4 alias gpp_bridge_2_3_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.5 alias gpp_bridge_2_4_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.6 alias gpp_bridge_2_5_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.7 alias gpp_bridge_2_6_a off end + end device pci 02.0 on end # Dummy device function, do not disable - device pci 02.1 alias gpp_bridge_2_7_a off end - device pci 02.2 alias gpp_bridge_2_8_a off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 02.1 alias gpp_bridge_2_7_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 02.2 alias gpp_bridge_2_8_a off end + end device pci 03.0 on end # Dummy device function, do not disable - device pci 03.1 alias gpp_bridge_2_0_b off end - device pci 03.2 alias gpp_bridge_2_1_b off end - device pci 03.3 alias gpp_bridge_2_2_b off end - device pci 03.4 alias gpp_bridge_2_3_b off end - device pci 03.5 alias gpp_bridge_2_4_b off end - device pci 03.6 alias gpp_bridge_2_5_b off end - device pci 03.7 alias gpp_bridge_2_6_b off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.1 alias gpp_bridge_2_0_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.2 alias gpp_bridge_2_1_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.3 alias gpp_bridge_2_2_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.4 alias gpp_bridge_2_3_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.5 alias gpp_bridge_2_4_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.6 alias gpp_bridge_2_5_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.7 alias gpp_bridge_2_6_b off end + end device pci 04.0 on end # Dummy device function, do not disable - device pci 04.1 alias gpp_bridge_2_7_b off end - device pci 04.2 alias gpp_bridge_2_8_b off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 04.1 alias gpp_bridge_2_7_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 04.2 alias gpp_bridge_2_8_b off end + end device pci 05.0 on end # Dummy device function, do not disable @@ -170,36 +286,80 @@ device pci 00.3 alias rcec_3 off end device pci 01.0 on end # Dummy device function, do not disable - device pci 01.1 alias gpp_bridge_3_0_a off end - device pci 01.2 alias gpp_bridge_3_1_a off end - device pci 01.3 alias gpp_bridge_3_2_a off end - device pci 01.4 alias gpp_bridge_3_3_a off end - device pci 01.5 alias gpp_bridge_3_4_a off end - device pci 01.6 alias gpp_bridge_3_5_a off end - device pci 01.7 alias gpp_bridge_3_6_a off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.1 alias gpp_bridge_3_0_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.2 alias gpp_bridge_3_1_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.3 alias gpp_bridge_3_2_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.4 alias gpp_bridge_3_3_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.5 alias gpp_bridge_3_4_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.6 alias gpp_bridge_3_5_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.7 alias gpp_bridge_3_6_a off end + end device pci 02.0 on end # Dummy device function, do not disable - device pci 02.1 alias gpp_bridge_3_7_a off end - device pci 02.2 alias gpp_bridge_3_8_a off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 02.1 alias gpp_bridge_3_7_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 02.2 alias gpp_bridge_3_8_a off end + end device pci 03.0 on end # Dummy device function, do not disable - device pci 03.1 alias gpp_bridge_3_0_b off end - device pci 03.2 alias gpp_bridge_3_1_b off end - device pci 03.3 alias gpp_bridge_3_2_b off end - device pci 03.4 alias gpp_bridge_3_3_b off end - device pci 03.5 alias gpp_bridge_3_4_b off end - device pci 03.6 alias gpp_bridge_3_5_b off end - device pci 03.7 alias gpp_bridge_3_6_b off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.1 alias gpp_bridge_3_0_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.2 alias gpp_bridge_3_1_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.3 alias gpp_bridge_3_2_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.4 alias gpp_bridge_3_3_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.5 alias gpp_bridge_3_4_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.6 alias gpp_bridge_3_5_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.7 alias gpp_bridge_3_6_b off end + end device pci 04.0 on end # Dummy device function, do not disable - device pci 04.1 alias gpp_bridge_3_7_b off end - device pci 04.2 alias gpp_bridge_3_8_b off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 04.1 alias gpp_bridge_3_7_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 04.2 alias gpp_bridge_3_8_b off end + end device pci 05.0 on end # Dummy device function, do not disable - device pci 05.1 alias gpp_bridge_3_0_c off end - device pci 05.2 alias gpp_bridge_3_1_c off end - device pci 05.3 alias gpp_bridge_3_2_c off end - device pci 05.4 alias gpp_bridge_3_3_c off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 05.1 alias gpp_bridge_3_0_c off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 05.2 alias gpp_bridge_3_1_c off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 05.3 alias gpp_bridge_3_2_c off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 05.4 alias gpp_bridge_3_3_c off end + end device pci 07.0 on end # Dummy device function, do not disable device pci 07.1 alias gpp_bridge_3_a off diff --git a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c index 5a07767..47bfdf1 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c +++ b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c @@ -198,5 +198,5 @@ for (struct device *dev = &dev_root; dev; dev = dev->next) if (dev->chip_ops == &vendorcode_amd_opensil_genoa_poc_mpio_ops && dev->chip_info != dev->upstream->dev->chip_info) - per_device_config(mpio_data, dev->upstream->dev, dev->chip_info); + per_device_config(mpio_data, dev, dev->chip_info); } -- To view, visit https://review.coreboot.org/c/coreboot/+/81340?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7e39bf68d30d7d00b16f943953e8207d6fe9ef41 Gerrit-Change-Number: 81340 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: vc/amd/opensil/*/mpio: add ENGINE_UNUSED mpio_type enum element
by Felix Held (Code Review) 18 Mar '24

18 Mar '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81339?usp=email ) Change subject: vc/amd/opensil/*/mpio: add ENGINE_UNUSED mpio_type enum element ...................................................................... vc/amd/opensil/*/mpio: add ENGINE_UNUSED mpio_type enum element Add ENGINE_UNUSED as first element to the mpio_type enum. This allows checking if the type was set in the devicetree, since the default will now be ENGINE_UNUSED. If the type is set to ENGINE_UNUSED although the corresponding PCI device function, a warning is printed and the PCI device function is disabled. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I85e2589c021b4f05662369fd551146b6f2fa0ad4 --- M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h M src/vendorcode/amd/opensil/stub/mpio/chip.h 3 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/81339/1 diff --git a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c index 1876da7..5a07767 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c +++ b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c @@ -134,6 +134,14 @@ printk(BIOS_DEBUG, "Setting MPIO port for domain 0x%x, PCI %d:%d\n", domain, PCI_SLOT(devfn), PCI_FUNC(devfn)); + if (config->type == ENGINE_UNUSED) { + if (is_dev_enabled(dev)) { + printk(BIOS_WARNING, "Unused MPIO engine, disabling PCI device.\n"); + dev->enabled = false; + } + return; + } + if (config->bmc) { setup_bmc_lanes(config->start_lane, 0); // TODO support multiple sockets return; diff --git a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h index 3717374..9b8d392 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h +++ b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h @@ -17,6 +17,7 @@ */ enum mpio_type { + ENGINE_UNUSED, ENGINE_PCIE, ENGINE_SATA, }; diff --git a/src/vendorcode/amd/opensil/stub/mpio/chip.h b/src/vendorcode/amd/opensil/stub/mpio/chip.h index 53d22a0..8b28c47d 100644 --- a/src/vendorcode/amd/opensil/stub/mpio/chip.h +++ b/src/vendorcode/amd/opensil/stub/mpio/chip.h @@ -3,6 +3,7 @@ #include <types.h> enum mpio_engine_type { + ENGINE_UNUSED, ENGINE_PCIE, ENGINE_SATA, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/81339?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I85e2589c021b4f05662369fd551146b6f2fa0ad4 Gerrit-Change-Number: 81339 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: vc/amd/opensil/genoa_poc/mpio: add ENGINE_ prefix to mpio_type values
by Felix Held (Code Review) 18 Mar '24

18 Mar '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81338?usp=email ) Change subject: vc/amd/opensil/genoa_poc/mpio: add ENGINE_ prefix to mpio_type values ...................................................................... vc/amd/opensil/genoa_poc/mpio: add ENGINE_ prefix to mpio_type values Add an ENGINE_ prefix to all elements of the mpio_type enum to have more specific names. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I229a3402c36941ee5347e3704fcf8d8a1bbc78a6 --- M src/mainboard/amd/onyx_poc/devicetree.cb M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h 3 files changed, 16 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/81338/1 diff --git a/src/mainboard/amd/onyx_poc/devicetree.cb b/src/mainboard/amd/onyx_poc/devicetree.cb index 3597847..9cdbe05 100644 --- a/src/mainboard/amd/onyx_poc/devicetree.cb +++ b/src/mainboard/amd/onyx_poc/devicetree.cb @@ -57,7 +57,7 @@ device ref rcec_0 on end device ref gpp_bridge_0_0_a on chip vendorcode/amd/opensil/genoa_poc/mpio # P2 - register "type" = "PCIE" + register "type" = "ENGINE_PCIE" register "start_lane" = "48" register "end_lane" = "63" register "gpio_group" = "1" @@ -67,7 +67,7 @@ end device ref gpp_bridge_0_0_b on chip vendorcode/amd/opensil/genoa_poc/mpio # G2 - register "type" = "PCIE" + register "type" = "ENGINE_PCIE" register "start_lane" = "112" register "end_lane" = "127" register "gpio_group" = "1" @@ -78,7 +78,7 @@ end device ref gpp_bridge_0_0_c on chip vendorcode/amd/opensil/genoa_poc/mpio - register "type" = "PCIE" + register "type" = "ENGINE_PCIE" register "start_lane" = "128" register "end_lane" = "131" register "gpio_group" = "1" @@ -101,7 +101,7 @@ device ref rcec_1 on end device ref gpp_bridge_1_0_a on chip vendorcode/amd/opensil/genoa_poc/mpio # P3 - register "type" = "PCIE" + register "type" = "ENGINE_PCIE" register "start_lane" = "16" register "end_lane" = "31" register "gpio_group" = "1" @@ -111,7 +111,7 @@ end device ref gpp_bridge_1_0_b on chip vendorcode/amd/opensil/genoa_poc/mpio # G3 - register "type" = "PCIE" + register "type" = "ENGINE_PCIE" register "start_lane" = "80" register "end_lane" = "95" register "gpio_group" = "1" @@ -126,7 +126,7 @@ device ref rcec_2 on end device ref gpp_bridge_2_0_a on chip vendorcode/amd/opensil/genoa_poc/mpio # P1 - register "type" = "PCIE" + register "type" = "ENGINE_PCIE" register "start_lane" = "32" register "end_lane" = "47" register "gpio_group" = "1" @@ -137,7 +137,7 @@ end device ref gpp_bridge_2_0_b on chip vendorcode/amd/opensil/genoa_poc/mpio # G1 - register "type" = "PCIE" + register "type" = "ENGINE_PCIE" register "start_lane" = "64" register "end_lane" = "79" register "gpio_group" = "1" @@ -153,7 +153,7 @@ device ref rcec_3 on end device ref gpp_bridge_3_0_a on chip vendorcode/amd/opensil/genoa_poc/mpio # P0 - register "type" = "PCIE" + register "type" = "ENGINE_PCIE" register "start_lane" = "0" register "end_lane" = "15" register "gpio_group" = "1" @@ -163,7 +163,7 @@ end device ref gpp_bridge_3_0_b on chip vendorcode/amd/opensil/genoa_poc/mpio # G0 - register "type" = "PCIE" + register "type" = "ENGINE_PCIE" register "start_lane" = "96" register "end_lane" = "111" register "gpio_group" = "1" @@ -173,7 +173,7 @@ end device ref gpp_bridge_3_0_c on # WAFL chip vendorcode/amd/opensil/genoa_poc/mpio - register "type" = "PCIE" + register "type" = "ENGINE_PCIE" register "start_lane" = "132" register "end_lane" = "133" register "gpio_group" = "1" @@ -183,7 +183,7 @@ end device ref gpp_bridge_3_1_c on # BMC chip vendorcode/amd/opensil/genoa_poc/mpio - register "type" = "PCIE" + register "type" = "ENGINE_PCIE" register "start_lane" = "134" register "end_lane" = "134" register "gpio_group" = "1" @@ -194,7 +194,7 @@ end device ref gpp_bridge_3_2_c on # BMC chip vendorcode/amd/opensil/genoa_poc/mpio - register "type" = "PCIE" + register "type" = "ENGINE_PCIE" register "start_lane" = "135" register "end_lane" = "135" register "gpio_group" = "1" diff --git a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c index 50e96c9..1876da7 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c +++ b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c @@ -141,7 +141,7 @@ static int mpio_port = 0; MPIO_PORT_DESCRIPTOR port = { .Flags = DESCRIPTOR_TERMINATE_LIST }; - if (config->type == PCIE) { + if (config->type == ENGINE_PCIE) { const MPIO_ENGINE_DATA engine_data = MPIO_ENGINE_DATA_INITIALIZER(MpioPcieEngine, config->start_lane, config->end_lane, @@ -160,7 +160,7 @@ config->aspm_l1_2, config->clock_pm); port.Port = port_data; - } else if (config->type == SATA) { + } else if (config->type == ENGINE_SATA) { const MPIO_ENGINE_DATA engine_data = MPIO_ENGINE_DATA_INITIALIZER(MpioSATAEngine, config->start_lane, config->end_lane, diff --git a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h index 64a8b3e..3717374 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h +++ b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h @@ -17,8 +17,8 @@ */ enum mpio_type { - PCIE, - SATA, + ENGINE_PCIE, + ENGINE_SATA, }; /* Sync with PCIE_HOTPLUG_TYPE */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I229a3402c36941ee5347e3704fcf8d8a1bbc78a6 Gerrit-Change-Number: 81338 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: acpi/acpi: mark CTBL coreboot table device as hidden
by Matt DeVillier (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Cliff Huang, CoolStar, Felix Held, Lance Zhao, Matt DeVillier, Tim Wawrzynczak. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81264?usp=email ) Change subject: acpi/acpi: mark CTBL coreboot table device as hidden ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > hmm, so hiding the device would make your driver fail to attach, but not hiding it requires manually […] ultimately, is this just a cosmetic issue of having an unknown device in Windows Device Manager? If there's no functional impact, I'd be inclined to leave it visible rather than making it a compile-time option -- To view, visit https://review.coreboot.org/c/coreboot/+/81264?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifaefeb662da33323460333d9ca9c0e8340720fd1 Gerrit-Change-Number: 81264 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 18 Mar 2024 19:35:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: CoolStar <coolstarorganization(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: Revert "make: add clang-format prepare-commit-msg hook"
by ron minnich (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Martin L Roth, Patrick Georgi, Stefan Reinauer. ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81307?usp=email ) Change subject: Revert "make: add clang-format prepare-commit-msg hook" ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: let's face it, I did a shite job here. -- To view, visit https://review.coreboot.org/c/coreboot/+/81307?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9466cfb9807e1969e3f50ef6b0d26decd3c67203 Gerrit-Change-Number: 81307 Gerrit-PatchSet: 1 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Mar 2024 19:31:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: Revert "make: add clang-format prepare-commit-msg hook"
by ron minnich (Code Review) 18 Mar '24

18 Mar '24

ron minnich has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81307?usp=email ) Change subject: Revert "make: add clang-format prepare-commit-msg hook" ...................................................................... Revert "make: add clang-format prepare-commit-msg hook" This reverts commit ff22b6aca6daba2bf20b3eebd5299d03f906674c. It has many flaws. It's not easily reversed, but, mainly, it can put the clang-formatted-by tag in the file in such a way that pushing won't accept it. Change-Id: I9466cfb9807e1969e3f50ef6b0d26decd3c67203 Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M 3rdparty/intel-microcode M Makefile.mk 2 files changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/81307/1 diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 41af345..ece0d29 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 41af34500598418150aa298bb04e7edacc547897 +Subproject commit ece0d294a29a1375397941a4e6f2f7217910bc89 diff --git a/Makefile.mk b/Makefile.mk index 73fb40b..58a4b50 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -766,9 +766,6 @@ gitconfig: util/gitconfig/gitconfig.sh "$(MAKE)" -install-git-commit-clangfmt: - cp util/scripts/prepare-commit-msg.clang-format .git/hooks/prepare-commit-msg - include util/crossgcc/Makefile.mk .PHONY: tools -- To view, visit https://review.coreboot.org/c/coreboot/+/81307?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9466cfb9807e1969e3f50ef6b0d26decd3c67203 Gerrit-Change-Number: 81307 Gerrit-PatchSet: 1 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: acpi/acpi: mark CTBL coreboot table device as hidden
by Felix Held (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Cliff Huang, CoolStar, Lance Zhao, Matt DeVillier, Matt DeVillier, Tim Wawrzynczak. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81264?usp=email ) Change subject: acpi/acpi: mark CTBL coreboot table device as hidden ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > No. Driver is here: https://github. […] hmm, so hiding the device would make your driver fail to attach, but not hiding it requires manually installing the driver for the warning to disappear. would adding a kconfig option to unhide the device be a good idea so that it can be decided at build time if that device is supposed to show up? can't say that really like any of the 3 solutions though -- To view, visit https://review.coreboot.org/c/coreboot/+/81264?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifaefeb662da33323460333d9ca9c0e8340720fd1 Gerrit-Change-Number: 81264 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Comment-Date: Mon, 18 Mar 2024 19:10:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: CoolStar <coolstarorganization(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/intel/pmc_mux/conn: Copy ACPI _PLD property from USB port to mux
by Emilie Roberts (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Paul Menzel, Won Chung. Emilie Roberts has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81089?usp=email ) Change subject: drivers/intel/pmc_mux/conn: Copy ACPI _PLD property from USB port to mux ...................................................................... Patch Set 7: (1 comment) Patchset: PS5: > I tried out on a leased lab dut and here is what I get. […] How do you know which physical port the something is plugged into without looking at the device in real life? On my mithrax (M123 kernel 5.15) in front of me, I see this identical setup if something is physically plugged into the **left**-hand port. Can you verify if setting the usb mode works? Maybe: `cat /sys/class/typec/port0/usb-role-switch/role`. If it says `none` you have the problem I do. If it says `device`, maybe there is something different with my mithrax device. Verify the other port : `cat /sys/class/typec/port1/usb-role-switch/role`, my hunch is that it will say `device`. In other words, mithrax is enumerating the left-hand port as port**0** because it happens to be first in the ACPI table. But the `physical_location/panel` is saying it should be port**1**. -- To view, visit https://review.coreboot.org/c/coreboot/+/81089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If27042cc995ef188f8a3e31444e994318ff98803 Gerrit-Change-Number: 81089 Gerrit-PatchSet: 7 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Emilie Roberts <hadrosaur(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Benson Leung <bleung(a)google.com> Gerrit-CC: Prashant Malani <pmalani(a)chromium.org> Gerrit-CC: Prashant Malani <pmalani(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Won Chung <wonchung(a)google.com> Gerrit-Comment-Date: Mon, 18 Mar 2024 18:36:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Emilie Roberts <hadrosaur(a)google.com> Comment-In-Reply-To: Won Chung <wonchung(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: WIP: simple, dumb, illegal instruction handling
by ron minnich (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Philipp Hug. Hello Philipp Hug, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81306?usp=email to look at the new patch set (#3). Change subject: WIP: simple, dumb, illegal instruction handling ...................................................................... WIP: simple, dumb, illegal instruction handling This is a very simple example of an illegal instruction handler. coreboot SBI is designed to minimize SBI functionality. This minimization is reflected in the lack of generality in the code. The ill() function switches out on a subset of instrution types, because C compilers tend to use a very limited subset of the possibilities of an instruction. In this case, code will support only two illegal instructions: csrrs x10, time, x0 csrrs x14, time, x0 On modern RISC-V systems, the trap will not even occur. At some point RISC-V community figured out that trapping on reading time was not always the best idea :-) So, in general, on future systems, reads will not trap. This CL can not go in until Hug's menvcfg support goes in. Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> Change-Id: I2d7b610698eca01b19a996bc80b0b08af4aed078 --- M src/arch/riscv/trap_handler.c M src/arch/riscv/virtual_memory.c 2 files changed, 50 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/81306/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81306?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d7b610698eca01b19a996bc80b0b08af4aed078 Gerrit-Change-Number: 81306 Gerrit-PatchSet: 3 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newpatchset

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