coreboot-gerrit March 2024

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[S] Change in coreboot[main]: drivers/intel/pmc_mux/conn: Copy ACPI _PLD property from USB port to mux
by Won Chung (Code Review) 19 Mar '24

19 Mar '24

Attention is currently required from: Paul Menzel, Won Chung. Hello Emilie Roberts, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81089?usp=email to look at the new patch set (#8). Change subject: drivers/intel/pmc_mux/conn: Copy ACPI _PLD property from USB port to mux ...................................................................... drivers/intel/pmc_mux/conn: Copy ACPI _PLD property from USB port to mux Copy ACPI _PLD values from USB ports to corresponding USB muxes so that the kernel can create symlinks between Type C connectors and corresponding USB muxes. This symlink will be used to let userspace be able to modify the USB role without knowing ACPI topology for the device. BUG=b:121287022 b:329657774 TEST=emerge-${BOARD} coreboot then check ACPI table on DUT Change-Id: If27042cc995ef188f8a3e31444e994318ff98803 Signed-off-by: Won Chung <wonchung(a)google.com> Tested-by: Emilie Roberts <hadrosaur(a)google.com> --- M src/drivers/intel/pmc_mux/conn/conn.c 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/81089/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/81089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If27042cc995ef188f8a3e31444e994318ff98803 Gerrit-Change-Number: 81089 Gerrit-PatchSet: 8 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Emilie Roberts <hadrosaur(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Benson Leung <bleung(a)google.com> Gerrit-CC: Prashant Malani <pmalani(a)chromium.org> Gerrit-CC: Prashant Malani <pmalani(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Won Chung <wonchung(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/nissa/var/anraggar: Assign GPP_C0 as TouchScreen enable pin
by Eric Lai (Code Review) 19 Mar '24

19 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Qinghong Zeng, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81265?usp=email ) Change subject: mb/google/nissa/var/anraggar: Assign GPP_C0 as TouchScreen enable pin ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81265?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia06209aa8303be4fc0669c5d6e5d7a06e8e9ab99 Gerrit-Change-Number: 81265 Gerrit-PatchSet: 4 Gerrit-Owner: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 19 Mar 2024 02:17:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/nissa/var/anraggar: Assign GPP_C0 as TouchScreen enable pin
by Weimin Wu (Code Review) 19 Mar '24

19 Mar '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Qinghong Zeng, Subrata Banik. Weimin Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81265?usp=email ) Change subject: mb/google/nissa/var/anraggar: Assign GPP_C0 as TouchScreen enable pin ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81265?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia06209aa8303be4fc0669c5d6e5d7a06e8e9ab99 Gerrit-Change-Number: 81265 Gerrit-PatchSet: 4 Gerrit-Owner: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 19 Mar 2024 02:05:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/nissa/var/anraggar: Assign GPP_C0 as TouchScreen enable pin
by Qinghong Zeng (Code Review) 19 Mar '24

19 Mar '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Qinghong Zeng, Subrata Banik, Weimin Wu. Qinghong Zeng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81265?usp=email ) Change subject: mb/google/nissa/var/anraggar: Assign GPP_C0 as TouchScreen enable pin ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/81265?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia06209aa8303be4fc0669c5d6e5d7a06e8e9ab99 Gerrit-Change-Number: 81265 Gerrit-PatchSet: 4 Gerrit-Owner: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 19 Mar 2024 02:05:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: arch/x86: Fix typo for macro CPUID_FEATURE_HTT
by Jincheng Li (Code Review) 19 Mar '24

19 Mar '24

Attention is currently required from: Jérémy Compostella, Patrick Rudolph, Shuo Liu. Jincheng Li has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81260?usp=email ) Change subject: arch/x86: Fix typo for macro CPUID_FEATURE_HTT ...................................................................... Patch Set 7: (1 comment) File src/arch/x86/include/arch/cpu.h: https://review.coreboot.org/c/coreboot/+/81260/comment/4a83ac12_8ccb0642 : PS7, Line 50: CPUID_FEATURE_PAE > Unused defines CPUID_FEATURE_PAE is used in src/arch/x86/cpu_common.c:59 "if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36))" -- To view, visit https://review.coreboot.org/c/coreboot/+/81260?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9b29233e75483cda6bf7723cf79632f6b04233b0 Gerrit-Change-Number: 81260 Gerrit-PatchSet: 7 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Comment-Date: Tue, 19 Mar 2024 01:59:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/brya: Create yavista variant
by Eric Lai (Code Review) 19 Mar '24

19 Mar '24

Attention is currently required from: Derek Huang, Dinesh Gehlot, Garen Wu, Kapil Porwal, Nick Vaccaro, Rasheed Hsueh. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80342?usp=email ) Change subject: mb/google/brya: Create yavista variant ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80342?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6fa464a4dcd9551a42e8746e64c724b3582dbe02 Gerrit-Change-Number: 80342 Gerrit-PatchSet: 6 Gerrit-Owner: Rasheed Hsueh <hsueh.rasheed(a)inventec.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Garen Wu <wu.garen(a)inventec.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ryan Lin <ryan.lin(a)intel.corp-partner.google.com> Gerrit-CC: Steven Yeh <yeh.stevenct(a)inventec.corp-partner.google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Rasheed Hsueh <hsueh.rasheed(a)inventec.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Garen Wu <wu.garen(a)inventec.corp-partner.google.com> Gerrit-Comment-Date: Tue, 19 Mar 2024 01:35:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: arch/riscv: add constants for Base Extension
by Maximilian Brune (Code Review) 19 Mar '24

19 Mar '24

Attention is currently required from: Arthur Heymans, Philipp Hug, ron minnich. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81286?usp=email ) Change subject: arch/riscv: add constants for Base Extension ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81286?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaad763464678d1921dfefdbee1e39fba2fe5585a Gerrit-Change-Number: 81286 Gerrit-PatchSet: 3 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Tue, 19 Mar 2024 01:12:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: superio/ite: Add special fan vectors, unify it8722f with common
by Joel Linn (Code Review) 19 Mar '24

19 Mar '24

Joel Linn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81310?usp=email ) Change subject: superio/ite: Add special fan vectors, unify it8722f with common ...................................................................... superio/ite: Add special fan vectors, unify it8722f with common A number of ITE SIOs support "special fan control vectors", which effectively allow non-linear fan speed control. This is for example used by the vendor firmware of "HP Pro 3500 Series". Because that board uses the it8779e (identifying itself as it8772f) and porting it also required functionality that is only found in the common code, the it8772f code was unified with the common code except for GPIO handling which currently lacks a sane abstraction in any codebase. The 3VSBSW# signal can now also be disabled again which is necessary to power components down properly in SMM when entering S5. The datasheets of the it8772e(f) and it8728f (for reference) were studied and verified against the common code, adding exceptions where needed. Change-Id: Ic4d9d5460628e444dc20f620179b39c90dbc28c6 Signed-off-by: Joel Linn <jl(a)conductive.de> --- M src/mainboard/acer/g43t-am3/early_init.c M src/mainboard/foxconn/g41s-k/early_init.c M src/mainboard/google/beltino/bootblock.c M src/mainboard/google/beltino/devicetree.cb M src/mainboard/google/beltino/onboard.h M src/mainboard/google/jecht/bootblock.c M src/mainboard/google/jecht/devicetree.cb M src/mainboard/google/jecht/onboard.h M src/mainboard/libretrend/lt1000/bootblock.c M src/mainboard/protectli/vault_cml/bootblock.c M src/mainboard/protectli/vault_kbl/bootblock.c M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb M src/mainboard/samsung/stumpy/early_init.c M src/mainboard/samsung/stumpy/smihandler.c M src/superio/ite/Makefile.mk M src/superio/ite/common/Kconfig M src/superio/ite/common/early_serial.c M src/superio/ite/common/env_ctrl.c M src/superio/ite/common/env_ctrl.h M src/superio/ite/common/env_ctrl_chip.h M src/superio/ite/common/ite.h A src/superio/ite/common/mainboard_impl.h M src/superio/ite/it8728f/Kconfig M src/superio/ite/it8772f/Kconfig M src/superio/ite/it8772f/chip.h M src/superio/ite/it8772f/early_init.c M src/superio/ite/it8772f/it8772f.h M src/superio/ite/it8772f/superio.c 29 files changed, 232 insertions(+), 343 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/81310/1 diff --git a/src/mainboard/acer/g43t-am3/early_init.c b/src/mainboard/acer/g43t-am3/early_init.c index b34ab46..9cdcb6e 100644 --- a/src/mainboard/acer/g43t-am3/early_init.c +++ b/src/mainboard/acer/g43t-am3/early_init.c @@ -18,7 +18,7 @@ ite_reg_write(GPIO_DEV, 0x29, 0x00); // GPIO set 5 /* Enable 3VSB during Suspend-to-RAM */ - ite_enable_3vsbsw(GPIO_DEV); + ite_set_3vsbsw(GPIO_DEV, true); /* Delay PWROK2 after 3VSBSW# during resume from Suspend-to-RAM */ ite_delay_pwrgd3(GPIO_DEV); diff --git a/src/mainboard/foxconn/g41s-k/early_init.c b/src/mainboard/foxconn/g41s-k/early_init.c index 29ae78e..2bb9b42 100644 --- a/src/mainboard/foxconn/g41s-k/early_init.c +++ b/src/mainboard/foxconn/g41s-k/early_init.c @@ -7,7 +7,7 @@ #include <superio/ite/it8720f/it8720f.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8720F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8720F_GPIO) +#define GPIO_DEV PNP_DEV(0x2e, IT8720F_GPIO) void bootblock_mainboard_early_init(void) { @@ -27,7 +27,7 @@ ite_reg_write(GPIO_DEV, 0xcb, 0x01); ite_reg_write(GPIO_DEV, 0xf5, 0x28); ite_reg_write(GPIO_DEV, 0xf6, 0x12); - ite_enable_3vsbsw(GPIO_DEV); + ite_set_3vsbsw(GPIO_DEV, true); /* Set up IRQ routing. */ RCBA16(D31IR) = 0x0132; diff --git a/src/mainboard/google/beltino/bootblock.c b/src/mainboard/google/beltino/bootblock.c index a68b03f..4139e38 100644 --- a/src/mainboard/google/beltino/bootblock.c +++ b/src/mainboard/google/beltino/bootblock.c @@ -9,7 +9,7 @@ { /* Early SuperIO setup */ ite_kill_watchdog(IT8772F_GPIO_DEV); - it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV); + ite_ac_resume_southbridge(IT8772F_EC_DEV); ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE); /* Turn on Power LED */ diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index cdaab35..d96ee11 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -81,9 +81,9 @@ # Skip keyboard init register "skip_keyboard" = "true" # Enable PECI on TMPIN3 - register "peci_tmpin" = "3" + register "TMPIN3.mode" = "THERMAL_PECI" # Enable FAN2 - register "fan2_enable" = "true" + register "FAN2.mode" = "FAN_SMART_SOFTWARE" device pnp 2e.0 off end # FDC device pnp 2e.1 on # Serial Port 1 diff --git a/src/mainboard/google/beltino/onboard.h b/src/mainboard/google/beltino/onboard.h index 8bd21ce..36295ec 100644 --- a/src/mainboard/google/beltino/onboard.h +++ b/src/mainboard/google/beltino/onboard.h @@ -26,7 +26,7 @@ #define IT8772F_BASE 0x2e #define IT8772F_SERIAL_DEV PNP_DEV(IT8772F_BASE, IT8772F_SP1) #define IT8772F_GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO) -#define IT8772F_SUPERIO_DEV PNP_DEV(IT8772F_BASE, 0) +#define IT8772F_EC_DEV PNP_DEV(IT8772F_BASE, IT8772F_EC) #ifndef __ACPI__ void lan_init(void); diff --git a/src/mainboard/google/jecht/bootblock.c b/src/mainboard/google/jecht/bootblock.c index db590cf..02b078e 100644 --- a/src/mainboard/google/jecht/bootblock.c +++ b/src/mainboard/google/jecht/bootblock.c @@ -8,7 +8,7 @@ void bootblock_mainboard_early_init(void) { /* Early SuperIO setup */ - it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV); + ite_ac_resume_southbridge(IT8772F_EC_DEV); ite_kill_watchdog(IT8772F_GPIO_DEV); ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index 1bf8a2a..215259a 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -75,15 +75,13 @@ # Skip keyboard init register "skip_keyboard" = "true" # Enable PECI on TMPIN3 - register "peci_tmpin" = "3" - # Disable use of TMPIN1 - register "tmpin1_mode" = "0" + register "TMPIN3.mode" = "THERMAL_PECI" # Enable Thermal Diode on TMPIN2 - register "tmpin2_mode" = "1" + register "TMPIN2.mode" = "THERMAL_DIODE" # Enable FAN2 - register "fan2_enable" = "true" + register "FAN2.mode" = "FAN_SMART_SOFTWARE" # Default FAN2 speed - register "fan2_speed" = "0x4d" + register "FAN2.pwm_start" = "30" device pnp 2e.0 off end # FDC device pnp 2e.1 on # Serial Port 1 diff --git a/src/mainboard/google/jecht/onboard.h b/src/mainboard/google/jecht/onboard.h index a6ba80a..ae68fb8 100644 --- a/src/mainboard/google/jecht/onboard.h +++ b/src/mainboard/google/jecht/onboard.h @@ -35,7 +35,7 @@ #define IT8772F_BASE 0x2e #define IT8772F_SERIAL_DEV PNP_DEV(IT8772F_BASE, IT8772F_SP1) #define IT8772F_GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO) -#define IT8772F_SUPERIO_DEV PNP_DEV(IT8772F_BASE, 0) +#define IT8772F_EC_DEV PNP_DEV(IT8772F_BASE, IT8772F_EC) /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ #define GPIO_SPI_WP 58 diff --git a/src/mainboard/libretrend/lt1000/bootblock.c b/src/mainboard/libretrend/lt1000/bootblock.c index 7756b04..7084e2e 100644 --- a/src/mainboard/libretrend/lt1000/bootblock.c +++ b/src/mainboard/libretrend/lt1000/bootblock.c @@ -14,7 +14,7 @@ void bootblock_mainboard_early_init(void) { ite_conf_clkin(GPIO_DEV, ITE_UART_CLK_PREDIVIDE_24); - ite_enable_3vsbsw(GPIO_DEV); + ite_set_3vsbsw(GPIO_DEV, true); ite_kill_watchdog(GPIO_DEV); ite_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/protectli/vault_cml/bootblock.c b/src/mainboard/protectli/vault_cml/bootblock.c index 82c46f9..17b394c 100644 --- a/src/mainboard/protectli/vault_cml/bootblock.c +++ b/src/mainboard/protectli/vault_cml/bootblock.c @@ -20,7 +20,7 @@ /* External CLKIN PCICLK */ ite_reg_write(GPIO_DEV, 0x71, 0x08); /* Enable 3VSB during Suspend-to-RAM */ - ite_enable_3vsbsw(GPIO_DEV); + ite_set_3vsbsw(GPIO_DEV, true); /* Delay PWROK2 after 3VSBSW# during resume from Suspend-to-RAM */ ite_delay_pwrgd3(GPIO_DEV); ite_kill_watchdog(GPIO_DEV); diff --git a/src/mainboard/protectli/vault_kbl/bootblock.c b/src/mainboard/protectli/vault_kbl/bootblock.c index a11b5fd..8100263 100644 --- a/src/mainboard/protectli/vault_kbl/bootblock.c +++ b/src/mainboard/protectli/vault_kbl/bootblock.c @@ -10,7 +10,7 @@ void bootblock_mainboard_early_init(void) { ite_conf_clkin(GPIO_DEV, ITE_UART_CLK_PREDIVIDE_24); - ite_enable_3vsbsw(GPIO_DEV); + ite_set_3vsbsw(GPIO_DEV, true); ite_kill_watchdog(GPIO_DEV); ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 092115c..87bc5de 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -209,9 +209,9 @@ end device ref lpc_espi on chip superio/ite/it8772f - register "peci_tmpin" = "3" - register "tmpin1_mode" = "THERMAL_RESISTOR" - register "tmpin2_mode" = "THERMAL_RESISTOR" + register "TMPIN1.mode" = "THERMAL_RESISTOR" + register "TMPIN2.mode" = "THERMAL_RESISTOR" + register "TMPIN3.mode" = "THERMAL_PECI" # FAN2 available on fan header but unused device pnp 2e.0 off end # FDC device pnp 2e.1 on # Serial Port 1 diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index ae3aab5..853e519 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -88,9 +88,9 @@ # Skip keyboard init register "skip_keyboard" = "true" # Enable PECI on TMPIN3 - register "peci_tmpin" = "3" + register "TMPIN3.mode" = "THERMAL_PECI" # Enable FAN3 - register "fan3_enable" = "true" + register "FAN3.mode" = "FAN_SMART_SOFTWARE" device pnp 2e.0 off end # FDC device pnp 2e.1 on # Serial Port 1 diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index 681373c..2719e33 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -12,9 +12,9 @@ #include <southbridge/intel/common/gpio.h> #include <superio/smsc/lpc47n207/lpc47n207.h> -#define SUPERIO_DEV PNP_DEV(0x2e, 0) #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) +#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) +#define EC_DEV PNP_DEV(0x2e, IT8772F_EC) void mainboard_late_rcba_config(void) { @@ -58,17 +58,17 @@ * GPIO10 as USBPWRON12# * GPIO12 as USBPWRON13# */ - it8772f_gpio_setup(SUPERIO_DEV, 1, 0x05, 0x05, 0x00, 0x05, 0x05); + it8772f_gpio_setup(GPIO_DEV, 1, 0x05, 0x05, 0x00, 0x05, 0x05); /* * GPIO22 as wake SCI# */ - it8772f_gpio_setup(SUPERIO_DEV, 2, 0x04, 0x04, 0x00, 0x04, 0x04); + it8772f_gpio_setup(GPIO_DEV, 2, 0x04, 0x04, 0x00, 0x04, 0x04); /* * GPIO32 as EXTSMI# */ - it8772f_gpio_setup(SUPERIO_DEV, 3, 0x04, 0x04, 0x00, 0x04, 0x04); + it8772f_gpio_setup(GPIO_DEV, 3, 0x04, 0x04, 0x00, 0x04, 0x04); /* * GPIO45 as LED_POWER# @@ -82,8 +82,8 @@ * GPIO51 as USBPWRON8# * GPIO52 as USBPWRON1# */ - it8772f_gpio_setup(SUPERIO_DEV, 5, 0x06, 0x06, 0x00, 0x06, 0x06); - it8772f_gpio_setup(SUPERIO_DEV, 6, 0x00, 0x00, 0x00, 0x00, 0x00); + it8772f_gpio_setup(GPIO_DEV, 5, 0x06, 0x06, 0x00, 0x06, 0x06); + it8772f_gpio_setup(GPIO_DEV, 6, 0x00, 0x00, 0x00, 0x00, 0x00); } void mainboard_fill_pei_data(struct pei_data *pei_data) @@ -117,7 +117,7 @@ setup_sio_gpios(); /* Early SuperIO setup */ - it8772f_ac_resume_southbridge(SUPERIO_DEV); + ite_ac_resume_southbridge(EC_DEV); ite_kill_watchdog(GPIO_DEV); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/samsung/stumpy/smihandler.c b/src/mainboard/samsung/stumpy/smihandler.c index 5000086..f9b9d3b 100644 --- a/src/mainboard/samsung/stumpy/smihandler.c +++ b/src/mainboard/samsung/stumpy/smihandler.c @@ -9,7 +9,7 @@ /* Include for SIO helper functions */ #include <superio/ite/it8772f/it8772f.h> -#define SUPERIO_DEV PNP_DEV(0x2e, 0) +#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) /* * Change LED_POWER# (SIO GPIO 45) state based on sleep type. @@ -20,14 +20,14 @@ switch (slp_typ) { case ACPI_S3: case ACPI_S4: - it8772f_gpio_led(SUPERIO_DEV, 4 /* set */, (0x1 << 5) /* select */, + it8772f_gpio_led(GPIO_DEV, 4 /* set */, (0x1 << 5) /* select */, (0x1 << 5) /* polarity */, (0x1 << 5) /* 1 = pullup */, (0x1 << 5) /* output */, 0x00, /* 0 = Alternate function */ SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); break; case ACPI_S5: - it8772f_gpio_led(SUPERIO_DEV, 4 /* set */, (0x1 << 5) /* select */, + it8772f_gpio_led(GPIO_DEV, 4 /* set */, (0x1 << 5) /* select */, 0x00 /* polarity: non-inverting */, 0x00 /* 0 = pulldown */, (0x1 << 5) /* output */, (0x1 << 5) /* 1 = Simple IO function */, SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); diff --git a/src/superio/ite/Makefile.mk b/src/superio/ite/Makefile.mk index b6d0199..d44ade4 100644 --- a/src/superio/ite/Makefile.mk +++ b/src/superio/ite/Makefile.mk @@ -7,6 +7,9 @@ ## include generic ite environment controller driver ramstage-$(CONFIG_SUPERIO_ITE_ENV_CTRL) += common/env_ctrl.c +## include generic ite driver to smm to control S3-relevant functions +smm-$(CONFIG_SUPERIO_ITE_COMMON_PRE_RAM) += common/early_serial.c + subdirs-y += it8528e subdirs-y += it8613e subdirs-y += it8623e diff --git a/src/superio/ite/common/Kconfig b/src/superio/ite/common/Kconfig index 36c1496..aefda46 100644 --- a/src/superio/ite/common/Kconfig +++ b/src/superio/ite/common/Kconfig @@ -48,4 +48,14 @@ Temperature can be read to any TMPIN from an external sensor via SST/PECI (instead of TMPIN3 only). +config SUPERIO_ITE_ENV_CTRL_FAN_VECTOR + bool + help + Special fan control that will assist the smart control + +config SUPERIO_ITE_ENV_CTRL_FAN_VECTOR_RANGED + bool + help + Range and negative slope support + endif diff --git a/src/superio/ite/common/early_serial.c b/src/superio/ite/common/early_serial.c index 5ff403f..ff7deaa 100644 --- a/src/superio/ite/common/early_serial.c +++ b/src/superio/ite/common/early_serial.c @@ -15,6 +15,8 @@ #define ITE_CONFIG_REG_WATCHDOG 0x72 /* watchdog config */ #define ITE_CONFIG_REG_WDT_TIMEOUT_LSB 0x73 /* watchdog timeout (LSB) */ #define ITE_CONFIG_REG_WDT_TIMEOUT_MSB 0x74 /* watchdog timeout (MSB) */ +#define ITE_CONFIG_REG_APC_PME_CTL1 0xf2 /* APC_PME Control 1 */ +#define ITE_CONFIG_REG_APC_PME_CTL2 0xf4 /* APC_PME Control 2 */ /* Helper procedure */ static void ite_sio_write(pnp_devfn_t dev, u8 reg, u8 value) @@ -74,6 +76,7 @@ * * LDN 7, reg 0x2a - needed for S3, or memory power will be cut off * this was documented only in IT8712F_V0.9.2! + * Also documented in IT8728F_V0.4.2 and IT8772E_V0.4 * * Enable 3VSBSW#. (For System Suspend-to-RAM) * 0: 3VSBSW# will be always inactive. @@ -84,13 +87,16 @@ * and pass: GPIO_DEV */ -void ite_enable_3vsbsw(pnp_devfn_t dev) +void ite_set_3vsbsw(pnp_devfn_t dev, bool enable) { u8 tmp; pnp_enter_conf_state(dev); pnp_set_logical_device(dev); tmp = pnp_read_config(dev, ITE_CONFIG_REG_MFC); - tmp |= 0x80; + if (enable) + tmp |= 0x80; + else + tmp &= ~0x80; pnp_write_config(dev, ITE_CONFIG_REG_MFC, tmp); pnp_exit_conf_state(dev); } @@ -136,3 +142,38 @@ ite_sio_write(dev, ITE_CONFIG_REG_WDT_TIMEOUT_MSB, 0x00); pnp_exit_conf_state(dev); } + +/* + * Disable PME# Output + * pass EC_DEV + */ +void ite_pme_out_disable(pnp_devfn_t dev) +{ + u8 tmp; + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + tmp = pnp_read_config(dev, ITE_CONFIG_REG_APC_PME_CTL1); + tmp |= 0x40; + pnp_write_config(dev, ITE_CONFIG_REG_APC_PME_CTL1, tmp); + pnp_exit_conf_state(dev); +} + +/* + * Set AC resume to be up to the Southbridge + * pass EC_DEV + */ +void ite_ac_resume_southbridge(pnp_devfn_t dev) +{ + u8 tmp; + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + tmp = pnp_read_config(dev, ITE_CONFIG_REG_APC_PME_CTL2); + /* + * Set both + * 6: Gate Extra PWRON# Pulse + * 5: PSON# state when 3VSB switched to on + */ + tmp |= 0x60; + pnp_write_config(dev, ITE_CONFIG_REG_APC_PME_CTL2, tmp); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index 9149c58..c9fe50b 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -7,6 +7,7 @@ #include "env_ctrl.h" #include "env_ctrl_chip.h" +#include "mainboard_impl.h" static void extemp_force_idle_status(const u16 base) { @@ -78,12 +79,16 @@ "PECI to TMPIN2 not supported on IT8721F\n"); return; } - if (reg & ITE_EC_ADC_TEMP_EXT_REPORTS_TO_MASK) { + u8 reg_new = (reg & ~ITE_EC_ADC_TEMP_EXT_REPORTS_TO_MASK) + | ITE_EC_ADC_TEMP_EXT_REPORTS_TO(tmpin); + /* Registers stick on reboot and resume, + * don't warn for correct reg values */ + if (reg & ITE_EC_ADC_TEMP_EXT_REPORTS_TO_MASK && + reg != reg_new) { printk(BIOS_WARNING, - "PECI specified for multiple TMPIN\n"); - return; + "PECI specified for another TMPIN, overwriting\n"); } - reg |= ITE_EC_ADC_TEMP_EXT_REPORTS_TO(tmpin); + reg = reg_new; } else if (tmpin == 3) { reg_extra |= ITE_EC_ADC_TEMP_EXTRA_TMPIN3_EXT; pnp_write_hwm5_index(base, ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE, @@ -102,6 +107,8 @@ case THERMAL_RESISTOR: reg |= ITE_EC_ADC_TEMP_RESISTOR_MODE(tmpin); break; + case THERMAL_MODE_DISABLED: + break; default: printk(BIOS_WARNING, "Unsupported thermal mode 0x%x on TMPIN%d\n", conf->mode, tmpin); @@ -115,7 +122,11 @@ reg = pnp_read_hwm5_index(base, ITE_EC_BEEP_ENABLE); reg |= ITE_EC_TEMP_ADJUST_WRITE_ENABLE; pnp_write_hwm5_index(base, ITE_EC_BEEP_ENABLE, reg); - pnp_write_hwm5_index(base, ITE_EC_TEMP_ADJUST[tmpin-1], conf->offset); + u8 offset = conf->offset; + if (offset == CPU_TJ_MAX_OFFSET) { + offset = cpu_get_temp_offset(); + } + pnp_write_hwm5_index(base, ITE_EC_TEMP_ADJUST[tmpin-1], offset); } /* Set temperature limits */ @@ -177,7 +188,9 @@ conf->tmp_full ? conf->tmp_full : 127); delta_temp = ITE_EC_FAN_CTL_DELTA_TEMP_INTRVL(conf->tmp_delta); - delta_temp |= ITE_EC_FAN_CTL_FULL_AT_THRML_LMT(conf->full_lmt); + if (!CONFIG(SUPERIO_ITE_IT8772F)) { + delta_temp |= ITE_EC_FAN_CTL_FULL_AT_THRML_LMT(conf->full_lmt); + } pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_DELTA_TEMP(fan), delta_temp); } @@ -247,6 +260,41 @@ } } +static void enable_fan_vector(const u16 base, const u8 fan_vector, + const struct ite_ec_fan_vector_config *const conf) +{ + u8 reg; + + u8 start = conf->tmp_start; + if (!start) + start = 0xff; + pnp_write_hwm5_index(base, ITE_EC_FAN_VEC_CTL_LIMIT_START(fan_vector), start); + + s8 slope = conf->slope; + bool slope_neg = slope < 0; + if (slope <= -128) + reg = 127; + else if (slope_neg) + reg = -slope; + else + reg = slope; + reg |= ITE_EC_FAN_VEC_CTL_TMPIN0(conf->tmpin); + pnp_write_hwm5_index(base, ITE_EC_FAN_VEC_CTL_SLOPE(fan_vector), reg); + + reg = ITE_EC_FAN_VEC_CTL_DELTA_TEMP_INTRVL(conf->tmp_delta); + reg |= ITE_EC_FAN_VEC_CTL_FANOUT(conf->fanout); + reg |= ITE_EC_FAN_VEC_CTL_TMPIN1(conf->tmpin); + pnp_write_hwm5_index(base, ITE_EC_FAN_VEC_CTL_DELTA(fan_vector), reg); + + if (CONFIG(SUPERIO_ITE_ENV_CTRL_FAN_VECTOR_RANGED)) { + reg = conf->tmp_range & 0x7f; + reg |= ITE_EC_FAN_VEC_CTL_SLOPESIGN(slope_neg); + pnp_write_hwm5_index(base, ITE_EC_FAN_VEC_CTL_RANGE(fan_vector), reg); + } else if (slope_neg) { + printk(BIOS_WARNING, "Unsupported negative slope on fan vector control\n"); + } +} + static void enable_beeps(const u16 base, const struct ite_ec_config *const conf) { u8 reg = 0; @@ -301,12 +349,23 @@ } /* Enable reading of voltage pins */ - pnp_write_hwm5_index(base, ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE, conf->vin_mask); + u8 vin_mask = conf->vin_mask; + if (CONFIG(SUPERIO_ITE_IT8772F)) { + // Not supported on IT8772F + vin_mask &= ~(VIN5 | VIN6); + } + pnp_write_hwm5_index(base, ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE, vin_mask); /* Enable FANx if configured */ for (i = 0; i < ITE_EC_FAN_CNT; ++i) enable_fan(base, i + 1, &conf->fan[i]); + /* Enable Special FAN Vector X if configured */ + if (CONFIG(SUPERIO_ITE_ENV_CTRL_FAN_VECTOR)) { + for (i = 0; i < ITE_EC_FAN_VECTOR_CNT; ++i) + enable_fan_vector(base, i, &conf->fan_vector[i]); + } + /* Enable beeps if configured */ enable_beeps(base, conf); @@ -319,3 +378,10 @@ if (conf->tmpin[i].mode == THERMAL_PECI) extemp_force_idle_status(base); } + +__weak u8 cpu_get_temp_offset(void) +{ + printk(BIOS_WARNING, + "CPU_TJ_MAX_OFFSET used but not implemented. Falling back to 127\n"); + return 127; +} diff --git a/src/superio/ite/common/env_ctrl.h b/src/superio/ite/common/env_ctrl.h index 5a31e7c..fc9916c 100644 --- a/src/superio/ite/common/env_ctrl.h +++ b/src/superio/ite/common/env_ctrl.h @@ -199,6 +199,17 @@ #define ITE_EC_FAN_CTL_TARGET_ZONE(x) (0x66 + ((x)-1) * 8) #define ITE_EC_FAN_CTL_TARGET_ZONE_MASK 0x0f +#define ITE_EC_FAN_VEC_CTL_LIMIT_START(x) (0x90 + (x) * 4) +#define ITE_EC_FAN_VEC_CTL_SLOPE(x) (0x91 + (x) * 4) +#define ITE_EC_FAN_VEC_CTL_DELTA(x) (0x92 + (x) * 4) +#define ITE_EC_FAN_VEC_CTL_RANGE(x) (0x93 + (x) * 4) + +#define ITE_EC_FAN_VEC_CTL_TMPIN0(x) (((x) & 0x1) << 7) +#define ITE_EC_FAN_VEC_CTL_TMPIN1(x) (((x) & 0x2) << 6) +#define ITE_EC_FAN_VEC_CTL_DELTA_TEMP_INTRVL(c) ITE_EC_FAN_CTL_DELTA_TEMP_INTRVL(c) +#define ITE_EC_FAN_VEC_CTL_FANOUT(x) (((x) & 0x3) << 5) +#define ITE_EC_FAN_VEC_CTL_SLOPESIGN(x) (((x) & 0x1) << 7) + #define ITE_EC_EXTEMP_STATUS 0x88 #define ITE_EC_EXTEMP_STATUS_HOST_BUSY (1 << 0) #define ITE_EC_EXTEMP_ADDRESS 0x89 diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h index 2bb0780..2a574b3 100644 --- a/src/superio/ite/common/env_ctrl_chip.h +++ b/src/superio/ite/common/env_ctrl_chip.h @@ -11,6 +11,8 @@ #define ITE_EC_FAN_CNT 3 #endif +#define ITE_EC_FAN_VECTOR_CNT 2 /* A, B */ + /* Supported thermal mode on TMPINx */ enum ite_ec_thermal_mode { THERMAL_MODE_DISABLED = 0, @@ -69,6 +71,17 @@ struct ite_ec_fan_smartconfig smart; }; +/* Special fan control modes that will assist smart control */ +struct ite_ec_fan_vector_config { + u8 tmpin; /* select TMPINx (1, 2 or 3) */ + u8 fanout; /* select FANx (1, 2 or 3) */ + u8 tmp_start; + u8 tmp_delta; + u8 tmp_range; /* restrict the range of the vector function, + 0x00 to disable */ + s8 slope; +}; + struct ite_ec_config { /* * Enable reading of voltage pins VINx. @@ -85,6 +98,13 @@ */ struct ite_ec_fan_config fan[ITE_EC_FAN_CNT]; +#if CONFIG(SUPERIO_ITE_ENV_CTRL_FAN_VECTOR) + /* + * Enable special FAN vector control. + */ + struct ite_ec_fan_vector_config fan_vector[ITE_EC_FAN_VECTOR_CNT]; +#endif + bool tmpin_beep; bool fan_beep; bool vin_beep; @@ -111,4 +131,9 @@ #define FAN4 ec.fan[3] #define FAN5 ec.fan[4] +#define FAN_VECA ec.fan_vector[0] +#define FAN_VECB ec.fan_vector[1] + +#define CPU_TJ_MAX_OFFSET 0xFF + #endif /* SUPERIO_ITE_ENV_CTRL_CHIP_H */ diff --git a/src/superio/ite/common/ite.h b/src/superio/ite/common/ite.h index 3e9b5028..c9dfb22 100644 --- a/src/superio/ite/common/ite.h +++ b/src/superio/ite/common/ite.h @@ -14,9 +14,11 @@ /* Some boards need to init wdt+gpio's very early */ void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value); -void ite_enable_3vsbsw(pnp_devfn_t dev); +void ite_set_3vsbsw(pnp_devfn_t dev, bool enable); void ite_delay_pwrgd3(pnp_devfn_t dev); void ite_kill_watchdog(pnp_devfn_t dev); +void ite_pme_out_disable(pnp_devfn_t dev); +void ite_ac_resume_southbridge(pnp_devfn_t dev); void pnp_enter_conf_state(pnp_devfn_t dev); void pnp_exit_conf_state(pnp_devfn_t dev); diff --git a/src/superio/ite/common/mainboard_impl.h b/src/superio/ite/common/mainboard_impl.h new file mode 100644 index 0000000..07c6aa8 --- /dev/null +++ b/src/superio/ite/common/mainboard_impl.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_ITE_COMMON_MAINBOARD_IMPL_H +#define SUPERIO_ITE_COMMON_MAINBOARD_IMPL_H + +#include <stdint.h> + +u8 cpu_get_temp_offset(void); + +#endif /* SUPERIO_ITE_COMMON_MAINBOARD_IMPL_H */ diff --git a/src/superio/ite/it8728f/Kconfig b/src/superio/ite/it8728f/Kconfig index 6d02c0b..6e459e8 100644 --- a/src/superio/ite/it8728f/Kconfig +++ b/src/superio/ite/it8728f/Kconfig @@ -5,8 +5,8 @@ select SUPERIO_ITE_COMMON_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 - select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG select SUPERIO_ITE_ENV_CTRL_8BIT_PWM select SUPERIO_ITE_ENV_CTRL_5FANS select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + select SUPERIO_ITE_ENV_CTRL_FAN_VECTOR diff --git a/src/superio/ite/it8772f/Kconfig b/src/superio/ite/it8772f/Kconfig index 194c736..9953a2e 100644 --- a/src/superio/ite/it8772f/Kconfig +++ b/src/superio/ite/it8772f/Kconfig @@ -3,3 +3,10 @@ config SUPERIO_ITE_IT8772F bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_ENV_CTRL + select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + select SUPERIO_ITE_ENV_CTRL_8BIT_PWM + select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG + select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + select SUPERIO_ITE_ENV_CTRL_FAN_VECTOR + select SUPERIO_ITE_ENV_CTRL_FAN_VECTOR_RANGED diff --git a/src/superio/ite/it8772f/chip.h b/src/superio/ite/it8772f/chip.h index eb3ccd2..1169b4b 100644 --- a/src/superio/ite/it8772f/chip.h +++ b/src/superio/ite/it8772f/chip.h @@ -3,12 +3,11 @@ #ifndef SUPERIO_ITE_IT8772F_CHIP_H #define SUPERIO_ITE_IT8772F_CHIP_H -#include <device/device.h> -#include <types.h> - -#include "it8772f.h" +#include <superio/ite/common/env_ctrl_chip.h> struct superio_ite_it8772f_config { + struct ite_ec_config ec; + /* GPIO SimpleIO register values via devicetree.cb */ u8 gpio_set1; u8 gpio_set2; @@ -18,31 +17,6 @@ u8 gpio_set6; bool skip_keyboard; - - /* - * Enable external temperature sensor to use PECI GetTemp() - * command and store in register TMPIN 1, 2, or 3. - */ - u8 peci_tmpin; - - /* - * Enable thermal mode on tmpinx. - */ - enum thermal_mode tmpin1_mode; - enum thermal_mode tmpin2_mode; - - /* - * Enable a FAN for software control. - */ - bool fan1_enable; - bool fan2_enable; - bool fan3_enable; - - /* - * Default FAN speed - */ - u8 fan2_speed; - u8 fan3_speed; }; #endif /* SUPERIO_ITE_IT8772F_CHIP_H */ diff --git a/src/superio/ite/it8772f/early_init.c b/src/superio/ite/it8772f/early_init.c index e41b206..efbb035 100644 --- a/src/superio/ite/it8772f/early_init.c +++ b/src/superio/ite/it8772f/early_init.c @@ -5,10 +5,13 @@ #include <device/pnp_ops.h> #include "it8772f.h" +#include "../common/ite.h" + +#define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ /* NOTICE: This file is deprecated, use ite/common instead */ -void it8772f_enter_conf(pnp_devfn_t dev) +static void it8772f_enter_conf(pnp_devfn_t dev) { u16 port = dev >> 8; @@ -18,27 +21,18 @@ outb((port == 0x4e) ? 0xaa : 0x55, port); } -void it8772f_exit_conf(pnp_devfn_t dev) +static void it8772f_exit_conf(pnp_devfn_t dev) { pnp_write_config(dev, IT8772F_CONFIG_REG_CC, 0x02); } -/* Set AC resume to be up to the Southbridge */ -void it8772f_ac_resume_southbridge(pnp_devfn_t dev) -{ - it8772f_enter_conf(dev); - pnp_write_config(dev, IT8772F_CONFIG_REG_LDN, IT8772F_EC); - pnp_write_config(dev, PNP_IDX_MSC4, 0x60); - it8772f_exit_conf(dev); -} - /* Configure a set of GPIOs */ void it8772f_gpio_setup(pnp_devfn_t dev, int set, u8 select, u8 polarity, u8 pullup, u8 output, u8 enable) { set--; /* Set 1 is offset 0 */ it8772f_enter_conf(dev); - pnp_write_config(dev, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); + pnp_set_logical_device(dev); if (set < 5) { pnp_write_config(dev, GPIO_REG_SELECT(set), select); pnp_write_config(dev, GPIO_REG_ENABLE(set), enable); @@ -55,7 +49,7 @@ { set--; /* Set 1 is offset 0 */ it8772f_enter_conf(dev); - pnp_write_config(dev, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); + pnp_set_logical_device(dev); if (set < 5) { pnp_write_config(dev, IT8772F_GPIO_LED_BLINK1_PINMAP, led_pin_map); pnp_write_config(dev, IT8772F_GPIO_LED_BLINK1_CONTROL, led_freq); diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h index 38cfe3b..4df21c5 100644 --- a/src/superio/ite/it8772f/it8772f.h +++ b/src/superio/ite/it8772f/it8772f.h @@ -3,13 +3,6 @@ #ifndef SUPERIO_ITE_IT8772F_H #define SUPERIO_ITE_IT8772F_H -/* Supported thermal mode on TMPINx */ -enum thermal_mode { - THERMAL_MODE_DISABLED = 0, - THERMAL_DIODE, - THERMAL_RESISTOR, -}; - #define IT8772F_FDC 0x00 /* Floppy disk controller */ #define IT8772F_SP1 0x01 /* Com1 */ #define IT8772F_EC 0x04 /* Environment controller */ @@ -18,71 +11,6 @@ #define IT8772F_GPIO 0x07 /* GPIO */ #define IT8772F_IR 0x0a /* Consumer IR */ -/* Environmental Controller interface */ -#define IT8772F_CONFIGURATION 0x00 -#define IT8772F_INTERFACE_SELECT 0x0a -#define IT8772F_INTERFACE_PSEUDO_EOC (1 << 7) -#define IT8772F_INTERFACE_SMB_ENABLE (1 << 6) -#define IT8772F_INTERFACE_SEL_DISABLE (0 << 4) -#define IT8772F_INTERFACE_SEL_SST_SLAVE (1 << 4) -#define IT8772F_INTERFACE_SEL_PECI (2 << 4) -#define IT8772F_INTERFACE_SEL_SST_HOST (3 << 4) -#define IT8772F_INTERFACE_CLOCK_32MHZ (0 << 3) -#define IT8772F_INTERFACE_CLOCK_24MHZ (1 << 3) -#define IT8772F_INTERFACE_SPEED_TOLERANCE (1 << 2) -#define IT8772F_INTERFACE_PECI_AWFCS (1 << 0) -#define IT8772F_FAN_TAC2_READ 0x0e -#define IT8772F_FAN_TAC3_READ 0x0f -#define IT8772F_FAN_MAIN_CTL 0x13 -#define IT8772F_FAN_MAIN_CTL_TAC_SMART(x) (1 << ((x)-1)) -#define IT8772F_FAN_MAIN_CTL_TAC_EN(x) (1 << ((x)+3)) -#define IT8772F_FAN_CTL_MODE 0x14 -#define IT8772F_FAN_CTL_ON(x) (1 << ((x)-1)) -#define IT8772F_FAN_PWM_MIN_DUTY (1 << 3) -#define IT8772F_FAN_PWM_CLOCK_48MHZ (0 << 4) -#define IT8772F_FAN_PWM_CLOCK_24MHZ (1 << 4) -#define IT8772F_FAN_PWM_CLOCK_8MHZ (3 << 4) -#define IT8772F_FAN_PWM_CLOCK_6MHZ (4 << 4) -#define IT8772F_FAN_PWM_CLOCK_3MHZ (5 << 4) -#define IT8772F_FAN_PWM_CLOCK_1_5MHZ (6 << 4) -#define IT8772F_FAN_PWM_CLOCK_51KHZ (7 << 4) -#define IT8772F_FAN_CTL_POLARITY_LOW (0 << 7) -#define IT8772F_FAN_CTL_POLARITY_HIGH (1 << 7) -#define IT8772F_FAN_CTL2_PWM_MODE 0x16 -#define IT8772F_FAN_CTL3_PWM_MODE 0x17 -#define IT8772F_FAN_CTL_PWM_MODE_SOFTWARE (0 << 7) -#define IT8772F_FAN_CTL_PWM_MODE_AUTOMATIC (1 << 7) -#define IT8772F_ADC_TEMP_CHANNEL_ENABLE 0x51 -#define IT8772F_FAN_CTL2_PWM_START 0x6b -#define IT8772F_FAN_CTL2_AUTO_MODE 0x6c -#define IT8772F_FAN_CTL3_PWM_START 0x73 -#define IT8772F_FAN_CTL3_AUTO_MODE 0x74 -#define IT8772F_FAN_CTL_AUTO_SMOOTHING_DIS (0 << 7) -#define IT8772F_FAN_CTL_AUTO_SMOOTHING_EN (1 << 7) -#define IT8772F_EXTEMP_STATUS 0x88 -#define IT8772F_EXTEMP_STATUS_HOST_BUSY (1 << 0) -#define IT8772F_EXTEMP_ADDRESS 0x89 -#define IT8772F_EXTEMP_WRITE_LENGTH 0x8a -#define IT8772F_EXTEMP_READ_LENGTH 0x8b -#define IT8772F_EXTEMP_COMMAND 0x8c -#define IT8772F_EXTEMP_WRITE_DATA_2 0x8d -#define IT8772F_EXTEMP_CONTROL 0x8e -#define IT8772F_EXTEMP_CONTROL_AUTO_32HZ (0 << 6) -#define IT8772F_EXTEMP_CONTROL_AUTO_16HZ (1 << 6) -#define IT8772F_EXTEMP_CONTROL_AUTO_8HZ (2 << 6) -#define IT8772F_EXTEMP_CONTROL_AUTO_4HZ (3 << 6) -#define IT8772F_EXTEMP_CONTROL_AUTO_START (1 << 5) -#define IT8772F_EXTEMP_CONTROL_AUTO_ABORT (1 << 4) -#define IT8772F_EXTEMP_CONTROL_AUTO_TWO_DOMAIN (1 << 3) -#define IT8772F_EXTEMP_CONTROL_CONTENTION (1 << 2) -#define IT8772F_EXTEMP_CONTROL_SST_IDLE_HIGH (1 << 1) -#define IT8772F_EXTEMP_CONTROL_START (1 << 0) - -/* Standard PECI GetTemp */ -#define PECI_CLIENT_ADDRESS 0x30 -#define PECI_GETTEMP_COMMAND 0x01 -#define PECI_GETTEMP_WRITE_LENGTH 0x01 -#define PECI_GETTEMP_READ_LENGTH 0x02 /* GPIO interface */ #define IT8772F_GPIO_LED_BLINK1_PINMAP 0xf8 @@ -115,17 +43,9 @@ #include <device/pnp_type.h> #include <stdint.h> -void it8772f_ac_resume_southbridge(pnp_devfn_t dev); void it8772f_gpio_setup(pnp_devfn_t dev, int set, u8 select, u8 polarity, u8 pullup, u8 output, u8 enable); -/* FIXME: should be static so will be removed later.. */ -/* Global configuration registers. */ -#define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8772F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ - -void it8772f_enter_conf(pnp_devfn_t dev); -void it8772f_exit_conf(pnp_devfn_t dev); void it8772f_gpio_led(pnp_devfn_t dev, int set, u8 select, u8 polarity, u8 pullup, u8 output, u8 enable, u8 led_pin_map, u8 led_freq); diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index 1771368..b4db663 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -4,6 +4,7 @@ #include <device/pnp.h> #include <console/console.h> #include <pc80/keyboard.h> +#include <superio/ite/common/env_ctrl.h> #include <arch/io.h> #include <delay.h> #include <superio/conf_mode.h> @@ -12,155 +13,6 @@ #include "chip.h" /* FIXME */ #include "it8772f.h" -/* FIXME: see if the common ITE environment controller code can be used here */ - -static void it8772f_extemp_force_idle_status(struct resource *res) -{ - u8 reg; - int retries = 10; - - /* Wait up to 10ms for non-busy state. */ - while (retries > 0) { - reg = pnp_read_hwm5_index(res->base, IT8772F_EXTEMP_STATUS); - - if ((reg & IT8772F_EXTEMP_STATUS_HOST_BUSY) == 0x0) - break; - - retries--; - - mdelay(1); - } - - if (retries == 0 && (reg & IT8772F_EXTEMP_STATUS_HOST_BUSY) == 0x1) { - /* - * SIO is busy due to unfinished peci transaction. - * Re-configure Register 0x8E to terminate processes. - */ - pnp_write_hwm5_index(res->base, IT8772F_EXTEMP_CONTROL, - IT8772F_EXTEMP_CONTROL_AUTO_4HZ | - IT8772F_EXTEMP_CONTROL_AUTO_START); - } -} - -/* - * Setup External Temperature to read via PECI into TMPINx register - */ -static void it8772f_enable_peci(struct resource *res, int tmpin) -{ - if (tmpin < 1 || tmpin > 3) - return; - - /* Enable PECI interface */ - pnp_write_hwm5_index(res->base, IT8772F_INTERFACE_SELECT, - IT8772F_INTERFACE_SEL_PECI | - IT8772F_INTERFACE_SPEED_TOLERANCE); - - /* Setup External Temperature using PECI GetTemp */ - pnp_write_hwm5_index(res->base, IT8772F_EXTEMP_ADDRESS, - PECI_CLIENT_ADDRESS); - pnp_write_hwm5_index(res->base, IT8772F_EXTEMP_COMMAND, - PECI_GETTEMP_COMMAND); - pnp_write_hwm5_index(res->base, IT8772F_EXTEMP_WRITE_LENGTH, - PECI_GETTEMP_WRITE_LENGTH); - pnp_write_hwm5_index(res->base, IT8772F_EXTEMP_READ_LENGTH, - PECI_GETTEMP_READ_LENGTH); - pnp_write_hwm5_index(res->base, IT8772F_EXTEMP_CONTROL, - IT8772F_EXTEMP_CONTROL_AUTO_4HZ | - IT8772F_EXTEMP_CONTROL_AUTO_START); - - /* External Temperature reported in TMPINx register */ - pnp_write_hwm5_index(res->base, IT8772F_ADC_TEMP_CHANNEL_ENABLE, - (tmpin & 3) << 6); -} - -/* - * Set up External Temperature to read via thermal diode/resistor - * into TMPINx register - */ -static void it8772f_enable_tmpin(struct resource *res, int tmpin, - enum thermal_mode mode) -{ - u8 reg; - - if (tmpin != 1 && tmpin != 2) - return; - - reg = pnp_read_hwm5_index(res->base, IT8772F_ADC_TEMP_CHANNEL_ENABLE); - - switch (mode) { - case THERMAL_DIODE: - /* Thermal Diode Mode */ - pnp_write_hwm5_index(res->base, IT8772F_ADC_TEMP_CHANNEL_ENABLE, - reg | tmpin); - break; - case THERMAL_RESISTOR: - /* Thermal Resistor Mode */ - pnp_write_hwm5_index(res->base, IT8772F_ADC_TEMP_CHANNEL_ENABLE, - reg | (tmpin << 3)); - break; - default: - printk(BIOS_ERR, "Unsupported thermal mode 0x%x on TMPIN%d\n", - mode, tmpin); - return; - } - - reg = pnp_read_hwm5_index(res->base, IT8772F_CONFIGURATION); - - /* Enable the startup of monitoring operation */ - pnp_write_hwm5_index(res->base, IT8772F_CONFIGURATION, reg | 0x01); -} - -/* - * Setup a FAN PWM interface for software control - */ -static void it8772f_enable_fan(struct resource *res, int fan, u8 fan_speed) -{ - u8 reg; - - if (fan < 1 || fan > 3) - return; - - /* Enable 6MHz (23.43kHz PWM) active high output */ - reg = pnp_read_hwm5_index(res->base, IT8772F_FAN_CTL_MODE); - reg |= IT8772F_FAN_CTL_ON(fan) | - IT8772F_FAN_PWM_CLOCK_6MHZ | - IT8772F_FAN_CTL_POLARITY_HIGH; - pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL_MODE, reg); - - /* Enable output in smart mode */ - reg = pnp_read_hwm5_index(res->base, IT8772F_FAN_MAIN_CTL); - reg |= IT8772F_FAN_MAIN_CTL_TAC_SMART(fan); - reg |= IT8772F_FAN_MAIN_CTL_TAC_EN(fan); - pnp_write_hwm5_index(res->base, IT8772F_FAN_MAIN_CTL, reg); - - switch (fan) { - case 2: - /* Enable software operation */ - pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL2_PWM_MODE, - IT8772F_FAN_CTL_PWM_MODE_SOFTWARE); - /* Disable Smoothing */ - pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL2_AUTO_MODE, - IT8772F_FAN_CTL_AUTO_SMOOTHING_DIS); - /* Set a default fan speed */ - if (fan_speed) - pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL2_PWM_START, - fan_speed); - break; - case 3: - /* Enable software operation */ - pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL3_PWM_MODE, - IT8772F_FAN_CTL_PWM_MODE_SOFTWARE); - /* Disable Smoothing */ - pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL3_AUTO_MODE, - IT8772F_FAN_CTL_AUTO_SMOOTHING_DIS); - /* Set a default fan speed */ - if (fan_speed) - pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL3_PWM_START, - fan_speed); - break; - } -} - static void it8772f_init(struct device *dev) { struct superio_ite_it8772f_config *conf = dev->chip_info; @@ -171,35 +23,11 @@ switch (dev->path.pnp.device) { case IT8772F_EC: + conf = dev->chip_info; res = probe_resource(dev, PNP_IDX_IO0); - if (!res) + if (!conf || !res) break; - - /* Enable PECI if configured */ - it8772f_enable_peci(res, conf->peci_tmpin); - - /* Enable HWM if configured */ - if (conf->tmpin1_mode != THERMAL_MODE_DISABLED) - it8772f_enable_tmpin(res, 1, conf->tmpin1_mode); - if (conf->tmpin2_mode != THERMAL_MODE_DISABLED) - it8772f_enable_tmpin(res, 2, conf->tmpin2_mode); - - /* Enable FANx if configured */ - if (conf->fan1_enable) - it8772f_enable_fan(res, 1, 0); - if (conf->fan2_enable) - it8772f_enable_fan(res, 2, - conf->fan2_speed ? conf->fan2_speed : 0x80); - if (conf->fan3_enable) - it8772f_enable_fan(res, 3, - conf->fan3_speed ? conf->fan3_speed : 0x80); - - /* - * System may get wrong temperature data when SIO is in - * busy state. Therefore, check the status and terminate - * processes if needed. - */ - it8772f_extemp_force_idle_status(res); + ite_ec_init(res->base, &conf->ec); break; case IT8772F_GPIO: /* Set GPIO output levels */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81310?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4d9d5460628e444dc20f620179b39c90dbc28c6 Gerrit-Change-Number: 81310 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Linn Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: cpu/x86: Use correct config flag for 1GiB page table
by Bora Guvendik (Code Review) 19 Mar '24

19 Mar '24

Attention is currently required from: Ashish Kumar Mishra, Jérémy Compostella. Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81343?usp=email ) Change subject: cpu/x86: Use correct config flag for 1GiB page table ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81343/comment/bbf99b86_30a48056 : PS4, Line 9: The patch below uses USE_1G_PAGETABLES config flag instead of > s/patch/commit Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic19812bc1f90cbe7d3739c42a0314b3650e0501d Gerrit-Change-Number: 81343 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Mon, 18 Mar 2024 23:03:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: amdfwtool: Add functions to link all the tables
by Felix Held (Code Review) 19 Mar '24

19 Mar '24

Attention is currently required from: Bao Zheng, Fred Reitberger, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81252?usp=email ) Change subject: amdfwtool: Add functions to link all the tables ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: would be good to mention in the commit message that integrate_psp_levels and integrate_bios_levels now only get called in the case where a level 2 directory table needs to be integrated into a level 1 directory table. at least that would have made it easier for me to see why only calling this in some cases is correct -- To view, visit https://review.coreboot.org/c/coreboot/+/81252?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieaf97208e943c79d7b76ea62eea9355138c220b9 Gerrit-Change-Number: 81252 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Mon, 18 Mar 2024 23:01:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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