coreboot-gerrit March 2024

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[XS] Change in coreboot[main]: vc/amd/opensil: add site-local path for phoenix source
by Marshall Dawson (Code Review) 18 Mar '24

18 Mar '24

Marshall Dawson has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/81190?usp=email ) Change subject: vc/amd/opensil: add site-local path for phoenix source ...................................................................... Abandoned For unreleased programs, we'll provide the path via a Kconfig inside site-local. -- To view, visit https://review.coreboot.org/c/coreboot/+/81190?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibe2dbc2f1ff88d893ecdf32f21f4644d5184b143 Gerrit-Change-Number: 81190 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: abandon

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[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Use DECLARE_REGION for FSP-M heap
by Julius Werner (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Chen, Gang C, Felix Held, Patrick Rudolph, Ronak Kanabar, Shuo Liu, Subrata Banik, Werner Zeh. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81097?usp=email ) Change subject: drivers/intel/fsp2_0: Use DECLARE_REGION for FSP-M heap ...................................................................... Patch Set 4: Code-Review+2 (1 comment) Patchset: PS3: > Hi Julius, about the usage of DECLARE_REGION, as of now I'm inclined to still keep it inside if (CON […] Yeah, sorry I should have been more clear on this... but I +2ed the earlier patch to signal that I'm okay with you doing it this way. -- To view, visit https://review.coreboot.org/c/coreboot/+/81097?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5f7d7855592d99b074f7ef49c285a13f8105f089 Gerrit-Change-Number: 81097 Gerrit-PatchSet: 4 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 18 Mar 2024 21:25:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: arch/x86: Add API to check if cache sets are power-of-two
by 9elements QA (Code Review) 18 Mar '24

18 Mar '24

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81268?usp=email ) Change subject: arch/x86: Add API to check if cache sets are power-of-two ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/202767 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/202765 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/202764 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/202763 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/202762 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/202761 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/202760 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/202759 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/202758 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/202757 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/202756 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/202755 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/81268?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I819e0d1aeb4c1dbe1cdf3115b2e172588a6e8da5 Gerrit-Change-Number: 81268 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 18 Mar 2024 21:23:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: arch/riscv: minimal changes to get sifive unmatched with non-SMP
by ron minnich (Code Review) 18 Mar '24

18 Mar '24

ron minnich has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81308?usp=email ) Change subject: arch/riscv: minimal changes to get sifive unmatched with non-SMP ...................................................................... arch/riscv: minimal changes to get sifive unmatched with non-SMP Change-Id: I2ac227e5b2833758506c8d0a8f6ac743ee226d58 Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/payload.c 1 file changed, 14 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/81308/1 diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c index 636462f..fd6fd3d 100644 --- a/src/arch/riscv/payload.c +++ b/src/arch/riscv/payload.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cbmem.h> +#include <delay.h> #include <program_loading.h> #include <stdint.h> #include <arch/boot.h> @@ -41,11 +42,16 @@ void (*doit)(int hart_id, void *fdt) = prog_entry(prog); int hart_id = read_csr(mhartid); uintptr_t status = read_csr(mstatus); - extern void *_text, *_estack; + extern char _text[], _estack[]; status = INSERT_FIELD(status, MSTATUS_MPIE, 0); + for (; hart_id != CONFIG_RISCV_WORKING_HARTID;) { + mdelay(1000 * hart_id + 1000); + } + switch (payload_mode) { case RISCV_PAYLOAD_MODE_S: + mstatus_init(); /* * Set up a PMP to protect coreboot, then close the PMPs. * If a mainboard or SoC needs other ranges @@ -61,8 +67,9 @@ * small, make this an NAPOT area. The linker scripts * should round _text and _estack to 4K. */ + printk(BIOS_DEBUG, "setup %p %p PMP_R\n", _text, _estack); setup_pmp((u64)(uintptr_t) _text, - (u64)(uintptr_t) _estack - (u64)(uintptr_t) _text, 0); + (u64)(uintptr_t) _estack - (u64)(uintptr_t) _text, PMP_R); /* * All pmp operations should be finished when close_pmp is called. @@ -82,6 +89,9 @@ write_csr(satp, 0); /* save stack to mscratch so trap_entry can use that as exception stack */ write_csr(mscratch, MACHINE_STACK_TOP()); + /* disable M-Mode interrupt */ + write_csr(mie, 0); + break; case RISCV_PAYLOAD_MODE_M: status = INSERT_FIELD(status, MSTATUS_MPP, PRV_M); @@ -94,8 +104,10 @@ die("wrong privilege level for payload"); break; } + printk(BIOS_DEBUG, "%s(%p, %p) mstatus: 0x%lx\n", __func__, doit, fdt, status); write_csr(mstatus, status); write_csr(mepc, doit); + printk(BIOS_DEBUG, "GO!\n"); asm volatile( "mv a0, %0\n\t" "mv a1, %1\n\t" -- To view, visit https://review.coreboot.org/c/coreboot/+/81308?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2ac227e5b2833758506c8d0a8f6ac743ee226d58 Gerrit-Change-Number: 81308 Gerrit-PatchSet: 1 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: cpu/x86: Use correct config flag for 1GiB page table
by Jérémy Compostella (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Ashish Kumar Mishra, Bora Guvendik. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81343?usp=email ) Change subject: cpu/x86: Use correct config flag for 1GiB page table ...................................................................... Patch Set 2: Code-Review-1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81343/comment/b8a97d7a_5bc552f2 : PS2, Line 9: The patch below uses USE_1G_PAGETABLES config flag instead of Please refer to the commit SHA1, format "commit <12-sha> ("headline")" instead of the gerrit link. -- To view, visit https://review.coreboot.org/c/coreboot/+/81343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic19812bc1f90cbe7d3739c42a0314b3650e0501d Gerrit-Change-Number: 81343 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Comment-Date: Mon, 18 Mar 2024 20:58:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: cpu/x86: Use correct config flag for 1GiB page table
by Bora Guvendik (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Jérémy Compostella. Hello Jérémy Compostella, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81343?usp=email to look at the new patch set (#2). Change subject: cpu/x86: Use correct config flag for 1GiB page table ...................................................................... cpu/x86: Use correct config flag for 1GiB page table The patch below uses USE_1G_PAGETABLES config flag instead of the correct USE_1G_PAGES_TLB. https://review.coreboot.org/c/coreboot/+/80088 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: Ic19812bc1f90cbe7d3739c42a0314b3650e0501d --- M src/cpu/x86/64bit/Makefile.mk 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/81343/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic19812bc1f90cbe7d3739c42a0314b3650e0501d Gerrit-Change-Number: 81343 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: cpu/x86: Use correct config flag for 1GiB page table
by Bora Guvendik (Code Review) 18 Mar '24

18 Mar '24

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81343?usp=email ) Change subject: cpu/x86: Use correct config flag for 1GiB page table ...................................................................... cpu/x86: Use correct config flag for 1GiB page table The patch below uses USE_1G_PAGETABLES config flag instead of the correct USE_1G_PAGES_TLB. https://review.coreboot.org/c/coreboot/+/80088 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: Ic19812bc1f90cbe7d3739c42a0314b3650e0501d --- M src/cpu/x86/64bit/Makefile.mk 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/81343/1 diff --git a/src/cpu/x86/64bit/Makefile.mk b/src/cpu/x86/64bit/Makefile.mk index 680ab2d..a8dc1a2 100644 --- a/src/cpu/x86/64bit/Makefile.mk +++ b/src/cpu/x86/64bit/Makefile.mk @@ -3,7 +3,7 @@ all_x86-y += mode_switch.S all_x86-y += mode_switch2.S -ifeq ($(CONFIG_USE_1G_PAGETABLES),y) +ifeq ($(CONFIG_USE_1G_PAGES_TLB),y) PAGETABLE_SRC := pt1G.S else PAGETABLE_SRC := pt.S -- To view, visit https://review.coreboot.org/c/coreboot/+/81343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic19812bc1f90cbe7d3739c42a0314b3650e0501d Gerrit-Change-Number: 81343 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: acpi/acpi: mark CTBL coreboot table device as hidden
by Felix Held (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Cliff Huang, CoolStar, Lance Zhao, Matt DeVillier, Matt DeVillier, Tim Wawrzynczak. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81264?usp=email ) Change subject: acpi/acpi: mark CTBL coreboot table device as hidden ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > ultimately, is this just a cosmetic issue of having an unknown device in Windows Device Manager? If […] yes, it's just a cosmetic issue, but if i didn't know the details and reasoning behind this, i'd expect that there's something wrong with my machine when seeing the unknown device warning in the device manager -- To view, visit https://review.coreboot.org/c/coreboot/+/81264?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifaefeb662da33323460333d9ca9c0e8340720fd1 Gerrit-Change-Number: 81264 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Comment-Date: Mon, 18 Mar 2024 20:40:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: CoolStar <coolstarorganization(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/brya: Create yavista variant
by Henry Sun (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Derek Huang, Dinesh Gehlot, Eric Lai, Garen Wu, Kapil Porwal, Nick Vaccaro, Rasheed Hsueh. Henry Sun has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80342?usp=email ) Change subject: mb/google/brya: Create yavista variant ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: Hi Garen/Rash, Missing the V+1 vote here. please update local test and vote if it's done. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/80342?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6fa464a4dcd9551a42e8746e64c724b3582dbe02 Gerrit-Change-Number: 80342 Gerrit-PatchSet: 6 Gerrit-Owner: Rasheed Hsueh <hsueh.rasheed(a)inventec.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Garen Wu <wu.garen(a)inventec.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ryan Lin <ryan.lin(a)intel.corp-partner.google.com> Gerrit-CC: Steven Yeh <yeh.stevenct(a)inventec.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Rasheed Hsueh <hsueh.rasheed(a)inventec.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Garen Wu <wu.garen(a)inventec.corp-partner.google.com> Gerrit-Comment-Date: Mon, 18 Mar 2024 20:29:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: vc/amd/opensil/genoa_poc/mpio: use device status for port_present
by Felix Held (Code Review) 18 Mar '24

18 Mar '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81342?usp=email ) Change subject: vc/amd/opensil/genoa_poc/mpio: use device status for port_present ...................................................................... vc/amd/opensil/genoa_poc/mpio: use device status for port_present Only report the port as present in the MPIO_PORT_DATA_INITIALIZER_PCIE macro parameter when the device is enabled; otherwise report the port as disabled. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ieaa2af6c5ff3fc7e25992e7fdf14d37ee4a57d62 --- M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/81342/1 diff --git a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c index d279555..2da8bf0 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c +++ b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c @@ -157,7 +157,8 @@ config->gpio_group); port.EngineData = engine_data; const MPIO_PORT_DATA port_data = - MPIO_PORT_DATA_INITIALIZER_PCIE(MpioPortEnabled, + MPIO_PORT_DATA_INITIALIZER_PCIE(is_dev_enabled(dev) ? + MpioPortEnabled : MpioPortDisabled, PCI_SLOT(devfn), PCI_FUNC(devfn), config->hotplug, -- To view, visit https://review.coreboot.org/c/coreboot/+/81342?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieaa2af6c5ff3fc7e25992e7fdf14d37ee4a57d62 Gerrit-Change-Number: 81342 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit March 2024