coreboot-gerrit March 2024

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[XS] Change in coreboot[main]: cpu/x86: Use correct config flag for 1GiB page table
by Jérémy Compostella (Code Review) 19 Mar '24

19 Mar '24

Attention is currently required from: Ashish Kumar Mishra, Bora Guvendik. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81343?usp=email ) Change subject: cpu/x86: Use correct config flag for 1GiB page table ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81343/comment/2f8a680a_e2567d5c : PS4, Line 9: The patch below uses USE_1G_PAGETABLES config flag instead of > s/patch/commit Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic19812bc1f90cbe7d3739c42a0314b3650e0501d Gerrit-Change-Number: 81343 Gerrit-PatchSet: 5 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Comment-Date: Mon, 18 Mar 2024 23:01:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: cpu/x86: Use correct config flag for 1GiB page table
by Jérémy Compostella (Code Review) 19 Mar '24

19 Mar '24

Attention is currently required from: Ashish Kumar Mishra, Bora Guvendik. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81343?usp=email ) Change subject: cpu/x86: Use correct config flag for 1GiB page table ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic19812bc1f90cbe7d3739c42a0314b3650e0501d Gerrit-Change-Number: 81343 Gerrit-PatchSet: 5 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Comment-Date: Mon, 18 Mar 2024 23:00:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: cpu/x86: Use correct config flag for 1GiB page table
by Bora Guvendik (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Ashish Kumar Mishra, Bora Guvendik. Hello Ashish Kumar Mishra, Jérémy Compostella, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81343?usp=email to look at the new patch set (#5). Change subject: cpu/x86: Use correct config flag for 1GiB page table ...................................................................... cpu/x86: Use correct config flag for 1GiB page table The commit below uses USE_1G_PAGETABLES config flag instead of the correct USE_1G_PAGES_TLB. "commit ecbc243a45de3b7894e2fe6c8e22b5d07172274b ("cpu/x86: Add 1GiB pages for memory access up to 512GiB")" Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: Ic19812bc1f90cbe7d3739c42a0314b3650e0501d --- M src/cpu/x86/64bit/Makefile.mk 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/81343/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/81343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic19812bc1f90cbe7d3739c42a0314b3650e0501d Gerrit-Change-Number: 81343 Gerrit-PatchSet: 5 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: cpu/x86: Use correct config flag for 1GiB page table
by Jérémy Compostella (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Ashish Kumar Mishra, Bora Guvendik. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81343?usp=email ) Change subject: cpu/x86: Use correct config flag for 1GiB page table ...................................................................... Patch Set 4: Code-Review-1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81343/comment/c714e28c_48d3af10 : PS4, Line 9: The patch below uses USE_1G_PAGETABLES config flag instead of s/patch/commit -- To view, visit https://review.coreboot.org/c/coreboot/+/81343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic19812bc1f90cbe7d3739c42a0314b3650e0501d Gerrit-Change-Number: 81343 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Comment-Date: Mon, 18 Mar 2024 22:57:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: amdfwtool: Set the cookie when the table header is created
by Felix Held (Code Review) 18 Mar '24

18 Mar '24

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[M] Change in coreboot[main]: amdfwtool: Move the header creation into integration function
by Felix Held (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Bao Zheng, Fred Reitberger, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81253?usp=email ) Change subject: amdfwtool: Move the header creation into integration function ...................................................................... Patch Set 2: Code-Review+1 (2 comments) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/81253/comment/442e1836_4db90473 : PS2, Line 963: else if (ctx->pspdir2_b == NULL) i'd use else if (cookie == PSPL2_COOKIE && ctx->pspdir2_b == NULL) to properly handle the case of an unexpected cookie value https://review.coreboot.org/c/coreboot/+/81253/comment/66643912_50c8f602 : PS2, Line 1260: else if (ctx->biosdir2_b == NULL) i'd check for cookie == BHDL2_COOKIE && ctx->biosdir2_b == NULL to also cover the case of an unexpected cookie value -- To view, visit https://review.coreboot.org/c/coreboot/+/81253?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia9d78bb8145855203048208fcd67f8b9cd9d3199 Gerrit-Change-Number: 81253 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Mon, 18 Mar 2024 22:38:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: cpu/x86: Use correct config flag for 1GiB page table
by Bora Guvendik (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Ashish Kumar Mishra, Jérémy Compostella. Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81343?usp=email ) Change subject: cpu/x86: Use correct config flag for 1GiB page table ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81343/comment/2e32c2bb_28c802a0 : PS2, Line 9: The patch below uses USE_1G_PAGETABLES config flag instead of > Please refer to the commit SHA1, format "commit <12-sha> ("headline")" instead of the gerrit link. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic19812bc1f90cbe7d3739c42a0314b3650e0501d Gerrit-Change-Number: 81343 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Mon, 18 Mar 2024 22:33:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: cpu/x86: Use correct config flag for 1GiB page table
by Bora Guvendik (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Ashish Kumar Mishra, Bora Guvendik. Hello Ashish Kumar Mishra, Jérémy Compostella, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81343?usp=email to look at the new patch set (#4). Change subject: cpu/x86: Use correct config flag for 1GiB page table ...................................................................... cpu/x86: Use correct config flag for 1GiB page table The patch below uses USE_1G_PAGETABLES config flag instead of the correct USE_1G_PAGES_TLB. "commit ecbc243a45de3b7894e2fe6c8e22b5d07172274b ("cpu/x86: Add 1GiB pages for memory access up to 512GiB")" Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: Ic19812bc1f90cbe7d3739c42a0314b3650e0501d --- M src/cpu/x86/64bit/Makefile.mk 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/81343/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/81343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic19812bc1f90cbe7d3739c42a0314b3650e0501d Gerrit-Change-Number: 81343 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: cpu/x86: Use correct config flag for 1GiB page table
by Bora Guvendik (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Ashish Kumar Mishra, Bora Guvendik. Hello Ashish Kumar Mishra, Jérémy Compostella, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81343?usp=email to look at the new patch set (#3). Change subject: cpu/x86: Use correct config flag for 1GiB page table ...................................................................... cpu/x86: Use correct config flag for 1GiB page table The patch below uses USE_1G_PAGETABLES config flag instead of the correct USE_1G_PAGES_TLB. ecbc243a45de3b7894e2fe6c8e22b5d07172274b "commit ecbc243a45de3b7894e2fe6c8e22b5d07172274b ("cpu/x86: Add 1GiB pages for memory access up to 512GiB")" Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: Ic19812bc1f90cbe7d3739c42a0314b3650e0501d --- M src/cpu/x86/64bit/Makefile.mk 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/81343/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic19812bc1f90cbe7d3739c42a0314b3650e0501d Gerrit-Change-Number: 81343 Gerrit-PatchSet: 3 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: amdfwtool: Move the address of tables to the context
by Felix Held (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Bao Zheng, Fred Reitberger, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81225?usp=email ) Change subject: amdfwtool: Move the address of tables to the context ...................................................................... Patch Set 3: Code-Review+1 (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/81225/comment/af0e2e5a_63167f20 : PS3, Line 1640: ctx.pspdir = NULL; : ctx.pspdir2 = NULL; : ctx.pspdir2_b = NULL; : ctx.biosdir = NULL; : ctx.biosdir2 = NULL; : ctx.biosdir2_b = NULL; : ctx.ish_a_dir = NULL; : ctx.ish_b_dir = NULL; i'd move those directly before the if (cb_config.use_combo && combo_index > 0). in the first iteration of the do while loop, those are already NULL due to the context ctx = { 0 };, but at least for me it would make the code a bit easier to read if resetting those to NULL wouldn't be conditional on this not being the first iteration of the do while loop -- To view, visit https://review.coreboot.org/c/coreboot/+/81225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I98b7d01e32c75b4f13e23d496cd3de3da900678d Gerrit-Change-Number: 81225 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Mon, 18 Mar 2024 22:27:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit March 2024