coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
by ron minnich (Code Review) 18 Mar '24

18 Mar '24

ron minnich has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/81305?usp=email ) Change subject: Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/81305?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ba80ca4f1e0cd7468065b29fd0d07eeff5ec9ed Gerrit-Change-Number: 81305 Gerrit-PatchSet: 1 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[M] Change in coreboot[main]: WIP: simple, dumb, illegal instruction handling
by ron minnich (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Philipp Hug. Hello Philipp Hug, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81306?usp=email to look at the new patch set (#2). Change subject: WIP: simple, dumb, illegal instruction handling ...................................................................... WIP: simple, dumb, illegal instruction handling This is a very simple example of an illegal instruction handler. coreboot SBI is designed to minimize SBI functionality. This minimization is reflected in the lack of generality in the code. The ill() function switches out on a subset of instrution types, because C compilers tend to use a very limited subset of the possibilities of an instruction. In this case, code will support only two illegal instructions: csrrs x10, time, x0 csrrs x14, time, x0 On modern RISC-V systems, the trap will not even occur. At some point RISC-V community figured out that trapping on reading time was not always the best idea :-) So, in general, on future systems, reads will not trap. This CL can not go in until Hug's menvcfg support goes in. Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> Change-Id: I2d7b610698eca01b19a996bc80b0b08af4aed078 --- M src/arch/riscv/trap_handler.c M src/arch/riscv/virtual_memory.c 2 files changed, 50 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/81306/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81306?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d7b610698eca01b19a996bc80b0b08af4aed078 Gerrit-Change-Number: 81306 Gerrit-PatchSet: 2 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: drivers/intel/pmc_mux/conn: Copy ACPI _PLD property from USB port to mux
by Won Chung (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Emilie Roberts, Paul Menzel. Won Chung has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81089?usp=email ) Change subject: drivers/intel/pmc_mux/conn: Copy ACPI _PLD property from USB port to mux ...................................................................... Patch Set 7: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81089/comment/5f223da7_35409e7d : PS5, Line 9: Copy ACPI _PLD values from USB ports to corresponding USB muxes. > The general case: to change the USB role, we need to modify `/sys/class/usb_role/CONX-role-switch`. […] Added more details to the commit message Patchset: PS5: > When I do that grep on mithrax, for port0, I see `physical_location/panel:right`. […] I tried out on a leased lab dut and here is what I get. ``` mithrax-rev2 ~ # ls /sys/class/typec port0 port0-cable port0-partner port0-plug0 port1 mithrax-rev2 ~ # cat /sys/class/typec/port0/physical_location/panel right mithrax-rev2 ~ # cat /sys/class/typec/port1/physical_location/panel left mithrax-rev2 ~ # ectool usbpdmuxinfo Port 0: USB=1 DP=0 POLARITY=INVERTED HPD_IRQ=0 HPD_LVL=0 SAFE=0 TBT=0 USB4=0 Port 1: USB=0 DP=0 POLARITY=NORMAL HPD_IRQ=0 HPD_LVL=0 SAFE=0 TBT=0 USB4=0 ``` So in this case, right port (port 0) seems to be connected to something (maybe servo) and `ectool usbpdmuxinfo` also indicates port 0 in use. I see no issue here. Btw, this dut is on M124 with kernel v6.6.21. -- To view, visit https://review.coreboot.org/c/coreboot/+/81089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If27042cc995ef188f8a3e31444e994318ff98803 Gerrit-Change-Number: 81089 Gerrit-PatchSet: 7 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Emilie Roberts <hadrosaur(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Benson Leung <bleung(a)google.com> Gerrit-CC: Prashant Malani <pmalani(a)chromium.org> Gerrit-CC: Prashant Malani <pmalani(a)google.com> Gerrit-Attention: Emilie Roberts <hadrosaur(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 18 Mar 2024 18:02:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Emilie Roberts <hadrosaur(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Won Chung <wonchung(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: WIP: simple, dumb, illegal instruction handling
by ron minnich (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Philipp Hug. ron minnich has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81306?usp=email ) Change subject: WIP: simple, dumb, illegal instruction handling ...................................................................... WIP: simple, dumb, illegal instruction handling This is a very simple example of an illegal instruction handler. coreboot SBI is designed to minimize SBI functionality. This minimization is reflected in the lack of generality in the code. The ill() function switches out on a subset of instrution types, because C compilers tend to use a very limited subset of the possibilities of an instruction. In this case, code will support only two illegal instructions: csrrs x10, time, x0 csrrs x14, time, x0 On modern RISC-V systems, the trap will not even occur. At some point RISC-V community figured out that trapping on reading time was not always the best idea :-) So, in general, on future systems, reads will not trap. This CL can not go in until Hug's menvcfg support goes in. Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> Change-Id: I2d7b610698eca01b19a996bc80b0b08af4aed078 --- M src/arch/riscv/trap_handler.c M src/arch/riscv/virtual_memory.c M util/scripts/prepare-commit-msg.clang-format 3 files changed, 12 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/81306/1 diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index d66bed5..8bcb0968 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -132,16 +132,16 @@ int insn_size = 4; switch (insn) { - case 0xc0102773: // csrrs x14, time, x0 - tf->gpr[24] = *HLS()->time; - break; - case 0xc0102573: // csrrs x10, time, x0 - tf->gpr[20] = *HLS()->time; - break; - default: // proceed anyway. - printk(BIOS_EMERG, "Unhandled instruction: %x\n", insn); - print_trap_information(tf); - break; + case 0xc0102773: // csrrs x14, time, x0 + tf->gpr[24] = *HLS()->time; + break; + case 0xc0102573: // csrrs x10, time, x0 + tf->gpr[20] = *HLS()->time; + break; + default: // proceed anyway. + printk(BIOS_EMERG, "Unhandled instruction: %x\n", insn); + print_trap_information(tf); + break; } write_csr(mepc, read_csr(mepc) + insn_size); } @@ -157,7 +157,6 @@ case CAUSE_ILLEGAL_INSTRUCTION: ill(tf); return; - break; case CAUSE_MISALIGNED_FETCH: case CAUSE_FETCH_ACCESS: case CAUSE_BREAKPOINT: diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 913836f..6ff2171 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -45,7 +45,8 @@ // Delegate supervisor timer and other interrupts to supervisor mode, // if supervisor mode is supported. if (supports_extension('S')) { - if (ENV_RAMSTAGE && has_menvcfg) + /* this code depends on a later CL from Hug that adds menvcfg support. */ + if (0 && ENV_RAMSTAGE && has_menvcfg) delegate |= (1 << CAUSE_ILLEGAL_INSTRUCTION); set_csr(mideleg, MIP_STIP | MIP_SSIP); set_csr(medeleg, delegate); diff --git a/util/scripts/prepare-commit-msg.clang-format b/util/scripts/prepare-commit-msg.clang-format index a6b3d08..e1add3f 100755 --- a/util/scripts/prepare-commit-msg.clang-format +++ b/util/scripts/prepare-commit-msg.clang-format @@ -3,11 +3,3 @@ if [ -z "$files" ]; then exit 0 fi -# This has to be set here; otherwise a grep error seems to cause -# us to exit with non-zero status. -set -e -clang-format -i $files -git add $files -u=`git config user.name` -m="clang-formatted-by: $u" -echo $m >> $1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81306?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d7b610698eca01b19a996bc80b0b08af4aed078 Gerrit-Change-Number: 81306 Gerrit-PatchSet: 1 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
by ron minnich (Code Review) 18 Mar '24

18 Mar '24

ron minnich has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81305?usp=email ) Change subject: Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> ...................................................................... Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> Change-Id: I3ba80ca4f1e0cd7468065b29fd0d07eeff5ec9ed clang-formatted-by: Ronald G Minnich --- M src/arch/riscv/trap_handler.c M src/arch/riscv/virtual_memory.c 2 files changed, 50 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/81305/1 diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index f3968bb..d66bed5 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -111,6 +111,41 @@ void (*trap_handler)(struct trapframe *tf) = default_trap_handler; +/* + * ill is the bare minimum, very unsophisticated illegal instruction handler. + * It is deliberately dumb because, in the long term, we don't intend + * to use it very much. People have a way of latching on to functions like + * this and growing them without bound. The entire purpose of coreboot SBI + * is to provided the absolute minimum capability needed for modern + * RISC-V CPUs. + * Also, NOTE: C compilers are pretty smart about handling case + * statements. Do not assume, because this looks inefficient, that it is + * inefficient. For a very simple example, note that most compilers + * inline this function without being told to. + * Also, we COULD make this very general, but compilers seem to use + * only a small subset of possible variations, so that may not be + * worth it. + */ +static void ill(struct trapframe *tf) +{ + u32 insn = (u32) (tf->badvaddr); + int insn_size = 4; + + switch (insn) { + case 0xc0102773: // csrrs x14, time, x0 + tf->gpr[24] = *HLS()->time; + break; + case 0xc0102573: // csrrs x10, time, x0 + tf->gpr[20] = *HLS()->time; + break; + default: // proceed anyway. + printk(BIOS_EMERG, "Unhandled instruction: %x\n", insn); + print_trap_information(tf); + break; + } + write_csr(mepc, read_csr(mepc) + insn_size); +} + void default_trap_handler(struct trapframe *tf) { if (tf->cause & 0x8000000000000000ULL) { @@ -119,9 +154,12 @@ } switch (tf->cause) { + case CAUSE_ILLEGAL_INSTRUCTION: + ill(tf); + return; + break; case CAUSE_MISALIGNED_FETCH: case CAUSE_FETCH_ACCESS: - case CAUSE_ILLEGAL_INSTRUCTION: case CAUSE_BREAKPOINT: case CAUSE_LOAD_ACCESS: case CAUSE_STORE_ACCESS: diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 43e3d70..913836f 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -16,7 +16,6 @@ static int delegate = 0 | (1 << CAUSE_MISALIGNED_FETCH) | (1 << CAUSE_FETCH_ACCESS) - | (1 << CAUSE_ILLEGAL_INSTRUCTION) | (1 << CAUSE_BREAKPOINT) | (1 << CAUSE_LOAD_ACCESS) | (1 << CAUSE_STORE_ACCESS) @@ -24,10 +23,18 @@ | (1 << CAUSE_FETCH_PAGE_FAULT) | (1 << CAUSE_LOAD_PAGE_FAULT) | (1 << CAUSE_STORE_PAGE_FAULT) + /* + * This should only be enabled if we do NOT have menvcfg. + * The comment is left here to make sure nobody thinks it was + * left out by mistake. + * | (1 << CAUSE_ILLEGAL_INSTRUCTION) + */ ; void mstatus_init(void) { + extern uintptr_t has_menvcfg; + // clear any pending timer interrupts. clear_csr(mip, MIP_STIP | MIP_SSIP); @@ -38,10 +45,13 @@ // Delegate supervisor timer and other interrupts to supervisor mode, // if supervisor mode is supported. if (supports_extension('S')) { + if (ENV_RAMSTAGE && has_menvcfg) + delegate |= (1 << CAUSE_ILLEGAL_INSTRUCTION); set_csr(mideleg, MIP_STIP | MIP_SSIP); set_csr(medeleg, delegate); } // Enable all user/supervisor-mode counters write_csr(mcounteren, 7); + } -- To view, visit https://review.coreboot.org/c/coreboot/+/81305?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ba80ca4f1e0cd7468065b29fd0d07eeff5ec9ed Gerrit-Change-Number: 81305 Gerrit-PatchSet: 1 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: mb/intel/mtlrvp: Add Intel Touch driver for controller 0 and 1
by Cliff Huang (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Bora Guvendik, Kyoung Il Kim. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81335?usp=email ) Change subject: mb/intel/mtlrvp: Add Intel Touch driver for controller 0 and 1 ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/81335?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5433693973a21e90886c9075a23aaac84b2f642d Gerrit-Change-Number: 81335 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Comment-Date: Mon, 18 Mar 2024 17:52:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/rex: Add Intel Touch for controller 1 for Rex
by Cliff Huang (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jingyuan Liang, Kapil Porwal, Kyoung Il Kim, Subrata Banik, Tarun. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81333?usp=email ) Change subject: mb/google/rex: Add Intel Touch for controller 1 for Rex ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/81333?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id89b5b46d67b90491410d3d08c1a3ae9549b4da5 Gerrit-Change-Number: 81333 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 18 Mar 2024 17:51:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/meteorlake: Update Touch Controller UDP params
by Cliff Huang (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jingyuan Liang, Kapil Porwal, Kyoung Il Kim, Subrata Banik, Tarun. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81332?usp=email ) Change subject: soc/intel/meteorlake: Update Touch Controller UDP params ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/81332?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I19edbcad705e889166d7d340b2caa74ab3bf15a1 Gerrit-Change-Number: 81332 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 18 Mar 2024 17:50:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: drivers/intel/touch: Add driver for Intel Touch Controller and Devices
by Cliff Huang (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Eran Mitrani, Jingyuan Liang, Kyoung Il Kim. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81331?usp=email ) Change subject: drivers/intel/touch: Add driver for Intel Touch Controller and Devices ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/81331?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I52dfcd187c92141cb8fc47f4143b90d243439d4e Gerrit-Change-Number: 81331 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Comment-Date: Mon, 18 Mar 2024 17:49:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: include/device/pci_ids.h: Add DIDs for MTL Touch controller
by Cliff Huang (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Eran Mitrani, Jingyuan Liang, Kyoung Il Kim. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81330?usp=email ) Change subject: include/device/pci_ids.h: Add DIDs for MTL Touch controller ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/81330?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1b98fdbd8d8588492bcafa0f3998818dc83ff1d9 Gerrit-Change-Number: 81330 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Comment-Date: Mon, 18 Mar 2024 17:48:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit March 2024