coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

1 participants
3668 discussions

[XS] Change in coreboot[main]: cpu/x86/mtrr: Error out caching limitation during NEM
by Jérémy Compostella (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Stefan Reinauer, Subrata Banik. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81336?usp=email ) Change subject: cpu/x86/mtrr: Error out caching limitation during NEM ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81336?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4fbef1fcc018856420428139683897634c9f85d Gerrit-Change-Number: 81336 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Mar 2024 16:59:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: symbols: Add __maybe_unused flag to region variable symbols
by Jérémy Compostella (Code Review) 18 Mar '24

18 Mar '24

Jérémy Compostella has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81209?usp=email ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: symbols: Add __maybe_unused flag to region variable symbols ...................................................................... symbols: Add __maybe_unused flag to region variable symbols In DECLARE_REGION and DECLARE_OPTIONAL_REGION, a set of 3 variables will be defined, that is the region 'base', 'end' and 'size'. However, in many codes, the users will only selectively use 'end' or 'size' instead of both of them, which will trigger compiler errors for unused variables. This patch sets __maybe_unused attributes on 'end' and 'size' so that users do not need to use all of them. TEST=intel/archercity CRB Change-Id: Ia5ed183b2dd7a474ce51de47dbc1f9e3f61e5a41 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81209 Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/symbols.h 1 file changed, 6 insertions(+), 6 deletions(-) Approvals: Julius Werner: Looks good to me, approved Martin L Roth: Looks good to me, approved build bot (Jenkins): Verified Jérémy Compostella: Looks good to me, but someone else must approve diff --git a/src/include/symbols.h b/src/include/symbols.h index b1e44e11..ef23814 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -10,9 +10,9 @@ #define REGION_SIZE(name) ((size_t)_##name##_size) #define DECLARE_REGION(name) \ - extern u8 _##name[]; \ - extern u8 _e##name[]; \ - extern u8 _##name##_size[]; + __maybe_unused extern u8 _##name[]; \ + __maybe_unused extern u8 _e##name[]; \ + __maybe_unused extern u8 _##name##_size[]; /* * Regions can be declared optional if not all configurations provide them in @@ -23,9 +23,9 @@ * should then check (REGION_SIZE(name) != 0) before accessing it. */ #define DECLARE_OPTIONAL_REGION(name) \ - __weak extern u8 _##name[]; \ - __weak extern u8 _e##name[]; \ - __weak extern u8 _##name##_size[]; + __maybe_unused __weak extern u8 _##name[]; \ + __maybe_unused __weak extern u8 _e##name[]; \ + __maybe_unused __weak extern u8 _##name##_size[]; DECLARE_REGION(sram) DECLARE_OPTIONAL_REGION(timestamp) -- To view, visit https://review.coreboot.org/c/coreboot/+/81209?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5ed183b2dd7a474ce51de47dbc1f9e3f61e5a41 Gerrit-Change-Number: 81209 Gerrit-PatchSet: 6 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[main]: arch/x86: Directly return result of `IS_POWER_OF_2()`
by Jérémy Compostella (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Paul Menzel. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81299?usp=email ) Change subject: arch/x86: Directly return result of `IS_POWER_OF_2()` ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81299?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I314d726deaed30e69121126ba6834e4c7cafd090 Gerrit-Change-Number: 81299 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 18 Mar 2024 16:51:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: security/tpm: make tis_probe() return tpm_family
by Jérémy Compostella (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Christian Walter, Julius Werner, Martin L Roth, Sergii Dmytruk. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69159?usp=email ) Change subject: security/tpm: make tis_probe() return tpm_family ...................................................................... Patch Set 26: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69159?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5006e0cdfef76ff79ce9e1cf280fcd5515ae01b0 Gerrit-Change-Number: 69159 Gerrit-PatchSet: 26 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Mon, 18 Mar 2024 16:50:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: security/tpm: replace CONFIG(TPMx) checks with runtime check
by Jérémy Compostella (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Christian Walter, Cliff Huang, Jan Samek, Julius Werner, Krystian Hebel, Lance Zhao, Michał Żygowski, Sergii Dmytruk, Tim Wawrzynczak. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69161?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: security/tpm: replace CONFIG(TPMx) checks with runtime check ...................................................................... Patch Set 33: (1 comment) File src/security/tpm/tss.h: https://review.coreboot.org/c/coreboot/+/69161/comment/382c5f66_f8281882 : PS33, Line 45: else the use of the `else` keyword really is optional and it makes the code looks unnecessarily complicated IMHO. -- To view, visit https://review.coreboot.org/c/coreboot/+/69161?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id9cc25aad8d1d7bfad12b7a92059b1b3641bbfa9 Gerrit-Change-Number: 69161 Gerrit-PatchSet: 33 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jan Samek <jan.samek(a)siemens.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Mon, 18 Mar 2024 16:45:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Use DECLARE_REGION for FSP-M heap
by Jérémy Compostella (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Chen, Gang C, Felix Held, Julius Werner, Patrick Rudolph, Ronak Kanabar, Shuo Liu, Subrata Banik, Werner Zeh. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81097?usp=email ) Change subject: drivers/intel/fsp2_0: Use DECLARE_REGION for FSP-M heap ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81097?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5f7d7855592d99b074f7ef49c285a13f8105f089 Gerrit-Change-Number: 81097 Gerrit-PatchSet: 4 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 18 Mar 2024 16:36:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: soc/intel/xeon_sp/spr: Enable x86_64 support
by Jérémy Compostella (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Ray Ni, Shuo Liu, Tim Chu. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81280?usp=email ) Change subject: soc/intel/xeon_sp/spr: Enable x86_64 support ...................................................................... Patch Set 1: (2 comments) File src/soc/intel/xeon_sp/uncore_acpi.c: https://review.coreboot.org/c/coreboot/+/81280/comment/41f2c1c5_213af202 : PS1, Line 23: #include <stddef.h> alphabetical order. https://review.coreboot.org/c/coreboot/+/81280/comment/0bbc5820_4002a8f0 : PS1, Line 459: l > For size_t: `z`. But I don't understand the cast TBH. […] Shouldn't we just be using PRIxPTR ? -- To view, visit https://review.coreboot.org/c/coreboot/+/81280?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c5ed0339a9c2e9b088b16dbb4c19df98e796d65 Gerrit-Change-Number: 81280 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Ray Ni <ray.ni(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ray Ni <ray.ni(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 18 Mar 2024 16:34:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: arch/riscv: add constants for Base Extension
by ron minnich (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Arthur Heymans, Maximilian Brune, Philipp Hug. ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81286?usp=email ) Change subject: arch/riscv: add constants for Base Extension ...................................................................... Patch Set 2: (2 comments) File src/arch/riscv/include/sbi.h: https://review.coreboot.org/c/coreboot/+/81286/comment/54cd77d1_d890450d : PS1, Line 20: #define SBI_EXTENSION_ID 0x10 > I would change the name to SBI_BASE_EXTENSION (makes it more easy to find the appropriate place in t […] Done https://review.coreboot.org/c/coreboot/+/81286/comment/4c238dc1_c241ca97 : PS1, Line 20: define SBI_EXTENSION_ID 0x10 : #define SBI_GET_SBI_SPEC_VERSION 0 : #define SBI_GET_SBI_IMPL_ID 1 : #define SBI_GET_SBI_IMPL_VERSION 2 : #define SBI_PROBE_EXTENSION 3 : #define SBI_GET_MVENDORID 4 : #define SBI_GET_MARCHID 5 : #define SBI_GET_MIMPID 6 > maybe something like this: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81286?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaad763464678d1921dfefdbee1e39fba2fe5585a Gerrit-Change-Number: 81286 Gerrit-PatchSet: 2 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Mon, 18 Mar 2024 16:04:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: arch/riscv: add new SBI calls
by ron minnich (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Arthur Heymans, Maximilian Brune, Philipp Hug. Hello Arthur Heymans, Maximilian Brune, Philipp Hug, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81294?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: arch/riscv: add new SBI calls ...................................................................... arch/riscv: add new SBI calls This is just a start. We are playing catch up. 7 down, 70+ to go. Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> clang-formatted-by: Ronald G Minnich Change-Id: I5dac8613020e26ec74ac1c74158fc9791553693f --- M src/arch/riscv/sbi.c 1 file changed, 80 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/81294/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81294?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5dac8613020e26ec74ac1c74158fc9791553693f Gerrit-Change-Number: 81294 Gerrit-PatchSet: 2 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[main]: WIP: arch/riscv: add test to set variable for menvcfg
by ron minnich (Code Review) 18 Mar '24

18 Mar '24

Attention is currently required from: Arthur Heymans, Maximilian Brune, Philipp Hug. Hello Arthur Heymans, Maximilian Brune, Philipp Hug, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81293?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: WIP: arch/riscv: add test to set variable for menvcfg ...................................................................... WIP: arch/riscv: add test to set variable for menvcfg there are many variant features on SoCs. This CL demonstrates a simple way to test feature existence with low effort. It correctly detects the menvcfg register. Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> Change-Id: If9f5db74d7467ab00044d20050531bcb511cce39 --- M src/arch/riscv/include/arch/encoding.h M src/arch/riscv/payload.c M src/arch/riscv/ramstage.S 3 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/81293/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81293?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If9f5db74d7467ab00044d20050531bcb511cce39 Gerrit-Change-Number: 81293 Gerrit-PatchSet: 2 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2024