coreboot-gerrit January 2024

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[L] Change in coreboot[main]: mainboard: Drop redundant PciRpEnable from devicetrees
by Nicholas Sudsgaard (Code Review) 13 Jan '24

13 Jan '24

Nicholas Sudsgaard has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79935?usp=email ) Change subject: mainboard: Drop redundant PciRpEnable from devicetrees ...................................................................... mainboard: Drop redundant PciRpEnable from devicetrees This is the dirty work of the proposed changes: https://review.coreboot.org/c/coreboot/+/79921 (and related changes) This is still not complete, as I was not able to change some configurations. Specifically, the ones in intel/coffeelake_rvp/variants, as I do not know the PCIe addresses of some of the enabled root ports. I tried to be careful, but I cannot guarantee that I did not mess up any configurations. I would appreciate anyone who can put some time into double-checking these changes. Change-Id: I9641a1ed241084f37089094b2392c29e2ac0fd95 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/acer/aspire_vn7_572g/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/boxy/overridetree.cb M src/mainboard/google/dedede/variants/bugzzy/overridetree.cb M src/mainboard/google/dedede/variants/dexi/overridetree.cb M src/mainboard/google/dedede/variants/dibbi/overridetree.cb M src/mainboard/google/dedede/variants/dita/overridetree.cb M src/mainboard/google/dedede/variants/sasuke/overridetree.cb M src/mainboard/google/dedede/variants/sasukette/overridetree.cb M src/mainboard/google/dedede/variants/storo/overridetree.cb M src/mainboard/google/dedede/variants/taranza/overridetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/fizz/variants/endeavour/overridetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/helios/overridetree.cb M src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb M src/mainboard/google/hatch/variants/kohaku/overridetree.cb M src/mainboard/google/hatch/variants/mushu/overridetree.cb M src/mainboard/google/hatch/variants/nightfury/overridetree.cb M src/mainboard/google/hatch/variants/palkia/overridetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/google/puff/variants/ambassador/overridetree.cb M src/mainboard/google/puff/variants/baseboard/devicetree.cb M src/mainboard/google/puff/variants/dooly/overridetree.cb M src/mainboard/google/puff/variants/duffy/overridetree.cb M src/mainboard/google/puff/variants/faffy/overridetree.cb M src/mainboard/google/puff/variants/genesis/overridetree.cb M src/mainboard/google/puff/variants/kaisa/overridetree.cb M src/mainboard/google/puff/variants/moonbuggy/overridetree.cb M src/mainboard/google/puff/variants/noibat/overridetree.cb M src/mainboard/google/puff/variants/puff/overridetree.cb M src/mainboard/google/puff/variants/scout/overridetree.cb M src/mainboard/google/puff/variants/wyvern/overridetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/chronicler/overridetree.cb M src/mainboard/google/volteer/variants/elemi/overridetree.cb M src/mainboard/google/volteer/variants/voema/overridetree.cb M src/mainboard/hp/280_g2/devicetree.cb M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/kontron/bsl6/devicetree.cb M src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/prodrive/hermes/devicetree.cb M src/mainboard/protectli/vault_cml/devicetree.cb M src/mainboard/protectli/vault_ehl/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb M src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb M src/mainboard/purism/librem_jsl/devicetree.cb M src/mainboard/purism/librem_l1um_v2/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/siemens/chili/variants/base/devicetree.cb M src/mainboard/siemens/chili/variants/chili/devicetree.cb M src/mainboard/siemens/fa_ehl/variants/fa_ehl/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb M src/mainboard/starlabs/starbook/variants/cml/devicetree.cb M src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb M src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb M src/mainboard/system76/addw1/devicetree.cb M src/mainboard/system76/bonw14/devicetree.cb M src/mainboard/system76/cml-u/variants/darp6/overridetree.cb M src/mainboard/system76/cml-u/variants/galp4/overridetree.cb M src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb M src/mainboard/system76/gaze15/devicetree.cb M src/mainboard/system76/kbl-u/devicetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/mainboard/system76/oryp6/devicetree.cb M src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb M src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb M src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb M src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb M src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb M src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb M src/mainboard/system76/whl-u/devicetree.cb 105 files changed, 57 insertions(+), 485 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/79935/1 diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 2695451..c630143 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -55,22 +55,21 @@ register "serirq_mode" = "SERIRQ_CONTINUOUS" - # Enable Root Ports 3, 4 and 9 - register "PcieRpEnable[2]" = "1" # Ethernet controller + # Ethernet controller register "PcieRpClkReqSupport[2]" = "1" register "PcieRpClkReqNumber[2]" = "0" register "PcieRpClkSrcNumber[2]" = "0" register "PcieRpAdvancedErrorReporting[2]" = "1" register "PcieRpLtrEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" # Wireless controller + # Wireless controller register "PcieRpClkReqSupport[3]" = "1" register "PcieRpClkReqNumber[3]" = "1" register "PcieRpClkSrcNumber[3]" = "1" register "PcieRpAdvancedErrorReporting[3]" = "1" register "PcieRpLtrEnable[3]" = "1" - register "PcieRpEnable[8]" = "1" # NVMe controller + # NVMe controller register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "4" register "PcieRpClkSrcNumber[8]" = "4" diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb index 0328ec7..f0d7a4f 100644 --- a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb +++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb @@ -253,7 +253,6 @@ # Board has no GPIO expander on I2C4 (despite SetupUtility claim that it does - this would be static text) device ref pcie_rp1 on # dGPU; x4 - register "PcieRpEnable[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpLtrEnable[0]" = "1" register "PcieRpClkReqSupport[0]" = "1" @@ -262,7 +261,6 @@ end device ref pcie_rp7 on # NGFF; x2 - register "PcieRpEnable[6]" = "1" register "PcieRpAdvancedErrorReporting[6]" = "1" register "PcieRpLtrEnable[6]" = "1" register "PcieRpClkReqSupport[6]" = "1" @@ -271,7 +269,6 @@ end device ref pcie_rp9 on # LAN - register "PcieRpEnable[8]" = "1" register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" @@ -280,7 +277,6 @@ end device ref pcie_rp10 on # WLAN - register "PcieRpEnable[9]" = "1" register "PcieRpAdvancedErrorReporting[9]" = "1" register "PcieRpLtrEnable[9]" = "1" register "PcieRpClkReqSupport[9]" = "1" diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index a6d16f9..63a1f8f 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -114,7 +114,6 @@ end device ref pcie_rp1 on end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "1" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "2" register "PcieRpAdvancedErrorReporting[4]" = "1" @@ -123,7 +122,6 @@ register "PcieRpHotPlug[4]" = "1" end device ref pcie_rp6 on - register "PcieRpEnable[5]" = "1" # Disable CLKREQ#, since onboard LAN is always present register "PcieRpClkReqSupport[5]" = "0" @@ -132,7 +130,6 @@ register "PcieRpClkSrcNumber[5]" = "1" end device ref pcie_rp7 on - register "PcieRpEnable[6]" = "1" register "PcieRpClkReqSupport[6]" = "1" register "PcieRpClkReqNumber[6]" = "3" register "PcieRpAdvancedErrorReporting[6]" = "1" diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index a98d144..b8e179f 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -137,7 +137,6 @@ device pci 1c.4 off end # PCI Express Port 5 device pci 1c.5 on # PCI Express Port 6 device pci 00.0 on end # x1 Card reader - register "PcieRpEnable[5]" = "1" register "PcieRpLtrEnable[5]" = "1" register "PcieClkSrcUsage[3]" = "5" register "PcieClkSrcClkReq[3]" = "3" @@ -147,7 +146,6 @@ chip drivers/wifi/generic device pci 00.0 on end end - register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[2]" = "7" register "PcieClkSrcClkReq[2]" = "2" @@ -155,7 +153,6 @@ smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" end device pci 1d.0 on # PCI Express Port 9 - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[4]" = "8" register "PcieClkSrcClkReq[4]" = "4" @@ -166,7 +163,6 @@ device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on # PCI Express Port 13 - register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[5]" = "12" register "PcieClkSrcClkReq[5]" = "5" diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index 765d17c..c0b7dd4 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -69,7 +69,6 @@ device ref uart2 on end device ref pcie_rp1 on device pci 00.0 on end # x4 TBT - register "PcieRpEnable[0]" = "1" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "4" register "PcieRpClkSrcNumber[0]" = "4" @@ -79,7 +78,6 @@ end device ref pcie_rp5 on device pci 00.0 on end # x1 LAN - register "PcieRpEnable[4]" = "1" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" @@ -87,7 +85,6 @@ end device ref pcie_rp6 on device pci 00.0 on end # x1 WLAN - register "PcieRpEnable[5]" = "1" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "2" register "PcieRpClkSrcNumber[5]" = "2" @@ -96,7 +93,6 @@ end device ref pcie_rp9 on device pci 00.0 on end # x4 M.2/M (J_SSD1) - register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "5" register "PcieRpClkSrcNumber[8]" = "5" diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb b/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb index 73f32e3..0131e21 100644 --- a/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb @@ -154,7 +154,6 @@ end end device ref pcie_rp3 on - register "PcieRpEnable[2]" = "true" register "PcieRpLtrEnable[2]" = "true" register "PcieClkSrcUsage[1]" = "2" register "PcieClkSrcClkReq[1]" = "1" @@ -167,14 +166,12 @@ device ref pcie_rp6 on # Card reader device pci 00.0 on end - register "PcieRpEnable[5]" = "true" register "PcieRpLtrEnable[5]" = "true" register "PcieClkSrcUsage[2]" = "5" register "PcieClkSrcClkReq[2]" = "2" end device ref pcie_rp9 on # SSD2 - PCIe mode - register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0" diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 3f71ca9..4ea8530 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -136,7 +136,6 @@ # PCIE Port 2 disabled # PCIE Port 3 x1 -> Module x1 : Mapped to PCIe 2 on the baseboard - register "PcieRpEnable[2]" = "1" # Disable CLKREQ# register "PcieRpClkReqSupport[2]" = "0" # Set MaxPayload to 256 bytes @@ -152,7 +151,6 @@ # PCIE Port 5 x1 -> MODULE i219 # PCIE Port 6 x1 -> BASEBOARD x1 i210 : Mapped to PCIe 4 on the baseboard - register "PcieRpEnable[5]" = "1" register "PcieRpClkReqSupport[5]" = "0" # Set MaxPayload to 256 bytes register "PcieRpMaxPayload[5]" = "RpMaxPayload_256" @@ -167,7 +165,6 @@ # PCIE Port 8 Disabled # PCIE Port 9 x4 -> BASEBOARD PEG0-3 FPGA - register "PcieRpEnable[8]" = "1" # Disable CLKREQ# register "PcieRpClkReqSupport[8]" = "0" # Use Hot Plug subsystem diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 2631b61..47ac5ce 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -107,17 +107,6 @@ [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }" - # PCIE Root Port Configuration - register "PcieRpEnable[0]" = "0" - register "PcieRpEnable[1]" = "0" - register "PcieRpEnable[2]" = "0" - register "PcieRpEnable[3]" = "0" - register "PcieRpEnable[4]" = "0" - register "PcieRpEnable[5]" = "0" - register "PcieRpEnable[6]" = "0" - # PCIe Root Port 8 (index 7) hosts M.2 E-key WLAN. - register "PcieRpEnable[7]" = "1" - register "PcieClkSrcUsage[0]" = "0xff" register "PcieClkSrcUsage[1]" = "0xff" register "PcieClkSrcUsage[2]" = "0xff" diff --git a/src/mainboard/google/dedede/variants/boxy/overridetree.cb b/src/mainboard/google/dedede/variants/boxy/overridetree.cb index ab6fc16..36eadcb 100644 --- a/src/mainboard/google/dedede/variants/boxy/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boxy/overridetree.cb @@ -46,19 +46,14 @@ .tdp_pl4 = 60, }" - # Enable Root Port 3 (index 2) for LAN + # Root Port 3 (index 2) for LAN # External PCIe port 7 is mapped to PCIe Root Port 3 - register "PcieRpEnable[2]" = "1" register "PcieClkSrcUsage[4]" = "2" - # Enable Root Port 7 (index 6) for WLAN + # Root Port 7 (index 6) for WLAN # External PCIe port 3 is mapped to PCIe Root Port 7 - register "PcieRpEnable[6]" = "1" register "PcieClkSrcUsage[3]" = "6" - # Disable PCIe Root Port 8 - register "PcieRpEnable[7]" = "0" - # Audio related configurations register "PchHdaAudioLinkDmicEnable[0]" = "0" register "PchHdaAudioLinkDmicEnable[1]" = "0" diff --git a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb index e7f2562..6a20938 100644 --- a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb +++ b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb @@ -8,8 +8,6 @@ register "SlowSlewRate" = "SlewRateFastBy8" register "FastPkgCRampDisable" = "1" - # Disable PCIe Root Port 8 (index 7) - register "PcieRpEnable[7]" = "0" # Disable PCIe Clock Source 4 (index 3) register "PcieClkSrcUsage[3]" = "0xff" diff --git a/src/mainboard/google/dedede/variants/dexi/overridetree.cb b/src/mainboard/google/dedede/variants/dexi/overridetree.cb index 2b09088..f53a11a 100644 --- a/src/mainboard/google/dedede/variants/dexi/overridetree.cb +++ b/src/mainboard/google/dedede/variants/dexi/overridetree.cb @@ -38,19 +38,14 @@ .tdp_pl4 = 60, }" - # Enable Root Port 3 (index 2) for LAN + # Root Port 3 (index 2) for LAN # External PCIe port 7 is mapped to PCIe Root Port 3 - register "PcieRpEnable[2]" = "1" register "PcieClkSrcUsage[4]" = "2" - # Enable Root Port 7 (index 6) for WLAN + # Root Port 7 (index 6) for WLAN # External PCIe port 3 is mapped to PCIe Root Port 7 - register "PcieRpEnable[6]" = "1" register "PcieClkSrcUsage[3]" = "6" - # Disable PCIe Root Port 8 - register "PcieRpEnable[7]" = "0" - # Audio related configurations register "PchHdaAudioLinkDmicEnable[0]" = "0" register "PchHdaAudioLinkDmicEnable[1]" = "0" diff --git a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb index 5bc127d..c7d6afb 100644 --- a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb +++ b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb @@ -38,19 +38,14 @@ .tdp_pl4 = 60, }" - # Enable Root Port 3 (index 2) for LAN + # Root Port 3 (index 2) for LAN # External PCIe port 7 is mapped to PCIe Root Port 3 - register "PcieRpEnable[2]" = "1" register "PcieClkSrcUsage[4]" = "2" - # Enable Root Port 7 (index 6) for WLAN + # Root Port 7 (index 6) for WLAN # External PCIe port 3 is mapped to PCIe Root Port 7 - register "PcieRpEnable[6]" = "1" register "PcieClkSrcUsage[3]" = "6" - # Disable PCIe Root Port 8 - register "PcieRpEnable[7]" = "0" - # Audio related configurations register "PchHdaAudioLinkDmicEnable[0]" = "0" register "PchHdaAudioLinkDmicEnable[1]" = "0" diff --git a/src/mainboard/google/dedede/variants/dita/overridetree.cb b/src/mainboard/google/dedede/variants/dita/overridetree.cb index 2b09088..f53a11a 100644 --- a/src/mainboard/google/dedede/variants/dita/overridetree.cb +++ b/src/mainboard/google/dedede/variants/dita/overridetree.cb @@ -38,19 +38,14 @@ .tdp_pl4 = 60, }" - # Enable Root Port 3 (index 2) for LAN + # Root Port 3 (index 2) for LAN # External PCIe port 7 is mapped to PCIe Root Port 3 - register "PcieRpEnable[2]" = "1" register "PcieClkSrcUsage[4]" = "2" - # Enable Root Port 7 (index 6) for WLAN + # Root Port 7 (index 6) for WLAN # External PCIe port 3 is mapped to PCIe Root Port 7 - register "PcieRpEnable[6]" = "1" register "PcieClkSrcUsage[3]" = "6" - # Disable PCIe Root Port 8 - register "PcieRpEnable[7]" = "0" - # Audio related configurations register "PchHdaAudioLinkDmicEnable[0]" = "0" register "PchHdaAudioLinkDmicEnable[1]" = "0" diff --git a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb index ce816e5..dcd5cbb 100644 --- a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb @@ -1,6 +1,4 @@ chip soc/intel/jasperlake - # Disable PCIe Root Port 8 (index 7) - register "PcieRpEnable[7]" = "0" # Disable PCIe Clock Source 4 (index 3) register "PcieClkSrcUsage[3]" = "0xff" diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb index 5e4de2a..23c0a2a 100644 --- a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb @@ -8,8 +8,6 @@ end chip soc/intel/jasperlake - # Disable PCIe Root Port 8 (index 7) - register "PcieRpEnable[7]" = "0" # Disable PCIe Clock Source 4 (index 3) register "PcieClkSrcUsage[3]" = "0xff" diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb index 1aa2e71..dce6986 100644 --- a/src/mainboard/google/dedede/variants/storo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb @@ -7,8 +7,6 @@ end chip soc/intel/jasperlake - # Disable PCIe Root Port 8 (index 7) - register "PcieRpEnable[7]" = "0" # Disable PCIe Clock Source 4 (index 3) register "PcieClkSrcUsage[3]" = "0xff" diff --git a/src/mainboard/google/dedede/variants/taranza/overridetree.cb b/src/mainboard/google/dedede/variants/taranza/overridetree.cb index 2b09088..f53a11a 100644 --- a/src/mainboard/google/dedede/variants/taranza/overridetree.cb +++ b/src/mainboard/google/dedede/variants/taranza/overridetree.cb @@ -38,19 +38,14 @@ .tdp_pl4 = 60, }" - # Enable Root Port 3 (index 2) for LAN + # Root Port 3 (index 2) for LAN # External PCIe port 7 is mapped to PCIe Root Port 3 - register "PcieRpEnable[2]" = "1" register "PcieClkSrcUsage[4]" = "2" - # Enable Root Port 7 (index 6) for WLAN + # Root Port 7 (index 6) for WLAN # External PCIe port 3 is mapped to PCIe Root Port 7 - register "PcieRpEnable[6]" = "1" register "PcieClkSrcUsage[3]" = "6" - # Disable PCIe Root Port 8 - register "PcieRpEnable[7]" = "0" - # Audio related configurations register "PchHdaAudioLinkDmicEnable[0]" = "0" register "PchHdaAudioLinkDmicEnable[1]" = "0" diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 950dab9..392b558 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -193,13 +193,11 @@ }" # PCIe port 9 for Card Reader - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[4]" = "8" register "PcieClkSrcClkReq[4]" = "4" # PCIe port 13 for M.2 2280 SSD - register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[2]" = "12" register "PcieClkSrcClkReq[2]" = "2" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index dfa7a6e..ffe01a3 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -125,8 +125,7 @@ .dc_loadline = 430, }" - # Enable Root port 1 with SRCCLKREQ1# - register "PcieRpEnable[0]" = "1" + # Root port 1 with SRCCLKREQ1# register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" @@ -135,8 +134,7 @@ #RP 1 uses CLK SRC 1 register "PcieRpClkSrcNumber[0]" = "1" - # Enable Root port 5 with SRCCLKREQ4# - register "PcieRpEnable[4]" = "1" + # Root port 5 with SRCCLKREQ4# register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "4" register "PcieRpAdvancedErrorReporting[4]" = "1" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 44fc014..b4a5bdf 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -158,8 +158,7 @@ .dc_loadline = 310, }" - # Enable Root port 3(x1) for LAN. - register "PcieRpEnable[2]" = "1" + # Root port 3(x1) for LAN. # Enable CLKREQ# register "PcieRpClkReqSupport[2]" = "1" # RP 3 uses SRCCLKREQ0# @@ -171,8 +170,7 @@ # RP 3 uses CLK SRC 0 register "PcieRpClkSrcNumber[2]" = "0" - # Enable Root port 4(x1) for WLAN. - register "PcieRpEnable[3]" = "1" + # Root port 4(x1) for WLAN. # Enable CLKREQ# register "PcieRpClkReqSupport[3]" = "1" # RP 4 uses SRCCLKREQ5# @@ -184,8 +182,7 @@ # RP 4 uses CLK SRC 5 register "PcieRpClkSrcNumber[3]" = "5" - # Enable Root port 5(x4) for NVMe. - register "PcieRpEnable[4]" = "1" + # Root port 5(x4) for NVMe. # Enable CLKREQ# register "PcieRpClkReqSupport[4]" = "1" # RP 5 uses SRCCLKREQ1# @@ -197,8 +194,7 @@ # RP 5 uses CLK SRC 1 register "PcieRpClkSrcNumber[4]" = "1" - # Enable Root port 9 for BtoB. - register "PcieRpEnable[8]" = "1" + # Root port 9 for BtoB. # Enable CLKREQ# register "PcieRpClkReqSupport[8]" = "1" # RP 9 uses SRCCLKREQ2# @@ -210,8 +206,7 @@ # RP 9 uses CLK SRC 2 register "PcieRpClkSrcNumber[8]" = "2" - # Enable Root port 11 for BtoB. - register "PcieRpEnable[10]" = "1" + # Root port 11 for BtoB. # Enable CLKREQ# register "PcieRpClkReqSupport[10]" = "1" # RP 11 uses SRCCLKREQ2# @@ -223,8 +218,7 @@ # RP 11 uses CLK SRC 2 register "PcieRpClkSrcNumber[10]" = "2" - # Enable Root port 12 for BtoB. - register "PcieRpEnable[11]" = "1" + # Root port 12 for BtoB. # Enable CLKREQ# register "PcieRpClkReqSupport[11]" = "1" # RP 12 uses SRCCLKREQ2# diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb index 989b2406..80dd07f 100644 --- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb +++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb @@ -1,7 +1,6 @@ chip soc/intel/skylake - # Enable Root port 7(x1) for TPU1 - register "PcieRpEnable[6]" = "1" + # Root port 7(x1) for TPU1 # Enable CLKREQ# register "PcieRpClkReqSupport[6]" = "1" # RP 7 uses SRCCLKREQ4# @@ -13,8 +12,7 @@ # RP 7 uses CLK SRC 4 register "PcieRpClkSrcNumber[6]" = "4" - # Enable Root port 8(x1) for TPU0 - register "PcieRpEnable[7]" = "1" + # Root port 8(x1) for TPU0 # Enable CLKREQ# register "PcieRpClkReqSupport[7]" = "1" # RP 8 uses SRCCLKREQ2# @@ -26,8 +24,7 @@ # RP 8 uses CLK SRC 2 register "PcieRpClkSrcNumber[7]" = "2" - # Enable Root port 9(x4) for i350 LAN - register "PcieRpEnable[8]" = "1" + # Root port 9(x4) for i350 LAN # Disable CLKREQ# register "PcieRpClkReqSupport[8]" = "0" # RP 9, Enable Advanced Error Reporting @@ -37,11 +34,6 @@ # RP 9 uses CLK SRC 2 register "PcieRpClkSrcNumber[8]" = "2" - # These are part of Root port 9(x4) - register "PcieRpEnable[9]" = "0" - register "PcieRpEnable[10]" = "0" - register "PcieRpEnable[11]" = "0" - register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)" # Type-C register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # HDMI register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Rear diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 58b421c..92f251e 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -48,8 +48,7 @@ register "PmConfigSlpSusMinAssert" = "3" # 4s register "PmConfigSlpAMinAssert" = "3" # 2s - # Enable Root port 1 - register "PcieRpEnable[0]" = "1" + # Root port 1 # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" # RP 1 uses SRCCLKREQ1# diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index c4679e3..0e2c81f 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -161,8 +161,7 @@ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 1 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN - # Enable Root port 9(x4) for NVMe. - register "PcieRpEnable[8]" = "1" + # Root port 9(x4) for NVMe. register "PcieRpLtrEnable[8]" = "1" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" @@ -170,7 +169,6 @@ register "PcieClkSrcClkReq[1]" = "1" # PCIe port 14 for M.2 E-key WLAN - register "PcieRpEnable[13]" = "1" register "PcieRpLtrEnable[13]" = "1" # RP 14 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "13" diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index 3a624d9..d634096 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -19,9 +19,6 @@ [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" - # No PCIe WiFi - register "PcieRpEnable[13]" = "0" - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -176,6 +173,7 @@ device i2c 3b on end end end #I2C #4 + device ref pcie_rp14 off end # No PCIe Wifi device ref gspi1 on chip drivers/spi/acpi register "name" = ""CRFP"" diff --git a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb index 691e51f..9037c85 100644 --- a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb @@ -19,25 +19,20 @@ [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" - # Enable Root port 9(x2) for NVMe. - register "PcieRpEnable[8]" = "1" + # Root port 9(x2) for NVMe. register "PcieRpLtrEnable[8]" = "1" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" # ClkReq-to-ClkSrc mapping for CLK SRC 1 register "PcieClkSrcClkReq[1]" = "1" - # Enable Root port 11(x2) for NVMe. - register "PcieRpEnable[10]" = "1" + # Root port 11(x2) for NVMe. register "PcieRpLtrEnable[10]" = "1" # RP 11 uses CLK SRC 2 register "PcieClkSrcUsage[2]" = "10" # ClkReq-to-ClkSrc mapping for CLK SRC 2 register "PcieClkSrcClkReq[2]" = "1" - # No PCIe WiFi - register "PcieRpEnable[13]" = "0" - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -184,8 +179,9 @@ device i2c 3b on end end end #I2C #4 - device ref pcie_rp9 on end # (x2 NVMe) - device ref pcie_rp11 on end # (x2 NVMe) + device ref pcie_rp9 on end # (x2 NVMe) + device ref pcie_rp11 on end # (x2 NVMe) + device ref pcie_rp14 off end # No PCIe Wifi device ref gspi1 on chip drivers/spi/acpi register "name" = ""CRFP"" diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 67f5238..2f843e7 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -19,9 +19,6 @@ [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" - # No PCIe WiFi - register "PcieRpEnable[13]" = "0" - # Enable DMIC1 register "PchHdaAudioLinkDmic1" = "1" @@ -211,7 +208,7 @@ device i2c 0x1a on end end end - # No PCIe WiFi + # No PCIe Wifi device ref pcie_rp14 off end device ref gspi1 on chip drivers/spi/acpi diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb index 0424da2..df11957 100644 --- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -71,14 +71,12 @@ }" # PCIe port 7 for M.2 E-key WLAN - register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" # RP 7 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "6" register "PcieClkSrcClkReq[3]" = "3" - # Enable Root port 13 (x4) for dGPU - register "PcieRpEnable[12]" = "1" + # Root port 13 (x4) for dGPU register "PcieRpLtrEnable[12]" = "1" # RP 13 uses CLK SRC 5 register "PcieClkSrcUsage[5]" = "12" diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb index b1df825..aeeb1bf 100644 --- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -19,9 +19,6 @@ [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" - # No PCIe WiFi - register "PcieRpEnable[13]" = "0" - # Enable DMIC1 register "PchHdaAudioLinkDmic1" = "1" @@ -219,8 +216,7 @@ device i2c 0x39 on end end end - # No PCIe WiFi - device ref pcie_rp14 off end + device ref pcie_rp14 off end # No PCIe WiFi device ref emmc on end device ref hda on chip drivers/sof diff --git a/src/mainboard/google/hatch/variants/palkia/overridetree.cb b/src/mainboard/google/hatch/variants/palkia/overridetree.cb index bac387d..7fca6cc 100644 --- a/src/mainboard/google/hatch/variants/palkia/overridetree.cb +++ b/src/mainboard/google/hatch/variants/palkia/overridetree.cb @@ -22,9 +22,6 @@ register "usb2_ports[2]" = "USB2_PORT_LONG(OC_SKIP)" # SD CARD register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD CARD - # No PCIe WiFi - register "PcieRpEnable[13]" = "0" - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -175,6 +172,7 @@ device i2c 39 on end end end + device ref pcie_rp14 off end # No PCIe Wifi device ref hda on chip drivers/generic/max98357a register "hid" = ""MX98357A"" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 4ba644f..72b002d 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -136,7 +136,6 @@ }" # PCIe Root port 1 with SRCCLKREQ1# (WLAN) - register "PcieRpEnable[0]" = "1" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 717ab54..37646e3 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -120,8 +120,7 @@ .dc_loadline = 420, }" - # Enable Root port 1. - register "PcieRpEnable[0]" = "1" + # Root port 1. # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" # RP 1 uses SRCCLKREQ1# diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index d1d0441..f9de618 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -128,13 +128,11 @@ }" # Root port 4 (x1) - # PcieRpEnable: Enable root port # PcieRpClkReqSupport: Enable CLKREQ# # PcieRpClkReqNumber: Uses SRCCLKREQ1# # PcieRpClkSrcNumber: Uses 1 # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism - register "PcieRpEnable[3]" = "1" register "PcieRpClkReqSupport[3]" = "1" register "PcieRpClkReqNumber[3]" = "1" register "PcieRpClkSrcNumber[3]" = "1" @@ -142,13 +140,11 @@ register "PcieRpLtrEnable[3]" = "1" # Root port 5 (x4) - # PcieRpEnable: Enable root port # PcieRpClkReqSupport: Enable CLKREQ# # PcieRpClkReqNumber: Uses SRCCLKREQ3# # PcieRpClkSrcNumber: Uses 3 # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism - register "PcieRpEnable[4]" = "1" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" @@ -156,13 +152,11 @@ register "PcieRpLtrEnable[4]" = "1" # Root port 9 (x2) - # PcieRpEnable: Enable root port # PcieRpClkReqSupport: Enable CLKREQ# # PcieRpClkReqNumber: Uses SRCCLKREQ2# # PcieRpClkSrcNumber: Uses 2 # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism - register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "2" register "PcieRpClkSrcNumber[8]" = "2" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 6cc1f8e..7c10885 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -138,8 +138,7 @@ .dc_loadline = 420, }" - # Enable Root port 1. - register "PcieRpEnable[0]" = "1" + # Root port 1. # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" # RP 1 uses SRCCLKREQ1# diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 5f322b1..3dc95d6 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -129,7 +129,6 @@ }" # PCIe Root port 1 with SRCCLKREQ1# - register "PcieRpEnable[0]" = "1" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" @@ -137,13 +136,11 @@ register "PcieRpLtrEnable[0]" = "1" # Root port 9 (x2) - # PcieRpEnable: Enable root port # PcieRpClkReqSupport: Enable CLKREQ# # PcieRpClkReqNumber: Uses SRCCLKREQ2# # PcieRpClkSrcNumber: Uses 3 # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism - register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "2" register "PcieRpClkSrcNumber[8]" = "3" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 8a3d4fd..ee13781 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -127,8 +127,7 @@ .dc_loadline = 430, }" - # Enable Root port 1. - register "PcieRpEnable[0]" = "1" + # Root port 1. # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" # RP 1 uses SRCCLKREQ1# diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index db79337..6c1b91f 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -129,8 +129,7 @@ .dc_loadline = 420, }" - # Enable Root port 1. - register "PcieRpEnable[0]" = "1" + # Root port 1. # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" # RP 1 uses SRCCLKREQ1# diff --git a/src/mainboard/google/puff/variants/ambassador/overridetree.cb b/src/mainboard/google/puff/variants/ambassador/overridetree.cb index 8b6a9ae..a61039d 100644 --- a/src/mainboard/google/puff/variants/ambassador/overridetree.cb +++ b/src/mainboard/google/puff/variants/ambassador/overridetree.cb @@ -190,10 +190,8 @@ }" # PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb index b7a9674..d351f31 100644 --- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -161,8 +161,7 @@ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 1 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN - # Enable Root port 9(x4) for NVMe. - register "PcieRpEnable[8]" = "1" + # Root port 9(x4) for NVMe. register "PcieRpLtrEnable[8]" = "1" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" @@ -170,7 +169,6 @@ register "PcieClkSrcClkReq[1]" = "1" # PCIe port 14 for M.2 E-key WLAN - register "PcieRpEnable[13]" = "1" register "PcieRpLtrEnable[13]" = "1" # RP 14 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "13" diff --git a/src/mainboard/google/puff/variants/dooly/overridetree.cb b/src/mainboard/google/puff/variants/dooly/overridetree.cb index 78324ed..ea04a77 100644 --- a/src/mainboard/google/puff/variants/dooly/overridetree.cb +++ b/src/mainboard/google/puff/variants/dooly/overridetree.cb @@ -173,7 +173,6 @@ }" # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" diff --git a/src/mainboard/google/puff/variants/duffy/overridetree.cb b/src/mainboard/google/puff/variants/duffy/overridetree.cb index b1c50a2..6123f9f 100644 --- a/src/mainboard/google/puff/variants/duffy/overridetree.cb +++ b/src/mainboard/google/puff/variants/duffy/overridetree.cb @@ -251,10 +251,8 @@ }" # PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" diff --git a/src/mainboard/google/puff/variants/faffy/overridetree.cb b/src/mainboard/google/puff/variants/faffy/overridetree.cb index 83f0c16..6c6a948 100644 --- a/src/mainboard/google/puff/variants/faffy/overridetree.cb +++ b/src/mainboard/google/puff/variants/faffy/overridetree.cb @@ -259,10 +259,8 @@ }" # PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" diff --git a/src/mainboard/google/puff/variants/genesis/overridetree.cb b/src/mainboard/google/puff/variants/genesis/overridetree.cb index 6458f9f..1f3ea68 100644 --- a/src/mainboard/google/puff/variants/genesis/overridetree.cb +++ b/src/mainboard/google/puff/variants/genesis/overridetree.cb @@ -183,45 +183,36 @@ }" # PCIe root port 7 for LAN - register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" # PCIe root port 8 for WLAN - register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" # Uses CLK SRC 5 register "PcieClkSrcUsage[5]" = "7" register "PcieClkSrcClkReq[5]" = "5" # PCIe root port 9 for SSD (PCIe Lanes 11, 12) - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" register "PcieClkSrcClkReq[1]" = "1" - # PCIe root port 10 disabled - register "PcieRpEnable[9]" = "0" - # PCIe root port 11 TPU1 - register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" # RP 11 uses CLK SRC 1 register "PcieClkSrcUsage[4]" = "10" register "PcieClkSrcClkReq[4]" = "4" # PCIe root port 12 TPU0 - register "PcieRpEnable[11]" = "1" register "PcieRpLtrEnable[11]" = "1" # RP 11 uses CLK SRC 1 register "PcieClkSrcUsage[2]" = "11" register "PcieClkSrcClkReq[2]" = "2" # PCIe port 13 for i350 NIC (x4) - register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" # RP 13 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "12" @@ -229,10 +220,6 @@ # NOTE: Any value other than a valid source-clock-request (0-5) is # effectively "not connected" register "PcieClkSrcClkReq[3]" = "0xFF" - # Disable the remaining ports 14-16 - register "PcieRpEnable[13]" = "0" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" # GPIO for SD card detect register "sdcard_cd_gpio" = "vSD3_CD_B" diff --git a/src/mainboard/google/puff/variants/kaisa/overridetree.cb b/src/mainboard/google/puff/variants/kaisa/overridetree.cb index 6a2dd7b..24c8cc0 100644 --- a/src/mainboard/google/puff/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/puff/variants/kaisa/overridetree.cb @@ -251,10 +251,8 @@ }" # PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" diff --git a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb index a89c56d..4d179da 100644 --- a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb +++ b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb @@ -183,45 +183,36 @@ }" # PCIe root port 7 for LAN - register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" # PCIe root port 8 for WLAN - register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" # Uses CLK SRC 5 register "PcieClkSrcUsage[5]" = "7" register "PcieClkSrcClkReq[5]" = "5" # PCIe root port 9 for SSD (PCIe Lanes 11, 12) - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" register "PcieClkSrcClkReq[1]" = "1" - # PCIe root port 10 disabled - register "PcieRpEnable[9]" = "0" - # PCIe root port 11 TPU1 - register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" # RP 11 uses CLK SRC 1 register "PcieClkSrcUsage[4]" = "10" register "PcieClkSrcClkReq[4]" = "4" # PCIe root port 12 TPU0 - register "PcieRpEnable[11]" = "1" register "PcieRpLtrEnable[11]" = "1" # RP 11 uses CLK SRC 1 register "PcieClkSrcUsage[2]" = "11" register "PcieClkSrcClkReq[2]" = "2" # PCIe port 13 for i350 NIC (x4) - register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" # RP 13 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "12" @@ -229,10 +220,6 @@ # NOTE: Any value other than a valid source-clock-request (0-5) is # effectively "not connected" register "PcieClkSrcClkReq[3]" = "0xFF" - # Disable the remaining ports 14-16 - register "PcieRpEnable[13]" = "0" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" # GPIO for SD card detect register "sdcard_cd_gpio" = "vSD3_CD_B" diff --git a/src/mainboard/google/puff/variants/noibat/overridetree.cb b/src/mainboard/google/puff/variants/noibat/overridetree.cb index 91a19397..586c82c 100644 --- a/src/mainboard/google/puff/variants/noibat/overridetree.cb +++ b/src/mainboard/google/puff/variants/noibat/overridetree.cb @@ -174,10 +174,8 @@ }" # PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" diff --git a/src/mainboard/google/puff/variants/puff/overridetree.cb b/src/mainboard/google/puff/variants/puff/overridetree.cb index 3cd6a01..913581b 100644 --- a/src/mainboard/google/puff/variants/puff/overridetree.cb +++ b/src/mainboard/google/puff/variants/puff/overridetree.cb @@ -184,10 +184,8 @@ }" # PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" diff --git a/src/mainboard/google/puff/variants/scout/overridetree.cb b/src/mainboard/google/puff/variants/scout/overridetree.cb index 5462e9b..e7bc6f1 100644 --- a/src/mainboard/google/puff/variants/scout/overridetree.cb +++ b/src/mainboard/google/puff/variants/scout/overridetree.cb @@ -184,48 +184,35 @@ }" # PCIe root port 7 for LAN - register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" # PCIe root port 8 for WLAN - register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" # Uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcClkReq[3]" = "3" # PCIe root port 9 for SSD (PCIe Lanes 9-12) - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" register "PcieClkSrcClkReq[1]" = "1" - # PCIe root port 10-12 disabled - register "PcieRpEnable[9]" = "0" - register "PcieRpEnable[10]" = "0" - register "PcieRpEnable[11]" = "0" - # PCIe root port 13 TPU0 - register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" # RP 13 uses CLK SRC 2 register "PcieClkSrcUsage[2]" = "12" register "PcieClkSrcClkReq[2]" = "2" # PCIe root port 14 TPU1 - register "PcieRpEnable[13]" = "1" register "PcieRpLtrEnable[13]" = "1" # RP 14 uses CLK SRC 4 register "PcieClkSrcUsage[4]" = "13" register "PcieClkSrcClkReq[4]" = "4" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" - # GPIO for SD card detect register "sdcard_cd_gpio" = "vSD3_CD_B" diff --git a/src/mainboard/google/puff/variants/wyvern/overridetree.cb b/src/mainboard/google/puff/variants/wyvern/overridetree.cb index 60ba0bc..c484ead 100644 --- a/src/mainboard/google/puff/variants/wyvern/overridetree.cb +++ b/src/mainboard/google/puff/variants/wyvern/overridetree.cb @@ -185,10 +185,8 @@ }" # PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 93ec7cf..b71da0c 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -182,18 +182,15 @@ }" # PCIe port 10 for M.2 2230 WLAN - register "PcieRpEnable[9]" = "1" register "PcieClkSrcUsage[2]" = "9" register "PcieClkSrcClkReq[2]" = "2" # PCIe port 11 for card reader - register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" register "PcieClkSrcUsage[1]" = "10" register "PcieClkSrcClkReq[1]" = "1" # PCIe port 13 for M.2 2280 SSD - register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[4]" = "12" register "PcieClkSrcClkReq[4]" = "4" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index b216235..20672ef 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -182,23 +182,19 @@ }" # PCIe port 8 for Card Reader - register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[4]" = "7" register "PcieClkSrcClkReq[4]" = "4" # PCIe port 9 for LAN - register "PcieRpEnable[8]" = "1" register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN" register "PcieClkSrcClkReq[3]" = "3" # PCIe port 10 for M.2 2230 WLAN - register "PcieRpEnable[9]" = "1" register "PcieClkSrcUsage[1]" = "9" register "PcieClkSrcClkReq[1]" = "1" # PCIe port 13 for M.2 2280 SSD - register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[2]" = "12" register "PcieClkSrcClkReq[2]" = "2" diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 078deb2..d47cc57 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -112,28 +112,24 @@ # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" - # Enable NVMe PCIE 9 using clk 0 - register "PcieRpEnable[8]" = "1" + # NVMe PCIE 9 using clk 0 register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0" register "PcieRpSlotImplemented[8]" = "1" - # Enable Optane PCIE 11 using clk 0 - register "PcieRpEnable[10]" = "1" + # Optane PCIE 11 using clk 0 register "PcieRpLtrEnable[10]" = "1" register "HybridStorageMode" = "0" register "PcieRpSlotImplemented[10]" = "1" - # Enable SD Card PCIE 8 using clk 3 - register "PcieRpEnable[7]" = "1" + # SD Card PCIE 8 using clk 3 register "PcieRpLtrEnable[7]" = "1" register "PcieRpHotPlug[7]" = "1" register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcClkReq[3]" = "3" - # Enable WLAN PCIE 7 using clk 1 - register "PcieRpEnable[6]" = "1" + # WLAN PCIE 7 using clk 1 register "PcieRpLtrEnable[6]" = "1" register "PcieClkSrcUsage[1]" = "6" register "PcieClkSrcClkReq[1]" = "1" diff --git a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb index 28f72d7..53ed651 100644 --- a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb +++ b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb @@ -5,8 +5,7 @@ register "DdiPort2Hpd" = "0" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}" - # Enable EMMC PCIE 5 using clk 5 - register "PcieRpEnable[4]" = "1" + # EMMC PCIE 5 using clk 5 register "PcieRpLtrEnable[4]" = "1" register "PcieRpHotPlug[4]" = "1" register "PcieClkSrcUsage[5]" = "4" diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb index 2152ec4..4adf76a 100644 --- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb +++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb @@ -5,8 +5,7 @@ register "DdiPort2Hpd" = "0" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}" - # Enable EMMC PCIE 5 using clk 5 - register "PcieRpEnable[4]" = "1" + # EMMC PCIE 5 using clk 5 register "PcieRpLtrEnable[4]" = "1" register "PcieRpHotPlug[4]" = "1" register "PcieClkSrcUsage[5]" = "4" diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb index d101b5d..594df87 100644 --- a/src/mainboard/google/volteer/variants/voema/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -12,13 +12,11 @@ register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}" # Disable WLAN PCIE 7 - register "PcieRpEnable[6]" = "0" register "PcieRpLtrEnable[6]" = "0" register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" register "PcieRpSlotImplemented[6]" = "1" # Disable SD Card PCIE 8 - register "PcieRpEnable[7]" = "0" register "PcieRpLtrEnable[7]" = "0" register "PcieRpHotPlug[7]" = "0" register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" @@ -102,6 +100,8 @@ probe AUDIO MAX98360_ALC5682I_I2S probe AUDIO RT1011_ALC5682I_I2S end + device ref pcie_rp7 off end + device ref pcie_rp8 off end device ref pcie_rp9 on chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" diff --git a/src/mainboard/hp/280_g2/devicetree.cb b/src/mainboard/hp/280_g2/devicetree.cb index 3b25a42..77ec8f5 100644 --- a/src/mainboard/hp/280_g2/devicetree.cb +++ b/src/mainboard/hp/280_g2/devicetree.cb @@ -65,14 +65,12 @@ device ref uart2 on end device ref pcie_rp5 on # IT8893E PCI Bridge - register "PcieRpEnable[4]" = "1" register "PcieRpLtrEnable[4]" = "1" register "PcieRpAdvancedErrorReporting[4]" = "1" register "PcieRpClkSrcNumber[4]" = "11" end device ref pcie_rp6 on # PCIe x1 slot - register "PcieRpEnable[5]" = "1" register "PcieRpHotPlug[5]" = "1" register "PcieRpLtrEnable[5]" = "1" register "PcieRpAdvancedErrorReporting[5]" = "1" @@ -80,14 +78,12 @@ end device ref pcie_rp7 on # RTL8111 GbE NIC - register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" register "PcieRpAdvancedErrorReporting[6]" = "1" register "PcieRpClkSrcNumber[6]" = "10" end device ref pcie_rp8 on # M.2 2230 slot - register "PcieRpEnable[7]" = "1" register "PcieRpHotPlug[7]" = "1" register "PcieRpLtrEnable[7]" = "1" register "PcieRpAdvancedErrorReporting[7]" = "1" diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index 2c952bf..732c396 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -42,14 +42,6 @@ register "SkipCpuReplacementCheck" = "1" # PCIe root ports related UPDs - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieClkSrcUsage[0]" = "0x00" register "PcieClkSrcUsage[1]" = "0x06" register "PcieClkSrcUsage[2]" = "0x04" diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 957ab1d..2b01970 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -63,11 +63,6 @@ register "PchHdaAudioLinkDmicEnable[0]" = "1" register "PchHdaAudioLinkDmicEnable[1]" = "1" - # PCIe port 1 for M.2 E-key WLAN - # Enable Root Port 4(x4) for NVMe - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[4]" = "1" - # Enable ClkReqDetect 1 for WLAN # Enable ClkReqDetect 4 for NVMe register "PcieRpClkReqDetect[1]" = "1" diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 0d9331b..1b5c7c4 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -107,9 +107,6 @@ .voltage_limit = 1520, }" - # Enable Root port 1 and 5. - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[4]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqSupport[4]" = "1" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index f2234a6..ae0a355 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -102,19 +102,13 @@ }" # Enable x1 slot - register "PcieRpEnable[7]" = "1" register "PcieRpClkReqSupport[7]" = "1" register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3 # Enable x4 slot - register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4 - # Enable Root port 6 and 13. - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[12]" = "1" - # Enable CLKREQ# register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqSupport[12]" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 1af05c4..6a7db5f 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -37,10 +37,6 @@ # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[10]" = "1" register "PcieRpSlotImplemented[2]" = "1" register "PcieRpSlotImplemented[3]" = "1" register "PcieRpSlotImplemented[8]" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index ad1a45d..5960a3c 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -38,10 +38,6 @@ # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[10]" = "1" register "PcieRpSlotImplemented[2]" = "1" register "PcieRpSlotImplemented[3]" = "1" register "PcieRpSlotImplemented[8]" = "1" diff --git a/src/mainboard/kontron/bsl6/devicetree.cb b/src/mainboard/kontron/bsl6/devicetree.cb index 08b90ce..eef7105 100644 --- a/src/mainboard/kontron/bsl6/devicetree.cb +++ b/src/mainboard/kontron/bsl6/devicetree.cb @@ -87,15 +87,9 @@ [2] = 1, }" end - device ref pcie_rp9 on - register "PcieRpEnable[8]" = "1" - end - device ref pcie_rp10 on - register "PcieRpEnable[9]" = "1" - end - device ref pcie_rp11 on - register "PcieRpEnable[10]" = "1" - end + device ref pcie_rp9 on end + device ref pcie_rp10 on end + device ref pcie_rp11 on end device ref lpc_espi on register "serirq_mode" = "SERIRQ_CONTINUOUS" diff --git a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb index ecfcd6f..b38ad9d 100644 --- a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb +++ b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb @@ -1,13 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only chip soc/intel/skylake - # Enable Root port 1..4 (COMe 4..7), 12 (COMe 3) - register "PcieRpEnable[ 0]" = "1" - register "PcieRpEnable[ 1]" = "1" - register "PcieRpEnable[ 2]" = "1" - register "PcieRpEnable[ 3]" = "1" - register "PcieRpEnable[11]" = "1" - register "usb2_ports[5]" = "USB2_PORT_LONG(OC2)" register "usb2_ports[6]" = "USB2_PORT_LONG(OC3)" register "usb2_ports[7]" = "USB2_PORT_LONG(OC3)" @@ -21,6 +14,7 @@ register "SataPortsEnable[3]" = "1" device domain 0 on + # Root ports 1..4 (COMe 4..7), 12 (COMe 3) device ref pcie_rp1 on end device ref pcie_rp2 on end device ref pcie_rp3 on end diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index cdddf3d..e1c2b83 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -117,14 +117,6 @@ .voltage_limit = 1520, }" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - register "PcieRpClkSrcNumber[0]" = "0" register "PcieRpClkSrcNumber[3]" = "1" register "PcieRpClkSrcNumber[4]" = "2" diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index 024b97d..d358446 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -178,7 +178,6 @@ end # UART #2, in ACPI mode device pci 1b.4 on # PCIe root port 21 (Slot 1) smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X" - register "PcieRpEnable[20]" = "1" register "PcieRpLtrEnable[20]" = "1" register "PcieRpSlotImplemented[20]" = "1" register "PcieRpMaxPayload[20]" = "RpMaxPayload_256" @@ -187,7 +186,6 @@ end device pci 1c.0 on # PCIe root port 1 (Slot 3) smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X" - register "PcieRpEnable[0]" = "1" register "PcieRpLtrEnable[0]" = "1" register "PcieRpSlotImplemented[0]" = "1" register "PcieRpMaxPayload[0]" = "RpMaxPayload_256" @@ -195,28 +193,24 @@ register "PcieRpAspm[0]" = "AspmDisabled" end device pci 1c.4 on # PCIe root port 5 (PHY 3) - register "PcieRpEnable[4]" = "1" register "PcieRpLtrEnable[4]" = "1" device pci 00.0 on smbios_dev_info 3 end end device pci 1c.5 on # PCIe root port 6 (PHY 4) - register "PcieRpEnable[5]" = "1" register "PcieRpLtrEnable[5]" = "1" device pci 00.0 on smbios_dev_info 4 end end device pci 1c.6 on # PCIe root port 7 (PHY 2) - register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" device pci 00.0 on smbios_dev_info 2 end end device pci 1c.7 on # PCIe root port 8 (PHY 1) - register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" device pci 00.0 on smbios_dev_info 1 @@ -224,12 +218,10 @@ end device pci 1d.0 on # PCIe root port 9 (M2 M) smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X" - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieRpSlotImplemented[8]" = "1" end device pci 1d.5 on # PCIe root port 14 (PHY 0) - register "PcieRpEnable[13]" = "1" register "PcieRpLtrEnable[13]" = "1" device pci 00.0 on smbios_dev_info 0 @@ -239,13 +231,11 @@ device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2500 VGA end - register "PcieRpEnable[14]" = "1" register "PcieRpLtrEnable[14]" = "1" register "PcieRpSlotImplemented[14]" = "1" end device pci 1d.7 on # PCIe root port 16 (M.2 E/CNVi) # Disabled when CNVi is present - register "PcieRpEnable[15]" = "1" register "PcieRpLtrEnable[15]" = "1" register "PcieRpSlotImplemented[15]" = "1" end diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb index dd04aa9..00d0943 100644 --- a/src/mainboard/protectli/vault_cml/devicetree.cb +++ b/src/mainboard/protectli/vault_cml/devicetree.cb @@ -52,15 +52,6 @@ register "SataPortsEnable[0]" = "1" register "SataPortsEnable[2]" = "1" - register "PcieRpEnable[4]" = "1" # LAN1 - register "PcieRpEnable[5]" = "1" # LAN2 - register "PcieRpEnable[6]" = "1" # LAN3 - register "PcieRpEnable[7]" = "1" # LAN4 - register "PcieRpEnable[8]" = "1" # LAN5 - register "PcieRpEnable[9]" = "1" # LAN6 - register "PcieRpEnable[11]" = "1" # M.2 WiFi - register "PcieRpEnable[12]" = "1" # M.2 NVMe x4 - # Enable Advanced Error Reporting for RP 5-10, 12, 13 register "PcieRpAdvancedErrorReporting[4]" = "1" register "PcieRpAdvancedErrorReporting[5]" = "1" diff --git a/src/mainboard/protectli/vault_ehl/devicetree.cb b/src/mainboard/protectli/vault_ehl/devicetree.cb index d21383e..bfb7937 100644 --- a/src/mainboard/protectli/vault_ehl/devicetree.cb +++ b/src/mainboard/protectli/vault_ehl/devicetree.cb @@ -43,12 +43,6 @@ register "usb3_ports[3]" = "USB3_PORT_EMPTY" # PCIe root ports related UPDs - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 092115c..f615103 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -116,15 +116,7 @@ register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[1]" = "0" - # Enable Root ports. 1-6 for LAN and Root Port 9 - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[8]" = "1" # mPCIe WiFi - + # PCIe Root ports. 1-6 for LAN, 9 for mPCIe Wifi # Enable Advanced Error Reporting for RP 1-6, 9 register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpAdvancedErrorReporting[1]" = "1" diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb index ef35ac0..38b1b78 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb @@ -153,7 +153,6 @@ register "SataPortsDevSlp[2]" = "1" end device pci 1c.6 on # PCI Express Port 7 -- x1 M.2/E 2230 (WLAN) - register "PcieRpEnable[6]" = "1" register "PcieRpSlotImplemented[6]" = "1" register "PcieRpLtrEnable[6]" = "1" register "PcieRpHotPlug[6]" = "1" @@ -163,12 +162,10 @@ end device pci 1c.7 on # PCI Express Port 8 device pci 00.0 on end # x1 (LAN) - register "PcieRpEnable[7]" = "1" register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcClkReq[3]" = "3" end device pci 1d.0 on # PCI Express Port 9 -- x4 M.2/M 2280 (NVMe) - register "PcieRpEnable[8]" = "1" register "PcieRpSlotImplemented[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[0]" = "8" @@ -176,7 +173,6 @@ smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" end device pci 1d.4 on # PCI Express Port 13 -- x4 M.2/M 2280 (NVMe) - register "PcieRpEnable[12]" = "1" register "PcieRpSlotImplemented[12]" = "1" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[1]" = "12" diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb index cab254a..2b3a25c 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb @@ -130,7 +130,6 @@ end device pci 1c.7 on # PCI Express Port 8 -- x1 M.2/E 2230 (WLAN) register "PcieRpSlotImplemented[7]" = "1" - register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" # ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC register "PcieClkSrcUsage[2]" = "0x80" @@ -138,13 +137,11 @@ end device pci 1d.1 on # PCI Express Port 10 device pci 00.0 on end # x1 (LAN) - register "PcieRpEnable[9]" = "1" register "PcieClkSrcUsage[3]" = "9" register "PcieClkSrcClkReq[3]" = "3" end device pci 1d.4 on # PCI Express Port 13 -- x4 M.2/M 2280 (NVMe) register "PcieRpSlotImplemented[12]" = "1" - register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[1]" = "12" register "PcieClkSrcClkReq[1]" = "1" diff --git a/src/mainboard/purism/librem_jsl/devicetree.cb b/src/mainboard/purism/librem_jsl/devicetree.cb index e3b3be2..c992c4f 100644 --- a/src/mainboard/purism/librem_jsl/devicetree.cb +++ b/src/mainboard/purism/librem_jsl/devicetree.cb @@ -159,7 +159,6 @@ device pci 1c.0 off end # PCI Express Root Port 1 device pci 1c.1 off end # PCI Express Root Port 2 device pci 1c.2 on # PCI Express Root Port 3 - M.2 M-key, PCIe only - register "PcieRpEnable[2]" = "true" register "PcieClkSrcUsage[0]" = "2" register "PcieClkSrcClkReq[0]" = "0" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth2X" diff --git a/src/mainboard/purism/librem_l1um_v2/devicetree.cb b/src/mainboard/purism/librem_l1um_v2/devicetree.cb index 0144f22..480d51c 100644 --- a/src/mainboard/purism/librem_l1um_v2/devicetree.cb +++ b/src/mainboard/purism/librem_l1um_v2/devicetree.cb @@ -212,20 +212,17 @@ end # SATA device pci 1b.4 on # PCI Express Port 21 - PCIE5 register "PcieRpSlotImplemented[20]" = "1" - register "PcieRpEnable[20]" = "1" register "PcieRpLtrEnable[20]" = "1" register "PcieClkSrcUsage[10]" = "20" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "PCIE5" "SlotDataBusWidth4X" end device pci 1c.0 on # PCI Express Port 1 - M2_1 register "PcieRpSlotImplemented[0]" = "1" - register "PcieRpEnable[0]" = "1" register "PcieRpLtrEnable[0]" = "1" register "PcieClkSrcUsage[1]" = "0x80" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_1" "SlotDataBusWidth4X" end device pci 1d.0 on # PCI Express Port 9 - GbE #1 - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[14]" = "8" # Type indexes are needed for systemd to use "onboard" names by default @@ -238,12 +235,10 @@ end end device pci 1d.1 on # PCI Express Port 10 - BMC video - register "PcieRpEnable[9]" = "1" register "PcieRpLtrEnable[9]" = "1" register "PcieClkSrcUsage[8]" = "9" end device pci 1d.2 on # PCI Express Port 11 - GbE #2 - register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" register "PcieClkSrcUsage[11]" = "10" device pci 00.0 on diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 1928d15..5cfc8dd 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -137,10 +137,6 @@ .dc_loadline = 420, }" - # Enable Root Ports 5 and 9 - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[8]" = "1" - # PL2 override 25W register "power_limits_config" = "{ .tdp_pl2_override = 25, diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 1323164..6a40461 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -115,11 +115,6 @@ .dc_loadline = 310, }" - # Enable Root Ports 3, 5 and 9 - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpLtrEnable[2]" = "1" register "PcieRpLtrEnable[4]" = "1" register "PcieRpLtrEnable[8]" = "1" diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb index 8d6c589..fb5ccc2 100644 --- a/src/mainboard/siemens/chili/variants/base/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -70,20 +70,17 @@ device pci 1c.3 off end # PCI Express Port 4 device pci 1c.4 on # PCI Express Port 5 device pci 00.0 on end # x1 i219 - register "PcieRpEnable[4]" = "1" register "PcieClkSrcUsage[4]" = "0x70" register "PcieClkSrcClkReq[4]" = "4" register "PcieRpSlotImplemented[4]" = "0" end device pci 1c.5 on # PCI Express Port 6 device pci 00.0 on end # x1 i210 - register "PcieRpEnable[5]" = "1" register "PcieClkSrcUsage[5]" = "5" register "PcieClkSrcClkReq[5]" = "5" register "PcieRpSlotImplemented[5]" = "0" end device pci 1c.6 on # PCI Express Port 7 - register "PcieRpEnable[6]" = "1" register "PcieRpSlotImplemented[6]" = "1" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X" end @@ -97,7 +94,6 @@ device pci 1d.6 off end # PCI Express Port 15 device pci 1d.7 off end # PCI Express Port 16 device pci 1b.0 on # PCI Express Port 17 - register "PcieRpEnable[16]" = "1" register "PcieClkSrcUsage[7]" = "16" register "PcieClkSrcClkReq[7]" = "7" register "PcieRpSlotImplemented[16]" = "1" diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb index cee1967..33d23c9 100644 --- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb @@ -108,37 +108,32 @@ device pci 19.1 off end # I2C #5 device pci 19.2 off end # UART #2 device pci 1a.0 off end # eMMC - device pci 1c.0 off # PCI Express Port 1 - register "PcieRpEnable[0]" = "0" # Debug (x1) + device pci 1c.0 off # PCI Express Port 1: Debug (x1) register "PcieClkSrcUsage[2]" = "0" register "PcieClkSrcClkReq[2]" = "2" end device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on # PCI Express Port 5 - register "PcieRpEnable[4]" = "1" # CORE (x1) + device pci 1c.4 on # PCI Express Port 5: CORE (x1) register "PcieClkSrcUsage[4]" = "4" register "PcieClkSrcClkReq[4]" = "4" register "PcieRpSlotImplemented[4]" = "1" end device pci 1c.5 on # PCI Express Port 6 device pci 00.0 on end # i210 (x1) - register "PcieRpEnable[5]" = "1" register "PcieClkSrcUsage[5]" = "5" register "PcieClkSrcClkReq[5]" = "5" register "PcieRpSlotImplemented[5]" = "0" end device pci 1c.6 on # PCI Express Port 7 device pci 00.0 on end # VL805 Front Rack/UIB (x1) - register "PcieRpEnable[6]" = "1" register "PcieClkSrcUsage[1]" = "6" register "PcieClkSrcClkReq[1]" = "1" register "PcieRpSlotImplemented[6]" = "0" end device pci 1c.7 on # PCI Express Port 8 device pci 00.0 on end # VL805 Back MB (x1) - register "PcieRpEnable[7]" = "1" register "PcieClkSrcUsage[0]" = "7" register "PcieClkSrcClkReq[0]" = "0" register "PcieRpSlotImplemented[7]" = "0" @@ -151,8 +146,7 @@ device pci 1d.5 off end # PCI Express Port 14 device pci 1d.6 off end # PCI Express Port 15 device pci 1d.7 off end # PCI Express Port 16 - device pci 1b.0 on # PCI Express Port 17 - register "PcieRpEnable[16]" = "1" # NVMe (x4) + device pci 1b.0 on # PCI Express Port 17: NVMe (x4) register "PcieClkSrcUsage[7]" = "16" register "PcieClkSrcClkReq[7]" = "7" register "PcieRpSlotImplemented[16]" = "1" diff --git a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/devicetree.cb b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/devicetree.cb index 5bc3931..5c6cbc0 100644 --- a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/devicetree.cb +++ b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/devicetree.cb @@ -40,9 +40,6 @@ register "SkipCpuReplacementCheck" = "1" # PCIe root ports related UPDs - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index 6994e8c..60c4b47 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -40,12 +40,6 @@ register "SkipCpuReplacementCheck" = "1" # PCIe root ports related UPDs - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE" diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index f14c225..abad9c7 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -40,9 +40,6 @@ register "SkipCpuReplacementCheck" = "1" # PCIe root ports related UPDs - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb index 9a0142c..3f44616 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb @@ -40,10 +40,6 @@ register "SkipCpuReplacementCheck" = "1" # PCIe root ports related UPDs - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE" diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb index e99dd48..17d6780 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb @@ -40,12 +40,6 @@ register "SkipCpuReplacementCheck" = "1" # PCIe root ports related UPDs - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE" diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb index 53ea1f6..43697be 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb @@ -40,9 +40,6 @@ register "SkipCpuReplacementCheck" = "1" # PCIe root ports related UPDs - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb index 9a71015..ad0c141 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb @@ -131,7 +131,6 @@ device pci 1c.7 off end # PCI Express Port 8 device pci 1d.0 on # PCI Express Port 9 (SSD x4) register "PcieRpSlotImplemented[8]" = "1" - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[1]" = "0x08" register "PcieClkSrcClkReq[1]" = "1" diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb index 44ffb41..d3c654d 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb @@ -96,7 +96,6 @@ end device ref uart2 on end device ref pcie_rp6 on - register "PcieRpEnable[5]" = "1" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "4" register "PcieRpClkSrcNumber[5]" = "4" @@ -106,7 +105,6 @@ end end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "0" register "PcieRpClkSrcNumber[8]" = "0" diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb index b870ec1..2b7c4f8 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb @@ -133,7 +133,6 @@ device ref uart2 on end device ref pcie_rp9 on register "HybridStorageMode" = "0" - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[3]" = "0x08" register "PcieClkSrcClkReq[3]" = "3" diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb index 98bfb04..e1d7fae 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb @@ -51,34 +51,27 @@ end device ref igpu on end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "1" device pci 00.0 on end # GbE end device ref pcie_rp2 on - register "PcieRpEnable[1]" = "1" device pci 00.0 on end # GbE end device ref pcie_rp3 on - register "PcieRpEnable[2]" = "1" device pci 00.0 on end # GbE end device ref pcie_rp4 on - register "PcieRpEnable[3]" = "1" device pci 00.0 on end # GbE end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth2X" end device ref pcie_rp7 on - register "PcieRpEnable[6]" = "1" device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2400 VGA end end device ref pcie_rp9 on # Slot JPCIE1 - register "PcieRpEnable[8]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device ref lpc_espi on diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index b46b220..37dbd85 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -43,12 +43,10 @@ device ref peg0 on end # unused device ref peg1 on # Slot JPCIE1 - register "PcieRpEnable[0]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X" end device ref pcie_rp1 on # Slot JPCIE1 - register "PcieRpEnable[2]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X" end device ref pcie_rp3 on @@ -57,12 +55,10 @@ end end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "1" device pci 00.0 on end # 10GbE device pci 00.1 on end # 10GbE end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X" end device ref lpc_espi on diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index 29252fe..0166595 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -46,20 +46,17 @@ end device ref pcie_rp1 on # Slot JPCIE4 - register "PcieRpEnable[0]" = "1" register "PcieRpLtrEnable[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device ref pcie_rp5 on # Slot JPCIE5 - register "PcieRpEnable[4]" = "1" register "PcieRpLtrEnable[4]" = "1" register "PcieRpAdvancedErrorReporting[4]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieRpAdvancedErrorReporting[8]" = "1" device pci 00.0 on # GbE 1 @@ -67,7 +64,6 @@ end end device ref pcie_rp10 on - register "PcieRpEnable[9]" = "1" register "PcieRpLtrEnable[9]" = "1" register "PcieRpAdvancedErrorReporting[9]" = "1" device pci 00.0 on # GbE 2 @@ -75,7 +71,6 @@ end end device ref pcie_rp11 on - register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" register "PcieRpAdvancedErrorReporting[10]" = "1" device pci 00.0 on # Aspeed PCI Bridge diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb index 29babda..db1bd0a 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb @@ -47,24 +47,19 @@ smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT1 PCI-E 3.0 X16" "SlotDataBusWidth16X" end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "1" device pci 00.0 on end # GbE end device ref pcie_rp2 on - register "PcieRpEnable[1]" = "1" device pci 00.0 on end # GbE end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X" end device ref pcie_rp9 on # Slot JSXB2 - register "PcieRpEnable[8]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthShort" "PCH SLOT2 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device ref pcie_rp13 on - register "PcieRpEnable[12]" = "1" device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2400 VGA end diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb index 529767c..7ddce87 100644 --- a/src/mainboard/system76/addw1/devicetree.cb +++ b/src/mainboard/system76/addw1/devicetree.cb @@ -114,7 +114,6 @@ device pci 1a.0 off end # eMMC device pci 1b.0 on # PCI Express Port 17 # PCI Express root port #17 x4, Clock 0 (Thunderbolt) - register "PcieRpEnable[16]" = "1" register "PcieRpLtrEnable[16]" = "1" register "PcieRpHotPlug[16]" = "1" register "PcieClkSrcUsage[0]" = "16" @@ -125,7 +124,6 @@ device pci 1b.3 off end # PCI Express Port 20 device pci 1b.4 on # PCI Express Port 21 # PCI Express root port #21 x4, Clock 10 (SSD2) - register "PcieRpEnable[20]" = "1" register "PcieRpLtrEnable[20]" = "1" register "PcieClkSrcUsage[10]" = "20" register "PcieClkSrcClkReq[10]" = "10" @@ -144,7 +142,6 @@ device pci 1c.7 off end # PCI Express Port 8 device pci 1d.0 on # PCI Express Port 9 # PCI Express root port #9 x4, Clock 9 (SSD1) - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[9]" = "8" register "PcieClkSrcClkReq[9]" = "9" @@ -156,7 +153,6 @@ device pci 1d.4 off end # PCI Express Port 13 device pci 1d.5 on # PCI Express Port 14 # PCI Express root port #14 x1, Clock 5 (GLAN) - register "PcieRpEnable[13]" = "1" register "PcieRpLtrEnable[13]" = "1" register "PcieClkSrcUsage[5]" = "13" register "PcieClkSrcClkReq[5]" = "5" @@ -164,7 +160,6 @@ end device pci 1d.6 on # PCI Express Port 15 # PCI Express root port #15 x1, Clock 7 (Card Reader) - register "PcieRpEnable[14]" = "1" register "PcieRpLtrEnable[14]" = "1" register "PcieClkSrcUsage[7]" = "14" register "PcieClkSrcClkReq[7]" = "7" @@ -172,7 +167,6 @@ end device pci 1d.7 on # PCI Express Port 16 # PCI Express root port #16 x1, Clock 6 (WLAN) - register "PcieRpEnable[15]" = "1" register "PcieRpLtrEnable[15]" = "1" register "PcieClkSrcUsage[6]" = "15" register "PcieClkSrcClkReq[6]" = "6" diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb index d79aa76..9d79cce 100644 --- a/src/mainboard/system76/bonw14/devicetree.cb +++ b/src/mainboard/system76/bonw14/devicetree.cb @@ -131,7 +131,6 @@ device pci 1a.0 off end # eMMC device pci 1b.0 on # PCI Express Port 17 # PCI Express root port #17 x4, Clock 14 (SSD2) - register "PcieRpEnable[16]" = "1" register "PcieRpLtrEnable[16]" = "1" register "PcieClkSrcUsage[14]" = "16" register "PcieClkSrcClkReq[14]" = "14" @@ -141,7 +140,6 @@ device pci 1b.3 off end # PCI Express Port 20 device pci 1b.4 on # PCI Express Port 21 # PCI Express root port #21 x4, Clock 15 (SSD3) - register "PcieRpEnable[20]" = "1" register "PcieRpLtrEnable[20]" = "1" register "PcieClkSrcUsage[15]" = "20" register "PcieClkSrcClkReq[15]" = "15" @@ -151,7 +149,6 @@ device pci 1b.7 off end # PCI Express Port 24 device pci 1c.0 on # PCI Express Port 1 # PCI Express root port #1 x4, Clock 6 (Thunderbolt) - register "PcieRpEnable[0]" = "1" register "PcieRpLtrEnable[0]" = "1" register "PcieRpHotPlug[0]" = "1" register "PcieClkSrcUsage[6]" = "PCIE_CLK_RP0" # 0 is converted to PCIE_CLK_NOTUSED @@ -162,7 +159,6 @@ device pci 1c.3 off end # PCI Express Port 4 device pci 1c.4 on # PCI Express Port 5 # PCI Express root port #5 x4, Clock 10 (USB 3.2) - register "PcieRpEnable[4]" = "1" register "PcieRpLtrEnable[4]" = "1" register "PcieClkSrcUsage[10]" = "4" register "PcieClkSrcClkReq[10]" = "10" @@ -172,7 +168,6 @@ device pci 1c.7 off end # PCI Express Port 8 device pci 1d.0 on # PCI Express Port 9 # PCI Express root port #9 x4, Clock 8 (SSD) - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[8]" = "8" register "PcieClkSrcClkReq[8]" = "8" @@ -182,21 +177,18 @@ device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on # PCI Express Port 13 # PCI Express root port #13 x1, Clock 0 (WLAN) - register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[0]" = "12" register "PcieClkSrcClkReq[0]" = "0" end device pci 1d.5 on # PCI Express Port 14 # PCI Express root port #14 x1, Clock 1 (GLAN) - register "PcieRpEnable[13]" = "1" register "PcieRpLtrEnable[13]" = "1" register "PcieClkSrcUsage[1]" = "13" register "PcieClkSrcClkReq[1]" = "1" end device pci 1d.6 on # PCI Express Port 15 # PCI Express root port #15 x1, Clock 4 (Card Reader) - register "PcieRpEnable[14]" = "1" register "PcieRpLtrEnable[14]" = "1" register "PcieClkSrcUsage[4]" = "14" register "PcieClkSrcClkReq[4]" = "4" diff --git a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb index b349762..d0fce6c 100644 --- a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb @@ -38,7 +38,6 @@ end device pci 1c.4 on # PCI Express Port 5 # PCI Express Root port #5 x4, Clock 4 (TBT) - register "PcieRpEnable[4]" = "1" register "PcieRpLtrEnable[4]" = "1" register "PcieRpHotPlug[4]" = "1" register "PcieClkSrcUsage[4]" = "4" @@ -46,21 +45,18 @@ end device pci 1d.0 on # PCI Express Port 9 # PCI Express Root port #9 x1, Clock 3 (LAN) - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[3]" = "8" register "PcieClkSrcClkReq[3]" = "3" end device pci 1d.1 on # PCI Express Port 10 # PCI Express Root port #10 x1, Clock 2 (WLAN) - register "PcieRpEnable[9]" = "1" register "PcieRpLtrEnable[9]" = "0" register "PcieClkSrcUsage[2]" = "9" register "PcieClkSrcClkReq[2]" = "2" end device pci 1d.4 on # PCI Express Port 13 # PCI Express Root port #13 x4, Clock 5 (NVMe) - register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[5]" = "12" register "PcieClkSrcClkReq[5]" = "5" diff --git a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb index bbfc2ea..61f3bd1 100644 --- a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb @@ -31,7 +31,6 @@ end device pci 1c.4 on # PCI Express Port 5 # PCI Express Root port #5 x4, Clock 4 (TBT) - register "PcieRpEnable[4]" = "1" register "PcieRpLtrEnable[4]" = "1" register "PcieRpHotPlug[4]" = "1" register "PcieClkSrcUsage[4]" = "4" @@ -39,21 +38,18 @@ end device pci 1d.0 on # PCI Express Port 9 # PCI Express Root port #9 x1, Clock 3 (LAN) - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[3]" = "8" register "PcieClkSrcClkReq[3]" = "3" end device pci 1d.1 on # PCI Express Port 10 # PCI Express Root port #10 x1, Clock 2 (WLAN) - register "PcieRpEnable[9]" = "1" register "PcieRpLtrEnable[9]" = "0" register "PcieClkSrcUsage[2]" = "9" register "PcieClkSrcClkReq[2]" = "2" end device pci 1d.4 on # PCI Express Port 13 # PCI Express Root port #13 x4, Clock 5 (NVMe) - register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[5]" = "12" register "PcieClkSrcClkReq[5]" = "5" diff --git a/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb index 164774a..92bb1b8 100644 --- a/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb @@ -39,7 +39,6 @@ end device pci 1c.5 on # PCI Express Port 6 device pci 00.0 on end # x1 Card reader - register "PcieRpEnable[5]" = "1" register "PcieRpLtrEnable[5]" = "1" register "PcieClkSrcUsage[3]" = "5" register "PcieClkSrcClkReq[3]" = "3" @@ -47,7 +46,6 @@ end device pci 1c.7 on # PCI Express Port 8 device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1) - register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[2]" = "7" register "PcieClkSrcClkReq[2]" = "2" @@ -59,7 +57,6 @@ end device pci 1d.0 on # PCI Express Port 9 device pci 00.0 on end # x4 M.2/M 2280 (J_SSD2) - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[4]" = "8" register "PcieClkSrcClkReq[4]" = "4" @@ -68,7 +65,6 @@ end device pci 1d.4 on # PCI Express Port 13 device pci 00.0 on end # x4 M.2/M 2280 (J_SSD1) - register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[5]" = "12" register "PcieClkSrcClkReq[5]" = "5" diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index 4ae412d..a4eaca9 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -117,7 +117,6 @@ device pci 1b.3 off end # PCI Express Port 20 device pci 1b.4 on # PCI Express Port 21 # PCI Express root port #21 x4, Clock 11 (SSD2) - register "PcieRpEnable[20]" = "1" register "PcieRpLtrEnable[20]" = "1" register "PcieClkSrcUsage[11]" = "20" register "PcieClkSrcClkReq[11]" = "11" @@ -136,7 +135,6 @@ device pci 1c.7 off end # PCI Express Port 8 device pci 1d.0 on # PCI Express Port 9 # PCI Express root port #9 x4, Clock 10 (SSD) - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[10]" = "8" register "PcieClkSrcClkReq[10]" = "10" @@ -148,7 +146,6 @@ device pci 1d.4 off end # PCI Express Port 13 device pci 1d.5 on # PCI Express Port 14 # PCI Express root port #14 x1, Clock 6 (WLAN) - register "PcieRpEnable[13]" = "1" register "PcieRpLtrEnable[13]" = "1" register "PcieClkSrcUsage[6]" = "13" register "PcieClkSrcClkReq[6]" = "6" @@ -156,7 +153,6 @@ end device pci 1d.6 on # PCI Express Port 15 # PCI Express root port #15 x1, Clock 5 (LAN) - register "PcieRpEnable[14]" = "1" register "PcieRpLtrEnable[14]" = "1" register "PcieClkSrcUsage[5]" = "14" register "PcieClkSrcClkReq[5]" = "5" diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb index 3b84d7f..5be84dc 100644 --- a/src/mainboard/system76/kbl-u/devicetree.cb +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -137,7 +137,6 @@ end device ref pcie_rp1 on # Root port #1 x4 (TBT) - register "PcieRpEnable[0]" = "1" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "4" register "PcieRpClkSrcNumber[0]" = "4" @@ -147,7 +146,6 @@ end device ref pcie_rp5 on # Root port #5 x1 (LAN) - register "PcieRpEnable[4]" = "1" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" @@ -156,7 +154,6 @@ end device ref pcie_rp6 on # Root port #6 x1 (WLAN) - register "PcieRpEnable[5]" = "1" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "2" register "PcieRpClkSrcNumber[5]" = "2" @@ -165,7 +162,6 @@ end device ref pcie_rp9 on # Root port #9 x4 (NVMe) - register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "5" register "PcieRpClkSrcNumber[8]" = "5" diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index f17862f..b671c11 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -130,7 +130,6 @@ device pci 1b.3 off end # PCI Express Port 20 device pci 1b.4 on # PCI Express Port 21 # PCI Express root port #21 x4, Clock 11 (SSD2) - register "PcieRpEnable[20]" = "1" register "PcieRpLtrEnable[20]" = "1" register "PcieClkSrcUsage[11]" = "20" register "PcieClkSrcClkReq[11]" = "11" @@ -148,7 +147,6 @@ device pci 1c.7 off end # PCI Express Port 8 device pci 1d.0 on # PCI Express Port 9 # PCI Express root port #9 x4, Clock 12 (SSD) - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[12]" = "8" register "PcieClkSrcClkReq[12]" = "12" @@ -159,21 +157,18 @@ device pci 1d.4 off end # PCI Express Port 13 device pci 1d.5 on # PCI Express Port 14 # PCI Express root port #14 x1, Clock 13 (WLAN) - register "PcieRpEnable[13]" = "1" register "PcieRpLtrEnable[13]" = "1" register "PcieClkSrcUsage[13]" = "13" register "PcieClkSrcClkReq[13]" = "13" end device pci 1d.6 on # PCI Express Port 15 # PCI Express root port #15 x1, Clock 14 (GLAN) - register "PcieRpEnable[14]" = "1" register "PcieRpLtrEnable[14]" = "1" register "PcieClkSrcUsage[14]" = "14" register "PcieClkSrcClkReq[14]" = "14" end device pci 1d.7 on # PCI Express Port 16 # PCI Express root port #16 x1, Clock 15 (Card Reader) - register "PcieRpEnable[15]" = "1" register "PcieRpLtrEnable[15]" = "1" register "PcieClkSrcUsage[15]" = "15" register "PcieClkSrcClkReq[15]" = "15" diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index c0c1b4a..a261bbd 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -125,7 +125,6 @@ device pci 1a.0 off end # eMMC device pci 1b.0 on # PCI Express Port 17 # PCI Express root port #17 x4, Clock 0 (Thunderbolt) - register "PcieRpEnable[16]" = "1" register "PcieRpLtrEnable[16]" = "1" register "PcieRpHotPlug[16]" = "1" register "PcieClkSrcUsage[0]" = "16" @@ -137,7 +136,6 @@ device pci 1b.3 off end # PCI Express Port 20 device pci 1b.4 on # PCI Express Port 21 # PCI Express root port #21 x4, Clock 11 (SSD2) - register "PcieRpEnable[20]" = "1" register "PcieRpLtrEnable[20]" = "1" register "PcieClkSrcUsage[11]" = "20" register "PcieClkSrcClkReq[11]" = "11" @@ -156,7 +154,6 @@ device pci 1c.7 off end # PCI Express Port 8 device pci 1d.0 on # PCI Express Port 9 # PCI Express root port #9 x4, Clock 12 (SSD1) - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[12]" = "8" register "PcieClkSrcClkReq[12]" = "12" @@ -168,7 +165,6 @@ device pci 1d.4 off end # PCI Express Port 13 device pci 1d.5 on # PCI Express Port 14 # PCI Express root port #14 x1, Clock 7 (GLAN) - register "PcieRpEnable[13]" = "1" register "PcieRpLtrEnable[13]" = "1" register "PcieClkSrcUsage[7]" = "13" register "PcieClkSrcClkReq[7]" = "7" @@ -176,7 +172,6 @@ end device pci 1d.6 on # PCI Express Port 15 # PCI Express root port #15 x1, Clock 9 (Card Reader) - register "PcieRpEnable[14]" = "1" register "PcieRpLtrEnable[14]" = "1" register "PcieClkSrcUsage[9]" = "14" register "PcieClkSrcClkReq[9]" = "9" @@ -184,7 +179,6 @@ end device pci 1d.7 on # PCI Express Port 16 # PCI Express root port #16 x1, Clock 6 (WLAN) - register "PcieRpEnable[15]" = "1" register "PcieRpLtrEnable[15]" = "1" register "PcieClkSrcUsage[6]" = "15" register "PcieClkSrcClkReq[6]" = "6" diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb index d03bd2e..ad90eab 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb @@ -53,21 +53,18 @@ end device ref pcie_rp5 on # PCIe root port #5 x1, Clock 5 (GLAN) - register "PcieRpEnable[4]" = "1" register "PcieRpLtrEnable[4]" = "1" register "PcieClkSrcUsage[5]" = "4" register "PcieClkSrcClkReq[5]" = "5" end device ref pcie_rp7 on # PCIe root port #7 x1, Clock 7 (CARD) - register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" register "PcieClkSrcUsage[7]" = "6" register "PcieClkSrcClkReq[7]" = "7" end device ref pcie_rp8 on # PCIe root port #8 x1, Clock 8 (WLAN) - register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[8]" = "7" register "PcieClkSrcClkReq[8]" = "8" @@ -75,7 +72,6 @@ end device ref pcie_rp9 on # PCIe root port #9 x4, Clock 9 (SSD1) - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[9]" = "8" register "PcieClkSrcClkReq[9]" = "9" diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb index b463fe7..bfbc5c5 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb @@ -53,21 +53,18 @@ end device ref pcie_rp5 on # PCIe root port #5 x1, Clock 8 (GLAN) - register "PcieRpEnable[4]" = "1" register "PcieRpLtrEnable[4]" = "1" #register "PcieClkSrcUsage[8]" = "4" register "PcieClkSrcClkReq[8]" = "8" end device ref pcie_rp7 on # PCIe root port #7 x1, Clock 3 (CARD) - register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" register "PcieClkSrcUsage[3]" = "6" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp8 on # PCIe root port #8 x1, Clock 2 (WLAN) - register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[2]" = "7" register "PcieClkSrcClkReq[2]" = "2" @@ -75,7 +72,6 @@ end device ref pcie_rp9 on # PCIe root port #9 x4, Clock 10 (SSD2) - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[10]" = "8" register "PcieClkSrcClkReq[10]" = "10" diff --git a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb index 6f25d7b..a09cf30 100644 --- a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb @@ -62,21 +62,18 @@ end device ref pcie_rp5 on # PCIe root port #5 x1, Clock 8 (GLAN) - register "PcieRpEnable[4]" = "1" register "PcieRpLtrEnable[4]" = "1" register "PcieClkSrcUsage[8]" = "4" register "PcieClkSrcClkReq[8]" = "8" end device ref pcie_rp6 on # PCIe root port #6 x1, Clock 10 (CARD) - register "PcieRpEnable[5]" = "1" register "PcieRpLtrEnable[5]" = "1" register "PcieClkSrcUsage[10]" = "5" register "PcieClkSrcClkReq[10]" = "10" end device ref pcie_rp8 on # PCIe root port #8 x1, Clock 2 (WLAN) - register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[2]" = "7" register "PcieClkSrcClkReq[2]" = "2" @@ -84,7 +81,6 @@ end device ref pcie_rp9 on # PCIe root port #9 x4, Clock 6 (SSD2) - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[6]" = "8" register "PcieClkSrcClkReq[6]" = "6" diff --git a/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb b/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb index 9a669ef..a35dc52 100644 --- a/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb +++ b/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb @@ -141,14 +141,12 @@ end device ref pcie_rp6 on # PCIe root port #6 x1, Clock 2 (CARD) - register "PcieRpEnable[5]" = "1" register "PcieRpLtrEnable[5]" = "1" register "PcieClkSrcUsage[2]" = "5" register "PcieClkSrcClkReq[2]" = "2" end device ref pcie_rp7 on # PCIe root port #7 x1, Clock 3 (GLAN) - register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" register "PcieClkSrcUsage[3]" = "6" register "PcieClkSrcClkReq[3]" = "3" @@ -161,7 +159,6 @@ end device ref pcie_rp8 on # PCIe root port #8 x1, Clock 1 (WLAN) - register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[1]" = "7" register "PcieClkSrcClkReq[1]" = "1" @@ -169,7 +166,6 @@ end device ref pcie_rp9 on # PCIe root port #9 x4, Clock 4 (SSD0) - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[4]" = "8" register "PcieClkSrcClkReq[4]" = "4" diff --git a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb index 7c3475e..075a2e4 100644 --- a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb +++ b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb @@ -141,7 +141,6 @@ end device ref pcie_rp5 on # PCIe root port #5 x4, Clock 2 (NVIDIA GPU) - register "PcieRpEnable[4]" = "1" register "PcieRpLtrEnable[4]" = "1" register "PcieClkSrcUsage[2]" = "4" register "PcieClkSrcClkReq[2]" = "2" @@ -158,14 +157,12 @@ end device ref pcie_rp9 on # PCIe root port #9 x1, Clock 3 (CARD) - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[3]" = "8" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp10 on # PCIe root port #10 x1, Clock 4 (GLAN) - register "PcieRpEnable[9]" = "1" register "PcieRpLtrEnable[9]" = "1" register "PcieClkSrcUsage[4]" = "9" register "PcieClkSrcClkReq[4]" = "4" @@ -178,7 +175,6 @@ end device ref pcie_rp11 on # PCIe root port #11 x1, Clock 1 (WLAN) - register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" register "PcieClkSrcUsage[1]" = "10" register "PcieClkSrcClkReq[1]" = "1" diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb b/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb index 671cdc4..ce45079 100644 --- a/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb +++ b/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb @@ -118,7 +118,6 @@ end device ref pcie_rp3 on # PCIe root port #3 x1, Clock 1 (WLAN) - register "PcieRpEnable[2]" = "1" register "PcieRpLtrEnable[2]" = "1" register "PcieClkSrcUsage[1]" = "2" register "PcieClkSrcClkReq[1]" = "1" @@ -126,7 +125,6 @@ end device ref pcie_rp6 on # PCIe root port #6 x1, Clock 2 (CARD) - register "PcieRpEnable[5]" = "1" register "PcieRpLtrEnable[5]" = "1" register "PcieClkSrcUsage[2]" = "5" register "PcieClkSrcClkReq[2]" = "2" @@ -134,7 +132,6 @@ device ref pcie_rp9 on # PCIe root port #9 x4, Clock 0 (SSD2) # Despite the name, SSD1_CLKREQ# is used for SSD2 - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0" diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb index 0899f62..098ebe6 100644 --- a/src/mainboard/system76/whl-u/devicetree.cb +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -120,7 +120,6 @@ device pci 1c.3 off end # PCI Express Port 4 device pci 1c.4 on # PCI Express Port 5 # PCI Express Root port #5 x4, Clock 4 (TBT) - register "PcieRpEnable[4]" = "1" register "PcieRpLtrEnable[4]" = "1" register "PcieRpHotPlug[4]" = "1" register "PcieClkSrcUsage[4]" = "4" @@ -131,14 +130,12 @@ device pci 1c.7 off end # PCI Express Port 8 device pci 1d.0 on # PCI Express Port 9 # PCI Express Root port #9 x1, Clock 3 (LAN) - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[3]" = "8" register "PcieClkSrcClkReq[3]" = "3" end device pci 1d.1 on # PCI Express Port 10 # PCI Express Root port #10 x1, Clock 2 (WLAN) - register "PcieRpEnable[9]" = "1" register "PcieRpLtrEnable[9]" = "0" register "PcieClkSrcUsage[2]" = "9" register "PcieClkSrcClkReq[2]" = "2" @@ -147,7 +144,6 @@ device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on # PCI Express Port 13 # PCI Express Root port #13 x4, Clock 5 (NVMe) - register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[5]" = "12" register "PcieClkSrcClkReq[5]" = "5" -- To view, visit https://review.coreboot.org/c/coreboot/+/79935?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9641a1ed241084f37089094b2392c29e2ac0fd95 Gerrit-Change-Number: 79935 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: Makefile.inc: Enable Wxor-used-as-pow command option
by Elyes Haouas (Code Review) 13 Jan '24

13 Jan '24

Elyes Haouas has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/79915?usp=email ) Change subject: Makefile.inc: Enable Wxor-used-as-pow command option ...................................................................... Abandoned Wxor-used-as-pow is enabled by default using gcc or clang. -- To view, visit https://review.coreboot.org/c/coreboot/+/79915?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6ae83c676ab347510f5dfa7d34a7b04ee439e9b6 Gerrit-Change-Number: 79915 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: abandon

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[S] Change in coreboot[main]: mb/google/brox: Enable Elan trackpad
by Shelley Chen (Code Review) 13 Jan '24

13 Jan '24

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79892?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/brox: Enable Elan trackpad ...................................................................... mb/google/brox: Enable Elan trackpad BUG=b:311450057,b:300690448 BRANCH=None TEST=to be tested on a device with i2cdetect Change-Id: If6da1c722e87a50c6d422b300f16a52d884fa08f Signed-off-by: Shelley Chen <shchen(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79892 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb 1 file changed, 10 insertions(+), 0 deletions(-) Approvals: Nick Vaccaro: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index 552164a..f824473 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -168,6 +168,16 @@ device generic 0 on end end end + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E3_IRQ)" + register "wake" = "GPE0_DW2_03" + register "detect" = "1" + device i2c 0x15 on end + end + end #I2C0 device ref i2c4 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" -- To view, visit https://review.coreboot.org/c/coreboot/+/79892?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If6da1c722e87a50c6d422b300f16a52d884fa08f Gerrit-Change-Number: 79892 Gerrit-PatchSet: 4 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/google/brox: Configure vGPIOs for NVMe
by Shelley Chen (Code Review) 13 Jan '24

13 Jan '24

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79857?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/brox: Configure vGPIOs for NVMe ...................................................................... mb/google/brox: Configure vGPIOs for NVMe This is needed for NVMe to work when PCIe device is connected to the CPU side of RPL soc. BUG=b:311450057,b:300690448, b:319058143 BRANCH=None TEST=Tested on device and was able to boot to the OS Change-Id: Ic8a1fdcedf2ec6c7bf1dd00e02ef7c13e9338aac Signed-off-by: Shelley Chen <shchen(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79857 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/gpio.c 1 file changed, 22 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c index 7a988e1..5c4f613 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c @@ -395,6 +395,28 @@ PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF2), /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_S0, NONE, DEEP), + + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), }; static const struct pad_config romstage_gpio_table[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/79857?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic8a1fdcedf2ec6c7bf1dd00e02ef7c13e9338aac Gerrit-Change-Number: 79857 Gerrit-PatchSet: 5 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/brox: Disable package c state demotion
by Shelley Chen (Code Review) 13 Jan '24

13 Jan '24

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79855?usp=email ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/brox: Disable package c state demotion ...................................................................... mb/google/brox: Disable package c state demotion This needs to be disabled for RPL otherwise we'll hit the assertion: [EMERG] ASSERTION ERROR: file 'src/soc/intel/alderlake/fsp_params.c', line 1066 There is a comment in the referenced file/line in the assertion that says that "C state demotion must be disabled for Raptorlake J0 and Q0 SKUs." So, disabling it. BUG=b:311450057,b:300690448 BRANCH=None TEST=Tested that we didn't hit this assertion on the device after this change Change-Id: Ib7b2484de2d84c980550fd951f1e30efab0ee197 Signed-off-by: Shelley Chen <shchen(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79855 Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index 23db754..552164a 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -14,6 +14,10 @@ # S0ix enable register "s0ix_enable" = "1" + # Disable package C state demotion on Raptorlake as a W/A for S0ix issues + # seen on J0 and Q0 SKUs + register "disable_package_c_state_demotion" = "1" + # DPTF enable register "dptf_enable" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/79855?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib7b2484de2d84c980550fd951f1e30efab0ee197 Gerrit-Change-Number: 79855 Gerrit-PatchSet: 6 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/google/brox: Enable WLAN on root port 5
by Shelley Chen (Code Review) 13 Jan '24

13 Jan '24

Attention is currently required from: Paul Menzel. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79888?usp=email ) Change subject: mb/google/brox: Enable WLAN on root port 5 ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79888/comment/1390bb9e_797b0b2d : PS2, Line 7: mb/google/brox: Enable WLAN > … on root port X Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79888?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I361bef13ebd073b6fccb729a1960d3832cf2681a Gerrit-Change-Number: 79888 Gerrit-PatchSet: 4 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 13 Jan 2024 01:28:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/brox: Enable WLAN on root port 5
by Shelley Chen (Code Review) 13 Jan '24

13 Jan '24

Attention is currently required from: Shelley Chen. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79888?usp=email to look at the new patch set (#4). Change subject: mb/google/brox: Enable WLAN on root port 5 ...................................................................... mb/google/brox: Enable WLAN on root port 5 BUG=b:311450057,b:300690448 BRANCH=None TEST=to be tested on device with lspci Change-Id: I361bef13ebd073b6fccb729a1960d3832cf2681a Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/brox/variants/brox/overridetree.cb 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/79888/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/79888?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I361bef13ebd073b6fccb729a1960d3832cf2681a Gerrit-Change-Number: 79888 Gerrit-PatchSet: 4 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/brox: Disable package c state demotion
by Shelley Chen (Code Review) 13 Jan '24

13 Jan '24

Attention is currently required from: Paul Menzel. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79855?usp=email ) Change subject: mb/google/brox: Disable package c state demotion ...................................................................... Patch Set 5: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79855/comment/20821514_10a3720a : PS2, Line 7: Disable package c state demotion > … unsupported on RPL Done. Clarified in the body of the commit. https://review.coreboot.org/c/coreboot/+/79855/comment/dc2565bb_b8e4d5dc : PS2, Line 11: [EMERG] ASSERTION ERROR: file 'src/soc/intel/alderlake/fsp_params.c', : line 1066 > Maybe also describe, what that assertion checks, and why it’s there. Done https://review.coreboot.org/c/coreboot/+/79855/comment/e879729c_b7917dc8 : PS2, Line 11: [EMERG] ASSERTION ERROR: file 'src/soc/intel/alderlake/fsp_params.c', : line 1066 > I’d put it in one line and indent it with four spaces. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79855?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib7b2484de2d84c980550fd951f1e30efab0ee197 Gerrit-Change-Number: 79855 Gerrit-PatchSet: 5 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 13 Jan 2024 01:21:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brox: Disable package c state demotion
by Shelley Chen (Code Review) 13 Jan '24

13 Jan '24

Attention is currently required from: Shelley Chen. Hello Eric Lai, Nick Vaccaro, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79855?usp=email to look at the new patch set (#5). Change subject: mb/google/brox: Disable package c state demotion ...................................................................... mb/google/brox: Disable package c state demotion This needs to be disabled for RPL otherwise we'll hit the assertion: [EMERG] ASSERTION ERROR: file 'src/soc/intel/alderlake/fsp_params.c', line 1066 There is a comment in the referenced file/line in the assertion that says that "C state demotion must be disabled for Raptorlake J0 and Q0 SKUs." So, disabling it. BUG=b:311450057,b:300690448 BRANCH=None TEST=Tested that we didn't hit this assertion on the device after this change Change-Id: Ib7b2484de2d84c980550fd951f1e30efab0ee197 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/79855/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/79855?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib7b2484de2d84c980550fd951f1e30efab0ee197 Gerrit-Change-Number: 79855 Gerrit-PatchSet: 5 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/pcengines/apu2: don't enable IOMMU
by Felix Held (Code Review) 13 Jan '24

13 Jan '24

Attention is currently required from: Krystian Hebel, Michał Żygowski, Paul Menzel, Piotr Król. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79896?usp=email ) Change subject: mb/pcengines/apu2: don't enable IOMMU ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79896/comment/5ae696dc_96fe77d8 : PS1, Line 11: Linux kernel > Which version? re-tested and added this info to the commit message. the same issue showed up with all kernel versions i ever remember testing with -- To view, visit https://review.coreboot.org/c/coreboot/+/79896?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If74a7c64f53903fec0c01a55e1b202e800f02986 Gerrit-Change-Number: 79896 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Mike Banon <mikebdp2(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Sat, 13 Jan 2024 00:00:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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coreboot-gerrit January 2024