coreboot-gerrit January 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: sb/intel/i82801{i,j}x/chip.h: Use boolean where appropriate
by Felix Singer (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Alexander Couzens, Elyes Haouas, Felix Held, Nicholas Chin, Stefan Ott. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77738?usp=email ) Change subject: sb/intel/i82801{i,j}x/chip.h: Use boolean where appropriate ...................................................................... Patch Set 8: Code-Review+2 (4 comments) File src/southbridge/intel/i82801ix/chip.h: https://review.coreboot.org/c/coreboot/+/77738/comment/01679a5e_5d06f5c9 : PS4, Line 59: unsigned int sata_clock_request : 1; : u > I need to look into these. Done https://review.coreboot.org/c/coreboot/+/77738/comment/7fec1183_d544a84b : PS4, Line 77: uint8_t pcie_hotplug_map[8]; > This should be bool as well. Done File src/southbridge/intel/i82801jx/chip.h: https://review.coreboot.org/c/coreboot/+/77738/comment/7c4a2597_dd175e6b : PS4, Line 46: unsigned int sata_clock_request : 1; > Sounds like it could be bool. I need to look into it. Done https://review.coreboot.org/c/coreboot/+/77738/comment/ec37852b_039ff61c : PS4, Line 63: uint8_t pcie_hotplug_map[8]; > This should be bool as well. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/77738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I867451ae3d6d37033c9e0e57a4d7fd4a06dedbef Gerrit-Change-Number: 77738 Gerrit-PatchSet: 8 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 12 Jan 2024 19:13:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel/i82801{i,j}x/chip.h: Use boolean where appropriate
by Felix Singer (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Alexander Couzens, Elyes Haouas, Felix Singer, Nicholas Chin, Stefan Ott. Felix Singer has uploaded a new patch set (#8) to the change originally created by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/77738?usp=email ) Change subject: sb/intel/i82801{i,j}x/chip.h: Use boolean where appropriate ...................................................................... sb/intel/i82801{i,j}x/chip.h: Use boolean where appropriate Use the boolean type instead of integers for appropriate attributes. Change-Id: I867451ae3d6d37033c9e0e57a4d7fd4a06dedbef Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/southbridge/intel/i82801ix/chip.h M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/chip.h M src/southbridge/intel/i82801jx/lpc.c 4 files changed, 17 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/77738/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/77738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I867451ae3d6d37033c9e0e57a4d7fd4a06dedbef Gerrit-Change-Number: 77738 Gerrit-PatchSet: 8 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: sb/intel/i82801{i,j}x/chip.h: Use boolean where appropriate
by Felix Singer (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Alexander Couzens, Elyes Haouas, Felix Singer, Nicholas Chin, Stefan Ott. Felix Singer has uploaded a new patch set (#7) to the change originally created by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/77738?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: sb/intel/i82801{i,j}x/chip.h: Use boolean where appropriate ...................................................................... sb/intel/i82801{i,j}x/chip.h: Use boolean where appropriate Use the boolean type instead of integers for appropriate attributes. Change-Id: I867451ae3d6d37033c9e0e57a4d7fd4a06dedbef Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/southbridge/intel/i82801ix/chip.h M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/chip.h M src/southbridge/intel/i82801jx/lpc.c 4 files changed, 14 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/77738/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/77738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I867451ae3d6d37033c9e0e57a4d7fd4a06dedbef Gerrit-Change-Number: 77738 Gerrit-PatchSet: 7 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/cavium/cn81xx/Kconfig: specify ECAM_MMCONF_BUS_NUMBER
by Felix Held (Code Review) 12 Jan '24

12 Jan '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79931?usp=email ) Change subject: soc/cavium/cn81xx/Kconfig: specify ECAM_MMCONF_BUS_NUMBER ...................................................................... soc/cavium/cn81xx/Kconfig: specify ECAM_MMCONF_BUS_NUMBER The Cavium CN82xx SoC selects ECAM_MMCONF_SUPPORT, but doesn't set a value for ECAM_MMCONF_BUS_NUMBER which results in it defaulting to 0 which is wrong. Unsure what the correct value would be here, so set it to the maximum of 256 buses that a system with a single PCI segment group can have and add a TODO. This will be at least less wrong than the previous solution. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ic98381e2cc597cf23af249c71911545692e40f64 --- M src/soc/cavium/cn81xx/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/79931/1 diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig index 368581f..68de1bc 100644 --- a/src/soc/cavium/cn81xx/Kconfig +++ b/src/soc/cavium/cn81xx/Kconfig @@ -39,4 +39,8 @@ config ECAM_MMCONF_BASE_ADDRESS default 0x848000000000 +# TODO: is this ECAM MMCONF bus number correct? +config ECAM_MMCONF_BUS_NUMBER + default 256 + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/79931?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic98381e2cc597cf23af249c71911545692e40f64 Gerrit-Change-Number: 79931 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: lint/kconfig_lint: Remove SOUTH_BRIDGE_OPTIONS
by Felix Singer (Code Review) 12 Jan '24

12 Jan '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79913?usp=email ) Change subject: lint/kconfig_lint: Remove SOUTH_BRIDGE_OPTIONS ...................................................................... lint/kconfig_lint: Remove SOUTH_BRIDGE_OPTIONS SOUTH_BRIDGE_OPTIONS Kconfig symbol is no longer used. Change-Id: I2380f1ce48afd191755d8b3dcab0b51909f5231f Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79913 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M util/lint/kconfig_lint 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Felix Singer: Looks good to me, approved diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint index 523fa3e..e67aebd 100755 --- a/util/lint/kconfig_lint +++ b/util/lint/kconfig_lint @@ -46,7 +46,7 @@ my @collected_symbols; # my %selected_symbols; # list of symbols that are enabled by a select statement -my $exclude_unused = '_SPECIFIC_OPTIONS|SOUTH_BRIDGE_OPTIONS'; +my $exclude_unused = '_SPECIFIC_OPTIONS'; Main(); -- To view, visit https://review.coreboot.org/c/coreboot/+/79913?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2380f1ce48afd191755d8b3dcab0b51909f5231f Gerrit-Change-Number: 79913 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: sb/intel/bd82x6x: Remove dummy SOUTH_BRIDGE_OPTIONS Kconfig symbol
by Felix Singer (Code Review) 12 Jan '24

12 Jan '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77532?usp=email ) Change subject: sb/intel/bd82x6x: Remove dummy SOUTH_BRIDGE_OPTIONS Kconfig symbol ...................................................................... sb/intel/bd82x6x: Remove dummy SOUTH_BRIDGE_OPTIONS Kconfig symbol Change-Id: If4ae9c800325f5de8f170f8922bacffad1c9bb20 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77532 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/southbridge/intel/bd82x6x/Kconfig 1 file changed, 12 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Felix Singer: Looks good to me, approved diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 41732bd..1a578dd 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -1,15 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only -config SOUTHBRIDGE_INTEL_BD82X6X - bool - -config SOUTHBRIDGE_INTEL_C216 - bool - -if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216 - -config SOUTH_BRIDGE_OPTIONS - def_bool y +config SOUTHBRIDGE_INTEL_BD82X6X_COMMON + def_bool n select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES @@ -39,6 +31,16 @@ select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG select TCO_SPACE_NOT_YET_SPLIT +config SOUTHBRIDGE_INTEL_BD82X6X + bool + select SOUTHBRIDGE_INTEL_BD82X6X_COMMON + +config SOUTHBRIDGE_INTEL_C216 + bool + select SOUTHBRIDGE_INTEL_BD82X6X_COMMON + +if SOUTHBRIDGE_INTEL_BD82X6X_COMMON + config EHCI_BAR hex default 0xfef00000 -- To view, visit https://review.coreboot.org/c/coreboot/+/77532?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If4ae9c800325f5de8f170f8922bacffad1c9bb20 Gerrit-Change-Number: 77532 Gerrit-PatchSet: 10 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: device: Add support for multiple PCI segment groups
by Felix Held (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Cliff Huang, Fred Reitberger, Jason Glenesk, Lance Zhao, Matt DeVillier, Nico Huber, Patrick Rudolph, Tim Wawrzynczak. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79927?usp=email ) Change subject: device: Add support for multiple PCI segment groups ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > oh, now the boards selecting NO_ECAM_MMCONF_SUPPORT fail to build; hadn't thought about that case Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79927?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied3313c41896362dd989ee2ab1b1bcdced840aa8 Gerrit-Change-Number: 79927 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 12 Jan 2024 17:58:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: device: Add support for multiple PCI segment groups
by Felix Held (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Cliff Huang, Fred Reitberger, Jason Glenesk, Lance Zhao, Matt DeVillier, Nico Huber, Patrick Rudolph, Tim Wawrzynczak. Hello Cliff Huang, Fred Reitberger, Jason Glenesk, Lance Zhao, Matt DeVillier, Nico Huber, Patrick Rudolph, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79927?usp=email to look at the new patch set (#6). Change subject: device: Add support for multiple PCI segment groups ...................................................................... device: Add support for multiple PCI segment groups Add initial support for multiple PCI segment groups. Instead of modifying secondary in the bus struct introduce a new variable and keep existing common code. Since all platforms currently only use 1 segment this is not a functional change. On platforms that support more than 1 segment the segment has to be set when creating the PCI domain. Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ied3313c41896362dd989ee2ab1b1bcdced840aa8 --- M src/acpi/acpi.c M src/device/Kconfig M src/device/device.c M src/device/device_const.c M src/device/device_util.c M src/device/pci_device.c M src/include/device/device.h M src/include/device/pci_def.h M src/include/device/pci_ops.h M src/lib/smbios.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/soc/amd/common/block/acpi/ivrs.c M src/soc/amd/common/block/data_fabric/domain.c M src/soc/amd/genoa_poc/domain.c 14 files changed, 85 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/79927/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/79927?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied3313c41896362dd989ee2ab1b1bcdced840aa8 Gerrit-Change-Number: 79927 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/intel/tigerlake: Drop redundant PcieRpEnable
by Subrata Banik (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Nick Vaccaro, Nico Huber. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79920?usp=email ) Change subject: soc/intel/tigerlake: Drop redundant PcieRpEnable ...................................................................... Patch Set 1: -Code-Review (1 comment) Patchset: PS1: https://qa.coreboot.org/job/coreboot-gerrit/250491/testReport/junit/(root)/… build is unhappy due to missing `PcieRpEnable` chip references -- To view, visit https://review.coreboot.org/c/coreboot/+/79920?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iacfef5f032278919f1fcf49e31fa42bcbf1eaf20 Gerrit-Change-Number: 79920 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 12 Jan 2024 17:35:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/tigerlake: Drop redundant PcieRpEnable
by Subrata Banik (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Nick Vaccaro, Nico Huber. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79920?usp=email ) Change subject: soc/intel/tigerlake: Drop redundant PcieRpEnable ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79920?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iacfef5f032278919f1fcf49e31fa42bcbf1eaf20 Gerrit-Change-Number: 79920 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 12 Jan 2024 17:33:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit January 2024