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Change subject: lint/kconfig_lint: Remove SOUTH_BRIDGE_OPTIONS
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Patch Set 1: Code-Review+2
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Change subject: sb/intel/bd82x6x: Remove dummy SOUTH_BRIDGE_OPTIONS Kconfig symbol
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Patch Set 9: Code-Review+2
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Change subject: [WIP] device/device_util: TODO look into is_pci_dev_on_bus
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Abandoned
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Change subject: [WIP] device/device_util: TODO look into is_pci_dev_on_bus
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Patch Set 3:
(1 comment)
File src/device/device_util.c:
https://review.coreboot.org/c/coreboot/+/79928/comment/4fa68f84_54687daa :
PS3, Line 985: is_pci_dev_on_bus
> looks like it's only used on platforms that expect 1 PCI segment group.
ok, i added a check to make sure that the segment group is 0 and squashed that into the main patch
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Hello Cliff Huang, Fred Reitberger, Jason Glenesk, Lance Zhao, Matt DeVillier, Patrick Rudolph, Tim Wawrzynczak, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/79927?usp=email
to look at the new patch set (#4).
The following approvals got outdated and were removed:
Code-Review+2 by Patrick Rudolph, Verified+1 by build bot (Jenkins)
The change is no longer submittable: Code-Review and Verified are unsatisfied now.
Change subject: device: Add support for multiple PCI segment groups
......................................................................
device: Add support for multiple PCI segment groups
Add initial support for multiple PCI segment groups.
Instead of modifying secondary in the bus struct introduce a
new variable and keep existing common code.
Since all platforms currently only use 1 segment this is not a
functional change. On platforms that support more than 1 segment
the segment has to be set when creating the PCI domain.
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ied3313c41896362dd989ee2ab1b1bcdced840aa8
---
M src/acpi/acpi.c
M src/device/Kconfig
M src/device/device.c
M src/device/device_const.c
M src/device/device_util.c
M src/device/pci_device.c
M src/include/device/device.h
M src/include/device/pci_def.h
M src/include/device/pci_ops.h
M src/lib/smbios.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/soc/amd/common/block/acpi/ivrs.c
M src/soc/amd/common/block/data_fabric/domain.c
M src/soc/amd/genoa_poc/domain.c
14 files changed, 72 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/79927/4
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Change subject: lint/kconfig_lint: Remove SOUTH_BRIDGE_OPTIONS
......................................................................
Patch Set 1: Code-Review+1
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Change subject: mb/google/nissa/var/craaskov: Update RAM ID table
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Patch Set 1: Code-Review+1
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79914/comment/6f391fd0_245253cb :
PS1, Line 7: Update RAM ID table
Please be more specific. Maybe:
> Add Micron MT62F1G32D4DR-031 to mem_parts
https://review.coreboot.org/c/coreboot/+/79914/comment/834ba476_eac0ed7d :
PS1, Line 10:
Please mention, that it’s ID 2 somewhere.
https://review.coreboot.org/c/coreboot/+/79914/comment/80c8c498_9c8c0d03 :
PS1, Line 11: DRAM Part Name ID to assign
: MT62F512M32D2DR-031 WT:B 0 (0000)
: H9JCNNNBK3MLYR-N6E 0 (0000)
: K3LKBKB0BM-MGCP 1 (0001)
: H9JCNNNCP3MLYR-N6E 2 (0010)
: MT62F1G32D4DR-031 WT:B 2 (0010)
Why paste this?
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