coreboot-gerrit January 2024

coreboot-gerrit@coreboot.org

1 participants
3043 discussions

[S] Change in coreboot[main]: device/Kconfig: Add an option to allocate above 4G by default
by Lean Sheng Tan (Code Review) 12 Jan '24

12 Jan '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78331?usp=email ) ( 18 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: device/Kconfig: Add an option to allocate above 4G by default ...................................................................... device/Kconfig: Add an option to allocate above 4G by default Historically resource allocation in coreboot was 32bit x86 thing. To remain compatible with this behavior (e.g. to keep 32bit payloads happy), resource allocation limits resources to 32 bits unless explicitly overridden. However this behavior is not always appropriate: e.g. on non x86 platforms the PCIe mem decode window could be above 4G. Another case on x86 is where the decode window(s) below 4G are not adequate for fitting all resources and the payload is 64bit capable (e.g. Linux). This adds a Kconfig flag to override the behavior to limit resources to 32bit by default and to allocate resources according to the real hardware limits. TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I01218a8a3efc4a5f8ba344808949ca6b8898525f Reviewed-on: https://review.coreboot.org/c/coreboot/+/78331 Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/device/Kconfig M src/device/resource_allocator_v4.c 2 files changed, 10 insertions(+), 0 deletions(-) Approvals: Nico Huber: Looks good to me, but someone else must approve build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Shuo Liu: Looks good to me, but someone else must approve diff --git a/src/device/Kconfig b/src/device/Kconfig index 83afa8c..374427a 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -1005,6 +1005,13 @@ undeclared resources. EDK2 is currently reported to also have problems on some platforms, at least with Intel's IGD. +config ALWAYS_ALLOW_ABOVE_4G_ALLOCATION + bool + default n if ARCH_X86 + default y + help + Don't limit mem resources to 4G, but to their actual limit. + config XHCI_UTILS def_bool n help diff --git a/src/device/resource_allocator_v4.c b/src/device/resource_allocator_v4.c index 96d4488..73ec9c1 100644 --- a/src/device/resource_allocator_v4.c +++ b/src/device/resource_allocator_v4.c @@ -84,6 +84,9 @@ static resource_t effective_limit(const struct resource *const res) { + if (CONFIG(ALWAYS_ALLOW_ABOVE_4G_ALLOCATION)) + return res->limit; + /* Always allow bridge resources above 4G. */ if (res->flags & IORESOURCE_BRIDGE) return res->limit; -- To view, visit https://review.coreboot.org/c/coreboot/+/78331?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I01218a8a3efc4a5f8ba344808949ca6b8898525f Gerrit-Change-Number: 78331 Gerrit-PatchSet: 20 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[main]: mb/google/geralt: Enable BOE_NV110WUM_L60 panel for Ciri
by Ruihai Zhou (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu, cong yang, ot_hao.han(a)mediatek.com. Ruihai Zhou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78957?usp=email ) Change subject: mb/google/geralt: Enable BOE_NV110WUM_L60 panel for Ciri ...................................................................... Patch Set 13: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78957/comment/d7e88f4c_22d6c145 : PS12, Line 10: > Please explain the `mdelay(10)` change in the commit message. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78957?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0a04f062f81c543d38716d7ff185b5633c1aa3a9 Gerrit-Change-Number: 78957 Gerrit-PatchSet: 13 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: ot_hao.han(a)mediatek.com <ot_hao.han(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: ot_hao.han(a)mediatek.com <ot_hao.han(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Fri, 12 Jan 2024 09:32:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: mb/google/geralt: Enable BOE_NV110WUM_L60 panel for Ciri
by Ruihai Zhou (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Ruihai Zhou, cong yang, ot_hao.han(a)mediatek.com. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), cong yang, ot_hao.han(a)mediatek.com, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78957?usp=email to look at the new patch set (#13). Change subject: mb/google/geralt: Enable BOE_NV110WUM_L60 panel for Ciri ...................................................................... mb/google/geralt: Enable BOE_NV110WUM_L60 panel for Ciri The MIPI panel BOE_NV110WUM_L60 will be used for Ciri, enable it. Also remove the `mdelay(10)` after mtk_i2c_bus_init, because MTK confirms this is not needed. Add mdelay(2) between VDD18 and VSP/VSN to meet the panel datasheet. BUG=b:308968270 TEST=Boot to firmware screen BRANCH=None Change-Id: I0a04f062f81c543d38716d7ff185b5633c1aa3a9 Signed-off-by: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/geralt/Kconfig M src/mainboard/google/geralt/Makefile.inc M src/mainboard/google/geralt/panel.c M src/mainboard/google/geralt/panel.h A src/mainboard/google/geralt/panel_ciri.c M src/mainboard/google/geralt/panel_geralt.c 6 files changed, 76 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/78957/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/78957?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0a04f062f81c543d38716d7ff185b5633c1aa3a9 Gerrit-Change-Number: 78957 Gerrit-PatchSet: 13 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: ot_hao.han(a)mediatek.com <ot_hao.han(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: ot_hao.han(a)mediatek.com <ot_hao.han(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[main]: drivers/mipi: Update init code for BOE_NV110WUM_L60
by Yu-Ping Wu (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Ruihai Zhou. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79897?usp=email ) Change subject: drivers/mipi: Update init code for BOE_NV110WUM_L60 ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79897?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f068ba0ec9dede3e3361b55c38a8eca8793905a Gerrit-Change-Number: 79897 Gerrit-PatchSet: 4 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Fri, 12 Jan 2024 09:23:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: mb/google/geralt: Enable IVO_T109NW41 MIPI panel for Ciri
by Yu-Ping Wu (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Hung-Te Lin, Ruihai Zhou, cong yang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79845?usp=email ) Change subject: mb/google/geralt: Enable IVO_T109NW41 MIPI panel for Ciri ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79845?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9dc2228d39bb8bb048d1f37727c96b0ad621e912 Gerrit-Change-Number: 79845 Gerrit-PatchSet: 5 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Fri, 12 Jan 2024 09:23:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: mb/google/geralt: Enable BOE_NV110WUM_L60 panel for Ciri
by Yu-Ping Wu (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Ruihai Zhou, cong yang, ot_hao.han(a)mediatek.com. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78957?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/geralt: Enable BOE_NV110WUM_L60 panel for Ciri ...................................................................... Patch Set 12: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78957/comment/6c13d5c8_28ac390c : PS12, Line 10: Please explain the `mdelay(10)` change in the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/78957?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0a04f062f81c543d38716d7ff185b5633c1aa3a9 Gerrit-Change-Number: 78957 Gerrit-PatchSet: 12 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: ot_hao.han(a)mediatek.com <ot_hao.han(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: ot_hao.han(a)mediatek.com <ot_hao.han(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Fri, 12 Jan 2024 09:22:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: mb/google/nissa/var/craaskov: Update RAM ID table
by Ian Feng (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Eric Lai, Nick Vaccaro, Subrata Banik. Ian Feng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79914?usp=email ) Change subject: mb/google/nissa/var/craaskov: Update RAM ID table ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/79914?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e54958490228beb7039d531c709d56ec244b9e7 Gerrit-Change-Number: 79914 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 12 Jan 2024 09:08:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: mb/google/nissa/var/craaskov: Update RAM ID table
by Ian Feng (Code Review) 12 Jan '24

12 Jan '24

Ian Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79914?usp=email ) Change subject: mb/google/nissa/var/craaskov: Update RAM ID table ...................................................................... mb/google/nissa/var/craaskov: Update RAM ID table Add new memory Micron MT62F1G32D4DR-031 WT:B. DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H9JCNNNBK3MLYR-N6E 0 (0000) K3LKBKB0BM-MGCP 1 (0001) H9JCNNNCP3MLYR-N6E 2 (0010) MT62F1G32D4DR-031 WT:B 2 (0010) BUG=b:319778218 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I9e54958490228beb7039d531c709d56ec244b9e7 Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/craaskov/memory/Makefile.inc M src/mainboard/google/brya/variants/craaskov/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/craaskov/memory/mem_parts_used.txt 3 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/79914/1 diff --git a/src/mainboard/google/brya/variants/craaskov/memory/Makefile.inc b/src/mainboard/google/brya/variants/craaskov/memory/Makefile.inc index 1f61b57..11778cf 100644 --- a/src/mainboard/google/brya/variants/craaskov/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/craaskov/memory/Makefile.inc @@ -6,4 +6,4 @@ SPD_SOURCES = SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 1(0b0001) Parts = K3LKBKB0BM-MGCP -SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 2(0b0010) Parts = H9JCNNNCP3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 2(0b0010) Parts = H9JCNNNCP3MLYR-N6E, MT62F1G32D4DR-031 WT:B diff --git a/src/mainboard/google/brya/variants/craaskov/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/craaskov/memory/dram_id.generated.txt index d659743..5438504 100644 --- a/src/mainboard/google/brya/variants/craaskov/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/craaskov/memory/dram_id.generated.txt @@ -8,3 +8,4 @@ H9JCNNNBK3MLYR-N6E 0 (0000) K3LKBKB0BM-MGCP 1 (0001) H9JCNNNCP3MLYR-N6E 2 (0010) +MT62F1G32D4DR-031 WT:B 2 (0010) diff --git a/src/mainboard/google/brya/variants/craaskov/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/craaskov/memory/mem_parts_used.txt index 126d067..6a61490 100644 --- a/src/mainboard/google/brya/variants/craaskov/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/craaskov/memory/mem_parts_used.txt @@ -13,3 +13,4 @@ H9JCNNNBK3MLYR-N6E K3LKBKB0BM-MGCP H9JCNNNCP3MLYR-N6E +MT62F1G32D4DR-031 WT:B -- To view, visit https://review.coreboot.org/c/coreboot/+/79914?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e54958490228beb7039d531c709d56ec244b9e7 Gerrit-Change-Number: 79914 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: mb/google/geralt: Enable BOE_NV110WUM_L60 panel for Ciri
by Yidi Lin (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Ruihai Zhou, Yu-Ping Wu, cong yang, ot_hao.han(a)mediatek.com. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78957?usp=email ) Change subject: mb/google/geralt: Enable BOE_NV110WUM_L60 panel for Ciri ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78957?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0a04f062f81c543d38716d7ff185b5633c1aa3a9 Gerrit-Change-Number: 78957 Gerrit-PatchSet: 12 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: ot_hao.han(a)mediatek.com <ot_hao.han(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: ot_hao.han(a)mediatek.com <ot_hao.han(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Fri, 12 Jan 2024 08:48:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: [WIP] device/device_util: TODO look into is_pci_dev_on_bus
by Patrick Rudolph (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Felix Held. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79928?usp=email ) Change subject: [WIP] device/device_util: TODO look into is_pci_dev_on_bus ...................................................................... Patch Set 3: (1 comment) File src/device/device_util.c: https://review.coreboot.org/c/coreboot/+/79928/comment/12a35217_5ce21997 : PS3, Line 985: is_pci_dev_on_bus looks like it's only used on platforms that expect 1 PCI segment group. -- To view, visit https://review.coreboot.org/c/coreboot/+/79928?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I74219f2db407c107e3e7dcae1ee11b2c91225fbf Gerrit-Change-Number: 79928 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 12 Jan 2024 08:47:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2024